TITLE MICROCIRCUIT, LINEAR, FAULT-PROTECTED RS-485 TRANSCEIVERS WITH EXTENDED COMMON-MODE RANGE, MONOLITHIC SILICON REVISIONS

Transcription

1 REVISIONS TR ESRIPTION TE PPROVE Prepared in accordance with SME Y14.24 Vendor item drawing REV PGE REV PGE REV STTUS OF PGES REV PGE PMI N/ PREPRE Y Phu H. Nguyen N N MRITIME Original date of drawing YY MM HEKE Y Phu H. Nguyen PPROVE Y Thomas M. Hess TITE MIROIRUIT, INER, FUT-PROTETE RS-485 TRNSEIVERS WITH EXTENE OMMON-MOE RNGE, MONOITHI SIION OE IENT. NO. REV PGE 1 OF 14 MS N/ 5962-V074-13

2 1. SOPE 1.1 Scope. This drawing documents the general requirements of a high performance fault protected RS-485 transceivers with extended common mode range microcircuit, with an operating temperature range of -55 to Vendor Item rawing dministrative ontrol Number. The manufacturer s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: evice type(s) X E rawing evice type ase outline ead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) evice type Generic ircuit function 01 SN65HV1792-EP Fault protected RS-485 transceivers with extended common mode range ase outline(s). The case outlines are as specified herein. Outline letter Number of pins JEE PU 95 Package style X 14 JEE MS-012- Plastic Small Outline Package ead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator E Z Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other N N MRITIME REV PGE 2

3 1.3 bsolute maximum ratings. 1/ Supply voltage, (V ) V to 7. Voltage range at bus pins (, pins) to 7 Input voltage range at any logic pin to V + 0. Transient overvoltage pulse through 100 Ω per TI to 10 Receiver output current m to 24 m Junction temperature, (T J) IE ES (human body model), bus terminals and GN... ±16 kv JEE standard 22: Test method 114 (human body model), bus terminal and GN... ±16 kv Test method 114 (human body model), all pins... ±4 kv Test method 101 (charged-device model), all pins... ±2 kv Test method 115 (machine model), all pins... ±40 ontinuous total power dissipation Package ase outline X JEE thermal model T < 25 Rating erating factor bove T = 25 T = 25 Rating T = 105 Rating High-K 1315 mw 10.5 mw/ 684 mw 474 mw ow-k 744 mw 6 mw/ 387 mw 268 mw 1.4 Thermal characteristics. Thermal metric 2/ ase outline X Units Junction to ambient thermal resistance, θ J 3/ 70.8 /W Junction to case (top) thermal resistance, θ Jtop 4/ 29.4 Junction to board thermal resistance, θ J 5/ 25.3 Junction to top characterization parameter, Ψ JT 6/ 8.2 Junction to board characterization parameter, Ψ J 7/ 25 Junction to case (bottom) thermal resistance, θ Jbot 8/ N/ 1/ Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2/ For more information about traditional and new thermal metrics, see manufacturer data. 3/ The junction to ambient thermal resistance under natural convection is obtained in a simulation on a JEE-standard, high-k-board, as specified in JES51-7, in an environment described in JES51-2a. 4/ The junction to case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specified JEEstandard test exists, but a close description can be found in the NSI SEMI standard G / The junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the P temperature, as described in JES / The junction to top characterization parameter, Ψ JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θ J, using a procedure described in JES51-2a (sections 6 and 7). 7/ The junction to board characterization parameter, Ψ J, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θ J, using a procedure described in JES51-2a (sections 6 and 7). 8/ The junction to case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specified JEE- standard test exists, but a close description can be found in the NSI SEMI standard G30-88 N N MRITIME REV PGE 3

4 1.5 Recommended operating conditions. Supply voltage (V ) V to 5.5 V Input voltage at any bus terminal (separately or common mode) () to 25 V 9/ High level input voltage (driver, driver enable, and receiver enable inputs) (H)... 2 V to V ow level input voltage (driver, driver enable, and receiver enable inputs) ()... to 0.8 V ifferential input voltage () V to 25 V Output current, (I O): river m to 60 m Receiver m to 8 m Minimum differential load resistance (R ) Ω Typical differential load capacitance () pf Maximum signaling rate (1/t UI)... 1 Mbps Operating free air temperature (T ) (see manufacturer application section for thermal information) to 105 Junction temperature (T J) to PPIE OUMENTS JEE SOI STTE TEHNOOGY SSOITION (JEE) JEP95 Registered and Standard Outlines for Semiconductor evices JES Electrostatic ischarge (ES) Sensitivity Testing Human ody Model (HM) JES Electrostatic ischarge (ES) Sensitivity Testing Machine Model (MM) JES Field Induced harged evice Model Test Method For Electrostatic ischarge Withstand Thresholds of Microelectronic components. JES51 Methodology for the Thermal Measurement of omponent Packages (Single Semiconductor evice). JES51-2a Integrated ircuits Thermal Test Method Environment onditions Natural onvection (Still ir) JES51-7 High Effective Thermal onductivity Test oard for eaded Surface Mount Packages JES51-8 Integrated ircuits Thermal Test Method Environment onditions Junction-to-board (opies of these documents are available online at or from JEE Solid State Technology ssociation, 3103 North 10th Street, Suite 240 S, rlington, V ). INTERNTION EETROTEHNI OMMISSION (IE) IE Electrostatic discharge (ES) sensitivity testing - Human body model (HM) (opies of these documents are available online at or IE Regional enter for merica (IE-ReN), 446 Main St., 16 th Floor, Worcester, M 01608). MERIN NTION STNRS INSTITUTE (NSI) STNR NSI SEMI STNR G30-88 Test Method for Junction-to-ase Thermal Resistance Measurements for eramic Packages (pplications for copies should be addressed to the merican National Standards Institute, Semiconductor Equipment and Materials International, 1819 Street, NW, 6 th floor, Washington, or online at 9/ y convention, the least positive (most negative) limit is designated as minimum in this data sheet. N N MRITIME REV PGE 4

5 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer s part number as shown in 6.3 herein and as follows:. Manufacturer s name, GE code, or logo. Pin 1 identifier. ESS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer s part number and with items and (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 esign, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 iagrams ase outline. The case outline shall be as shown in and figure Terminal connections. The terminal connections shall be as shown in figure ogic iagram (Positive logic). The logic diagram (Positive logic) shall be as shown in figure river function table. The river function table shall be as shown in figure Receiver function table. The Receiver function table shall be as shown in figure Measurement of river differential output voltage with common mode load. The measurement of river differential output voltage with common mode load shall be as shown in figure Measurement of river differential and common mode output with RS-485 load. The measurement of river differential and common mode output with RS-485 load shall be as shown in figure Measurement of river differential output rise and fall times and propagation delays. The measurement of river differential output rise and fall times and propagation delays shall be as shown in figure Measurement of river enable and disable times with active high output and pulldown load. The measurement of river enable and disable times with active high output and pulldown load shall be as shown in figure Measurement of river enable and disable times with active low output and pulldown load. The measurement of river enable and disable times with active low output and pulldown load shall be as shown in figure Measurement of receiver output rise and fall times and propagation delays. The measurement of receiver output rise and fall times and propagation delays shall be as shown in figure Measurement of receiver enable/disable times with drives enabled. The measurement of receiver enable/disable times with drives enabled shall be as shown in figure Measurement of receiver enable times with driver disabled. The measurement of receiver enable times with driver disabled shall be as shown in figure 13. N N MRITIME REV PGE 5

6 TE I. Electrical performance characteristics. 1/ Test Symbol Test conditions 2/ river differential output voltage magnitude hange in magnitude of driver differential output voltage Steady state common mode output voltage hange in differential driver output common mode voltage Peak to peak driver common mode output voltage RS-485 with common-mode load, V > 4.75 V, see FIGURE 6 imits Unit Min Typ Max 1.37 V R = 54 Ω, 4.75 V V 5.25 V R = 100 Ω, 4.75 V V 5.25 V R = 54 Ω V (SS) 1 V /2 (SS) mv (PP) enter of two 27 Ω load resistors, See FIGURE mv ifferential output capacitance O 23 pf Positive going receiver differential input voltage threshold T mv Negative going receiver differential T- V M = -2 to 25 V mv input voltage threshold Receiver differential input voltage V HYS mv threshold hysteresis Receiver high level output voltage H I OH = -8 m 2.4 V 0. I OH = -400 µ 4 Receiver low level output voltage I O = 8 m V river input, driver enable, and receiver enable input current I I µ Receiver output high impedance current I OZ = or V, RE at V -1 1 river short circuit output current I OS m us input current (disable driver) Supply current (quiescent) Supply current (dynamic) See footnote at end of table. I I I V = 4.5 V to 5.5 V or V =, E at river and receiver enabled river enabled, receiver disabled river disabled, receiver enabled river and receiver disabled See manufacturer data = 12 V µ = -7 V E = V, m RE = GN, no load E = V, RE = V, no load E = GN, RE = GN, no load E = GN, = open RE = V, no load T J = -40 to 105 T J = µ N N MRITIME REV PGE 6

7 TE I. Electrical performance characteristics - ontinued. 1/ Test Symbol Test conditions 2/ imits Min Typ Max SWITHING HRTERISTIS river river differential output rise/fall time t r, t f ns river propagation delay t PH, t PH R = 54 Ω, = 50 pf, 200 river differential output pulse skew, t PH t PH t SK(P) See FIGURE 8 29 river disable time t PHZ, t PZ See 3 µs Receiver enabled FIGURE ns river enable time t and 10 PZH, t PZ Receiver disabled 10 µs Receiver enabled V M > V 500 ns Receiver Receiver output rise/fall time t r, t f 4 15 ns Receiver propagation delay time t PH, t PH = 15 pf, See FIGURE Receiver output pulse skew, t PH t PH t SK(P) 6 20 Receiver disable time t PZ, t PHZ river enabled, See FIGURE Receiver enable time t PZ(1), t PZH(1) river enabled, See FIGURE t PZ(2), t PZH(2) river disabled, See FIGURE µs Unit 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Over recommended operating conditions (unless otherwise noted). N N MRITIME REV PGE 7

8 ase X e b.010(0.25) M 14 8 E E1 1 7 PIN 1 INEX RE SEE ETI 1 c GGE PNE (0.10) SETING PNE.010(0.25) ETI imensions Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max E E b e.050 S 1.27 S c NOTES: 1. ll linear dimensions are in inches (millimeters). 2. This drawing is subject to change without notice. 3. ody length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed.006 (0.15) each side. 4. ody width does not include interlead flash. Interlead flash shall not exceed.017 (0.43) each side. 5. Falls within JEE MS-012 variation. FIGURE 1. ase outline. N N MRITIME REV PGE 8

9 Terminal number Terminal symbol ase outline X Terminal number Terminal symbol 1 N 14 V 2 R 1 3 RE 12 4 E Z 6 GN 9 Y 7 GN 8 N N = No internal connection Pins 6 and 7 are connected together internally. Pins 13 and 14 are connected together internally. FIGURE 2. Terminal connections. E Y Z RE R FIGURE 3. ogic iagram (Positive logic). Input Enable Outputs E H H H ctively drive bus high H H ctively drive bus low X Z Z river disabled X Open Z Z river disabled by default Open H H ctively drive bus high by default FIGURE 4. river function table. N N MRITIME REV PGE 9

10 ifferential Input Enable Output = V - V RE R T+ < H Receive valid bus high T- < < T+? Intermediate bus state < T- Receive valid bus low X H Z Receiver disabled X Open Z Receiver disabled by default Open circuit bus H Fail safe high output Short circuit bus H Fail safe high output Idle(Terminated) bus H Fail safe high output FIGURE 5. Receiver function table. V 375 or E Y 60 Z < V(test)< 25 V FIGURE 6. Measurement of river differential output voltage with common mode load. V INPUT E 27 V V 27 =50 pf ±20% (PP) (SS) INUES FIXTURE N INSTRUMENTTION PITNE FIGURE 7. Measurement of river differential and common mode output with RS-485 load. N N MRITIME REV PGE 10

11 INPUT GENERTOR 50 V E R=54 =50 pf t t PH PH ±20% 2 V 90% 10% -2 V t r t f INUES FIXTURE N INSTRUMENTTION PITNE FIGURE 8. Measurement of river differential output rise and fall times and propagation delays. INPUT GENERTOR S1 E =50 pf =110 R t t PZH PHZ 0.5 V ±20% V H I 50 90% INUES FIXTURE N INSTRUMENTTION PITNE NOTE: 1. at to test non-inverting output, at to test inverting output FIGURE 9. Measurement of river enable and disable times with active high output and pulldown load. INPUT GENERTOR 50 E S1 =50 pf ±20% INUES FIXTURE N INSTRUMENTTION PITNE R =110 t PZ t PZ 10% NOTE: 1. at to test non-inverting output, at to test inverting output FIGURE 10. Measurement of river enable and disable times with active low output and pulldown load. N N MRITIME REV PGE 11

12 INPUT GENERTOR V 1.5 V R I 50 RE =15 pf ±20% INUES FIXTURE N INSTRUMENTTION PITNE t PH t r t PH t f H 90% 10% FIGURE 11. Measurement of receiver output rise and fall times and propagation delays. or INPUT GENERTOR E 50 RE R 1 k =15 pf ±20% V INUES FIXTURE N INSTRUMENTTION PITNE S1 t PZH(1) t PHZ t PZ(1) H 90% at S1 to GN t PZ V at S1 to V 10% FIGURE 12. Measurement of receiver enable/disable times with drives enabled. N N MRITIME REV PGE 12

13 V INPUT GENERTOR or 1.5 V 1.5 V or 50 RE R 1 k =15 pf ±20% S1 INUES FIXTURE N INSTRUMENTTION PITNE t PZH(2) t PZ(2) H GN V at 1.5 V at 0V S1 to GN at at 1.5 V S1 to V FIGURE 13. Measurement of receiver enable times with driver disabled. N N MRITIME REV PGE 13

14 4. VERIFITION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPRTION FOR EIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESS. evices are electrostatic discharge sensitive and are classified as ESS class 1 minimum. 6.2 onfiguration control. The data contained herein is based on the salient characteristics of the device manufacturer s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. and and Maritime maintains an online database of all current sources of supply at Vendor item drawing administrative control number 1/ evice manufacturer GE code Transport media Vendor part number -01XE Tape and real Tube SN65HV1792TREP SN65HV1792TEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. GE code Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest ane P.O. ox allas, TX Point of contact: U.S. Highway 75 South P.O. ox 84, M/S 853 Sherman, TX N N MRITIME REV PGE 14