TITLE MICROCIRCUIT, DIGITAL, ADVANCED CMOS, 16- BIT BUS TRANSCEIVER WITH THREE-STATE OUTPUTS, TTL COMPATIBLE, MONOLITHIC SILICON REVISIONS

Transcription

1 REVISIONS LTR DESCRIPTION DTE PPROVED B Update boilerplate paragraphs to current requirements. - PHN Update boilerplate to current MIL-PRF requirements. - PHN Charles F. Saffle Thomas M. Hess CURRENT DESIGN CTIVITY CGE CODE HS CHNGED NMES TO: DL LND ND MRITIME Prepared in accordance with SME Y14.24 Vendor item drawing REV PGE REV PGE REV STTUS OF PGES REV B B B B B B B B B B PGE PMIC N/ Original date of drawing YY MM DD PREPRED BY Phu H. Nguyen CHECKED BY Phu H. Nguyen PPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITL, DVNCED CMOS, 16- BIT BUS TRNSCEIVER WITH THREE-STTE OUTPUTS, TTL COMPTIBLE, MONOLITHIC SILICON CODE IDENT. NO. REV B PGE 1 OF 10 MSC N/ V075-15

2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 16-bit bus transceiver with three-state outputs, with an operating temperature range of -40 C to +125 C. 1.2 Vendor Item Drawing dministrative Control Number. The manufacturer s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: Device type(s) X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) Device Type Generic Circuit function 01 SN74CT16245Q-EP 16-Bit Bus Transceiver with three-state outputs Case outline(s). The case outline(s) are as specified herein. Outline Letter Number of pins JEDEC PUB 95 Package style X 48 JEDEC MO-118 Plastic small outline Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator B C D E Z Material: Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other 1.3 bsolute maximum ratings 1/ Supply voltage range (V CC) V to 7 V Input voltage range (V I) V to V CC +0.5 V 2/ Output voltage range (V O) V to V CC +0.5 V 2/ Input clamp current (I IK) (V I < 0 V or V I > V CC)... ± 20 m Output clamp current (I OK) (V I < 0 V or V I > V CC)... ± 24 m Continuous output current (I O) (V O = 0 V to V CC)... ± 24 m Continuous current through V CC or GND... ± 260 m Maximum power dissipation at T = 55 o C (in still air) W 3/ Storage temperature range, T stg o C to 150 o C 1/ Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if the input and output ratings are observed. 3/ The maximum package power dissipation is calculated using a junction temperature of 150 o C and a broad trace length of 750 mils. REV B PGE 2

3 1.4 Recommended operating conditions 4/ 5/ Supply voltage range (V CC) V to +5.5 V 6/ Input voltage range (V IN) V to V CC Output voltage range (V OUT) V to V CC Minimum high-level input voltage (V IH) V Maximum low level input voltage (V IL) V Maximum high level output current (I OH) m Maximum low level output current (I OL) m Input transition rise or fall rate ( t/ v)... 0 to 10 ns/v mbient operating temperature (T ) o C to 125 o C 2. PPLICBLE DOCUMENTS JEDEC SOLID STTE TECHNOLOGY SSOCITION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at or from JEDEC Solid State Technology ssociation, 3103 North 10th Street, Suite 240 S, rlington, V ). 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer s part number as shown in 6.3 herein and as follows:. Manufacturer s name, CGE code or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer s part number and with items and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4 and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams Case outline(s). The case outline (s) shall be as shown in and figure Block diagram. The block diagram shall be as shown in figure Terminal connections. The terminal connections shall be as shown in figure Timing waveforms. The timing waveforms shall be as shown in figure 4. 4/ Unused inputs should be tied to V CC through a pullup resistor of approximately 5 kω or greater to keep them from floating. Refer to the device manufacturer s application report. 5/ Use of this product beyond the manufacturers design rules or stated parameters is done at the user s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 6/ ll V CC and GND pins must be connected to the proper-voltage power supply. REV B PGE 3

4 TBLE I. Electrical performance characteristics. 1/ Test Symbol Test conditions unless otherwise specified V CC T at Device type High level output voltage V OH I OH = -50 µ 4.5 V 25 C V -40 C to +125 C V 25 C C to +125 C 5.40 I OH = -16 m 4.5 V 25 C C to +125 C V 25 C C to +125 C 4.94 I OH = -24 m 2/ 5.5 V -40 C to +125 C 3.85 Low level output voltage I OL = 50 µ 4.5 V 25 C 0.10 V -40 C to +125 C V 25 C C to +125 C 0.10 I OL = 16 m 4.5 V 25 C C to +125 C V 25 C C to +125 C 0.50 I OL = 24 m 2/ 5.5 V -40 C to +125 C 0.50 Input current I I V I = V CC or GND 5.5 V 25 C ± 0.10 µ (Control inputs) -40 C to +125 C ± 1 Three-state output leakage I OZ V O = V CC or GND 5.5 V 25 C ± 0.50 µ current ( 0r B ports) 3/ -40 C to +125 C ± 10 Quiescent supply current I CC V I = V CC or GND, 5.5 V 25 C 8 µ I O = 0-40 C to +125 C 160 Quiescent supply current I CC One input at 3.4 V, 5.5 V 25 C 0.9 m delta 4/ Other inputs at GND or V CC -40 C to +125 C 1 Input capacitance C I V I = V CC or GND 5.0 V 25 C 4.5 TYP pf (Control inputs) Output capacitance ( or B ports) C IO V O = V CC or GND 5.0 V 25 C 16 TYP pf Power capacitance per C PD C L = 50 pf Output 5.0 V 25 C 52 TYP pf transceiver f = 1 MHz enabled Output disabled 10 TYP See footnotes at end of table. Min Limits Max Unit REV B PGE 4

5 TBLE I. Electrical performance characteristics. 1/ Test Propagation delay time Symbol t PLH Test conditions unless otherwise specified From (Input) or B To (Output) B or V CC T at Device type Min Limits Max Unit 5/ 25 C ns -40 C to +125 C t PHL 5/ 25 C t PZH -40 C to +125 C / 25 C G B or -40 C to +125 C t PZL 5/ 25 C t PHZ -40 C to +125 C / 25 C G B or -40 C to +125 C t PLZ 5/ 25 C C to +125 C Notes: 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. 3/ For I/O ports, the parameter I OZ includes the input leakage current I I. 4/ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V CC. 5/ V CC = 4.5 V to 5.5 V REV B PGE 5

6 Case X Symbol Inches Millimeters Min Max Min Max b D E E e Typ Typ L L L FIGURE 1. Case outline. REV B PGE 6

7 Function table Control Inputs Operation G DIR L L B data to bus L H data to B bus H X Isolation L = Low H = High X = Don t care FIGURE 2. Block diagram. REV B PGE 7

8 Terminal number Terminal Symbol Terminal number Terminal Symbol 1 1DIR 25 2 G 2 1B B GND 28 GND 5 1B B V CC 31 V CC 8 1B B GND 34 GND 11 1B B B B GND 39 GND 16 2B B V CC 42 V CC 19 2B B GND 45 GND 22 2B B DIR 48 1 G FIGURE 3. Terminal connections. REV B PGE 8

9 Test t PLH / t PHL t PLZ / t PZL t PHZ / t PZH S1 Open 2 x V CC GND Notes: 1/ CL includes probe and jig capacitance. 2/ Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control 3/ ll impulses are supplied by generators having the following characteristics: PRR 1 MHz, Z O = 50 Ω, t r = 3 ns, t f = 3 ns. 4/ The outputs are measured one at a time with one input transition per measurement. FIGURE 4. Timing waveforms. REV B PGE 9

10 4. VERIFICTION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices as applicable. 5. PREPRTION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DL Land and Maritime maintains an online database of all current sources of supply at Vendor item drawing administrative control number 1/ Device manufacturer CGE code Vendor part number Top-Side Marking -01XE SN74CT16245QDLREP CT16245QEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CGE code Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box Dallas, TX Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX REV B PGE 10