DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO TITLE MICROCIRCUIT, DIGITAL-LINEAR, 1 OHM, SPDT ANALOG SWITCH, MONOLITHIC SILICON REVISIONS

Transcription

1 REVISIONS LTR DESCRIPTION DTE PPROVED Update document paragraphs to current requirements. - ro C. SFFLE CURRENT DESIGN CTIVITY CGE CODE HS CHNGED NMES TO: DL LND ND MRITIME Prepared in accordance with SME Y14.24 Vendor item drawing REV PGE REV PGE REV STTUS OF PGES REV PGE PMIC N/ PREPRED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS Original date of drawing YY-MM-DD CHECKED BY TOM HESS PPROVED BY RYMOND MONNIN TITLE MICROCIRCUIT, DIGITL-LINER, 1 OHM, SPDT NLOG SWITCH, MONOLITHIC SILICON CODE IDENT. NO. REV PGE 1 OF 19 MSC N/ 5962-V077-14

2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance one ohm SPDT analog switch microcircuit, with an operating temperature range of -55 C to +125 C. 1.2 Vendor Item Drawing dministrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: Device type(s) X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) Device type Generic Circuit function 01 TS53159-EP 1 ohm SPDT analog switch Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 6 MO-178-B Plastic small outline Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator B C D E Z Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other REV PGE 2

3 1.3 bsolute maximum ratings. 1/ Supply voltage range ( V+ ) V to 6.5 V 2/ nalog voltage range ( V NO, V COM ) V to V V 2/ 3/ 4/ nalog port diode current ( I I/OK ) : V NO, V COM 0 or V NO, V COM V m On state switch current ( I NO, I COM ): V NO, V COM = 0 to V m On state peak switch current m 5/ Digital input voltage range ( V IN ) V to 6.5 V 2/ 3/ Digital input clamp current (I IK ) ( V IN 0 ) m Continuous current through V+ or GND m Storage temperature range ( Tstg ) C to +150 C Package thermal impedance ( J ) C/W 6/ 1.4 Recommended operating conditions. 7/ Supply voltage range ( V+ ) V to 5.5 V Operating free-air temperature range (T ) C to +125 C 1/ Stresses beyond those listed under absolute maximum rating may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ ll voltages are with respect to ground, unless otherwise specified. 3/ The input and output voltage ratings may be exceeded if the input and output clamp current ratings are observed. 4/ This value is limited to 5.5 V maximum. 5/ Pulse at 1 ms duration 10 % duty cycle. 6/ The package thermal impedance is calculated in accordance with JESD / Use of this product beyond the manufacturers design rules or stated parameters is done at the user s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. REV PGE 3

4 2. PPLICBLE DOCUMENTS JEDEC Solid State Technology ssociation EI/JEDEC 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (pplications for copies should be addressed to the Electronic Industries lliance, 2500 Wilson Boulevard, rlington, V or online at 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer s part number as shown in 6.3 herein and as follows:. Manufacturer s name, CGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer s part number and with items and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams Case outline. The case outline shall be as shown in and figure Terminal connections. The terminal connections shall be as shown in figure Truth table. The truth table shall be as shown in figure Parameter description table. The parameter description table shall be as shown in figure Timing waveforms and test circuits. The timing waveforms and test circuits shall be as shown in figure 5. REV PGE 4

5 TBLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ Temperature, T Device type Min Limits Max Unit nalog switch section nalog signal range V COM, V NC, V NO Peak ON resistance r peak 0 V NO or V NC V+, switch on, I COM = -30 m, see figure 5, V+ = 4.5 V ON state resistance r on V NO or V NC = 2.5 V, switch on, I COM = -30 m, see figure 5, V+ = 4.5 V -55 C to +125 C 01 0 V+ V +25 C C to +125 C C C to +125 C 1.3 ON state resistance match between channels r on V NO or V NC = 2.5 V, switch on, I COM = -30 m, see figure 5, V+ = 4.5 V +25 C typical On state resistance flatness r on(flat) 0 V NO or V INC V+, switch on, I COM = -30 m, see figure 5, V+ = 4.5 V +25 C typical V NO or V NC = 1 V, 1.5 V, 2.5 V, 0.15 typical I COM = -30 m, switch on, see figure 5, V+ = 4.5 V NC, NO OFF leakage current NC, NO ON leakage current I NC(OFF), V NC or V NO = 4.5 V, V COM = 0, +25 C n I NO(OFF) V+ = 5.5 V, switch off, see figure 5-55 C to +125 C I NC(ON), V NC or V NO = 4.5 V, V COM = open, +25 C n V+ = 5.5 V, switch on, I NO(ON) see figure 5-55 C to +125 C COM ON leakage current I COM(ON) V NC or V NO = 4.5 V, or open V COM = 4.5 V, V+ = 5.5 V, switch on, see figure C n -55 C to +125 C See footnotes at end of table. REV PGE 5

6 TBLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ Temperature, T Device type Min Limits Max Unit Digital control input ( IN ) section Input logic high voltage Input logic low voltage V IH -55 C to +125 C V V IL -55 C to +125 C V Input leakage current I IH, I IL V I = 5.5 V or 0, V+ = 5.5 V -55 C to +125 C Dynamic section Turn on time t ON V COM = V+, C L = 35 pf, R L = 50, see figure 5, V+ = 4.5 V to 5.5 V Turn off time t OFF V COM = V+, C L = 35 pf, R L = 50, see figure 5, V+ = 4.5 V to 5.5 V +25 C ns -55 C to +125 C C ns -55 C to +125 C 35 Break before make time t BBM V NC = V NO = V+ / 2, C L = 35 pf, R L = 50, see figure 5, V+ = 4.5 V to 5.5 V +25 C ns -55 C to +125 C 1 Charge injection Q C C L = 1 nf, V GEN = 0 V, see figure 5, V+ = 5 V +25 C typical pc NC, NO, OFF capacitance C NC(OFF), C NO(OFF) V NC or V NO = V+ or GND, switch OFF, see figure 5, V+ = 5 V +25 C typical pf NC, NO, ON capacitance C NC(ON), C NO(ON) V NC or V NO = V+ or GND, switch ON, see figure 5, V+ = 5 V +25 C typical pf COM ON capacitance C COM(ON) V COM = V+ or GND, V+ 5 V, switch ON, see figure C typical pf Digital input capacitance C IN V IN = V+ or GND, V+ = 5 V, see figure C typical pf See footnotes at end of table. REV PGE 6

7 TBLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ Temperature, T Device type Min Limits Max Unit Dynamic section - continued Bandwidth BW R L = 50, switch ON, V+ = 5 V, see figure C typical MHz OFF isolation O ISO R L = 50, switch OFF, V+ = 5 V, f = 1 MHz, see figure C typical db Crosstalk X TLK R L = 50, switch ON, V+ = 5 V, f = 1 MHz, see figure C typical db Talk harmonic distortion THD R L = 600, C L = 50 pf, V+ = 5 V, f = 600 Hz to 20 khz, see figure C typical % Supply section Positive supply current I+ V IN = V+ or GND, V+ = 5.5 V, switch ON or OFF -55 C to +125 C / Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Unless otherwise specified, V+ = 4.5 V to 5.5 V. REV PGE 7

8 Case X FIGURE 1. Case outline. REV PGE 8

9 Case X Dimensions Symbol Inches Millimeters Min Max Min Max b c D E E e BSC 0.95 BSC L L BSC 0.25 BSC n 6 6 NOTES: 1. Controlling dimensions are millimeter, inch dimensions are given for reference only. 2. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 mm (.005 inch) per side. 3. Leads 1, 2, 3 may be wider than leads 4, 5, 6 for package orientation. 4. Falls within JEDEC MO-178 variation B, except minimum lead width. FIGURE 1. Case outline Continued. REV PGE 9

10 Device type 01 Case outline X Terminal number Terminal symbol Description 1 NO Normally open 2 GND Digital ground 3 NC Normally closed 4 COM Common 5 V+ Power supply 6 IN Digital control pin to connect COM to NO or NC FIGURE 2. Terminal connections. IN NC to COM, COM to NC NO to COM, COM to NO L ON OFF H OFF ON FIGURE 3. Truth table. REV PGE 10

11 Symbol Description V COM V NC V NO r on r peak r on r on(flat) I NC(OFF) I NO(OFF) I NC(ON) I NO(ON) I COM(ON) V IH V IL V IN I IH, I IL t ON t OFF Voltage at COM. Voltage at NC. Voltage at NO. Resistance between COM and NO ports when the channel is ON. Peak on state resistance over a specified voltage range. Difference of r on between channels in a specific device Difference between the maximum and minimum value of r on in a channel over the specified range of conditions. Leakage current measured at the NC port, with the corresponding channel (NC to COM) in the OFF state under worst case input and output conditions. Leakage current measured at the NO port, with the corresponding channel (NO to COM) in the OFF state. Leakage current measured at the NC port, with corresponding channel (NC to COM) in the ON state and the output (COM) open. Leakage current measured at the NO port, with corresponding channel (NO to COM) in the ON state and the output (COM) open. Leakage current measured at the COM port, with corresponding channel (COM to NO) in the ON state and the output (NO) open. Minimum input voltage for logic high for the control input (IN). Maximum input voltage for logic low for the control input (IN). Voltage at IN. Leakage current measured at IN. Turn on time for the switch. This parameter is measured under the specified range of conditions and by the propagation delay between the digital control (IN) signal and analog output (COM or NO) signal when the switch is turning ON. Turn off time for the switch. This parameter is measured under the specified range of conditions and by the propagation delay between the digital control (IN) signal and analog output (COM or NO) signal when the switch is turning OFF. FIGURE 4. Parameter description table. REV PGE 11

12 Symbol t BBM Q C C NC(OFF) C NO(OFF) C NC(ON) C NO(ON) C COM(ON) C IN O ISO X TLK BW Description Break before make time. This parameter is measured under the specified range of conditions and by the propagation delay between the output of two adjacent analog channels (NC and NO), when the control signal changes state. Charge injection is a measurement of unwanted signal coupling from the control (IN) input to the analog (NO or COM) output. This is measured in coulomb (C) and measured by the total charge induced due to switching of the control input. Charge injection, Q C = C L x V COM, C L is the load capacitance and V COM is the change in analog output voltage. Capacitance at the NC port when the corresponding channel (NC to COM) is OFF. Capacitance at the NO port when the corresponding channel (NC to COM) is OFF. Capacitance at the NC port when the corresponding channel (NC to COM) is ON. Capacitance at the NO port when the corresponding channel (NC to COM) is ON. Capacitance at the COM port when the corresponding channel (COM to NO) is ON. Capacitance of IN. OFF isolation of the switch is a measurement of OFF state switch impedance. This is measured in db in a specific frequency, with the corresponding channel (NO to COM) in the OFF state. Crosstalk is a measurement of unwanted signal coupling from an ON channel to an adjacent ON channel (NC1 to NC2). This is measured in a specific frequency and in db. Bandwidth of the switch. This is the frequency in which the gain of an ON channel is -3 db below the DC gain. I+ Static power supply current with the control (IN) pin at V+ or GND. I+ This is the increase in I+ for each control (IN) input that is at the specified voltage, rather than at V+ or GND. FIGURE 4. Parameter description table Continued. REV PGE 12

13 ON state resistance ( r on ) OFF state leakage current ( I NC(OFF), I NO(OFF) ) FIGURE 5. Timing waveforms and test circuit. REV PGE 13

14 NOTE: See electrical characteristics for test conditions. ON state leakage current ( I COM(ON), I NC(ON), I NO(ON) ) Capacitance ( C I, C COM(ON), C NC(OFF), C NO(OFF), C NC(ON), C NO(ON) ) FIGURE 5. Timing waveforms and test circuit Continued. REV PGE 14

15 NOTES: 1. ll input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z O = 50, t r 5 ns, t f 5 ns. 2. C L includes probe and jig capacitance. Turn on ( t ON ) and turn off time ( t OFF ) NOTES: 1. ll input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z O = 50, t r 5 ns, t f 5 ns. 2. C L includes probe and jig capacitance. Break before make time ( t BBM ) FIGURE 5. Timing waveforms and test circuit Continued. REV PGE 15

16 Bandwidth ( BW ) OFF isolation ( O ISO ) FIGURE 5. Timing waveforms and test circuit Continued. REV PGE 16

17 Crosstalk ( X TLK ) NOTES: 1. ll input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z O = 50, t r 5 ns, t f 5 ns. 2. C L includes probe and jig capacitance. Charge injection ( Q C ) FIGURE 5. Timing waveforms and test circuit Continued. REV PGE 17

18 NOTE: 1. C L includes probe and jig capacitance. Total harmonic distortion ( THD ) FIGURE 5. Timing waveforms and test circuit Continued. REV PGE 18

19 4. VERIFICTION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPRTION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DL Land and Maritime maintains an online database of all current sources of supply at Vendor item drawing administrative control number 1/ Device manufacturer CGE code Package 2/ Top side marking Vendor part number -01XE SOT (SOT-23) - DBV Tape and reel J8R TS53159MDBVREP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ Package drawings, standard packaging quantities, thermal data, symbolization, and PCB design guidelines are available from manufacturer. CGE code Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box Dallas, TX Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX REV PGE 19