DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO TITLE MICROCIRCUIT, LINEAR, SWITCH MODE LEAD ACID BATTERY CHARGER, MONOLITHIC SILICON

Transcription

1 REVISIONS LTR DESCRIPTION DTE PPROVED dd the minimum limit to the High output voltage (V OH ) test as specified under Table I. Updating document paragraph to current requirements. - ro C. SFFLE CURRENT DESIGN CTIVITY CGE CODE HS CHNGED NMES TO: DL LND ND MRITIME Prepared in accordance with SME Y14.24 Vendor item drawing REV PGE REV PGE REV STTUS OF PGES REV PGE PMIC N/ PREPRED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS Original date of drawing YY-MM-DD CHECKED BY RJESH PITHDI PPROVED BY CHRLES F. SFFLE TITLE MICROCIRCUIT, LINER, SWITCH MODE LED CID BTTERY CHRGER, MONOLITHIC SILICON CODE IDENT. NO. REV PGE 1 OF 15 MSC N/ 5962-V069-16

2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance switch mode lead acid battery charger microcircuit, with an operating temperature range of -55 C to +125 C. 1.2 Vendor Item Drawing dministrative Control Number. The manufacturer s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: Device type(s) X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) Device type Generic Circuit function 01 UC2909-EP Switch mode lead acid battery charger Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 20 MS-013-C Plastic surface mount Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator B C D E Z Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other REV PGE 2

3 1.3 bsolute maximum ratings. 1/ 2/ Supply voltage range (V CC ): OUT, STT0, STT1 pins V Output current sink Voltage at CS+, CS- pins V to V CC 3/ Remaining pin voltages V to 9 V Power dissipation (P D )... 4 W Storage temperature range (T STG ) C to 150 C Junction temperature range (T J ) C to 150 C Lead temperature (soldering, 10 seconds) C Thermal resistance, junction to ambient ( JC ) C/W Thermal resistance, junction to ambient ( J ) C/W 1.4 Recommended operating conditions. 4/ Supply voltage range (V CC ) V Operating free-air temperature range (T ) C to +125 C 1/ Stresses beyond those listed under absolute maximum rating may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ ll currents are positive into, negative out of the specified terminal. 3/ Voltages more negative than -0.4 V can be tolerated if current is limited to 50 m. 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at the user s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. REV PGE 3

4 2. PPLICBLE DOCUMENTS JEDEC Solid State Technology ssociation JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at or from JEDEC Solid State Technology ssociation, 3103 North 10th Street, Suite 240 S, rlington, V ). 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer s part number as shown in 6.3 herein and as follows:. Manufacturer s name, CGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer s part number and with items and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams Case outline. The case outline shall be as shown in and figure Terminal connections. The terminal connections shall be as shown in figure Charge state decode table. The charge state decode table shall be as shown in figure 3. REV PGE 4

5 TBLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ Temperature, T Device type Min Limits Max Unit Current sense amplifier (CS) V ID = CS+ - CS- DC gain CS- = 0 V, CS+ = -50 mv; CS+ = -200 mw CS+ = 0 V, CS- = 50 mv; CS- = 250 mw -55 C to +125 C V/V Offset voltage (VCSO - VCO) V OFFSET CS+ = CS- = 2.3 V, CO = C- -55 C to +125 C mv Common mode rejection ratio CMRR V CM = -0.2 V to V CC - 2, 8.8 V V CC 14 V V CM = -0.2 V to V CC, 14 V V CC 35 V -55 C to +125 C db 50 Low output voltage V OL V ID = -550 mv, -0.2 V V CM V CC - 2, I O = 500 High output voltage V OH V ID = 700 mv, -0.2 V V CM V CC - 2, I O = C to +125 C V -55 C to +125 C V Output source current I SOURCE V ID = 700 mv, CSO = 4 V -55 C to +125 C m Output sink current I SINK V ID = 550 mv, CSO = 1 V -55 C to +125 C 01 3 m 3 db bandwidth 3/ BW V ID = 90 mv, V CM = 0 V +25 C typical khz Current error amplifier (CE) Input bias current I B 8.8 V V CC 35 V, -55 C to +125 C V CHGENB = V LOGIC Input offset voltage 4/ V IO 8.8 V V CC 35 V, CO = C- +25 C typical mv Output voltage gain VO 1 V V O 4 V -55 C to +125 C db Gain bandwidth GBW f = 100 khz T J = +25 C 01 1 MHz See footnotes at end of table. REV PGE 5

6 TBLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ Temperature, T Device type Min Limits Max Unit Current error amplifier (CE) - continued. Low output voltage V OL I O = C to +125 C V High output voltage V OH I O = -5 m -55 C to +125 C V Output source current I SOURCE CO = 4 V -55 C to +125 C m Output sink current I SINK CO = 1 V -55 C to +125 C 01 2 m Trickle control current I C-, V CHGENB = GND -55 C to +125 C I TRCK_ CONTROL Voltage amplifier (CE) Input bias current I B Total bias current, regulating level -55 C to +125 C 01 1 Input offset voltage 4/ V IO 8.8 V V CC 35 V, +25 C typical mv V CM = 2.3 V, V O = V - Output voltage gain VO 1 V CO 4 V -55 C to +125 C db Gain bandwidth GBW f = 100 khz T J = +25 C MHz Low output voltage V OL I O = C to +125 C V High output voltage V OH I O = C to +125 C V Output source current I SOURCE CO = 4 V -55 C to +125 C 01-2 m Output sink current I SINK CO = 1 V -55 C to +125 C 01 2 m VO leakage: high impedance state V CHGENB = GND, STT0 = 0 and STT1 = 0, V O = 2.3 V -55 C to +125 C See footnotes at end of table. REV PGE 6

7 TBLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ Temperature, T Device type Limits Unit Min Max Pulse width modulation Maximum duty cycle CO = 0.6 V -55 C to +125 C % Modulator gain CO = 2.5 V, 3.2 V -55 C to +125 C %/V OSC peak +25 C 01 3 typical V OSC valley +25 C 01 1 typical V Oscillator Frequency 8.8 V V CC 35 V -55 C to +125 C khz Thermistor derived Initial accuracy, VO (R THM = 10 k ) V ID = V RTHM - V R10 V ID = 0 V, R10 = R THM = 10 k 5/ -55 C to +125 C V Line regulation V CC = 8.8 V to 35 V -55 C to +125 C mv Voltage error amplifier VO R THM = 138 k, R10 = 10 k -55 C to +125 C V R THM = k, R10 = 10 k R THM = k, R10 = 10 k Charge enable comparator (CEC) Threshold voltage s a function of V C to +125 C V/V Input bias current I IB CHGENB = 2.3 V -55 C to +125 C Voltage sense comparator (VSC) Threshold voltage V TH STT0 = 0, STT1 = 0, function of V REF STT0 = 1, STT1 = 0, -55 C to +125 C V/V function of V REF See footnotes at end of table. REV PGE 7

8 TBLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ Temperature, T Device type Min Limits Max Unit Over charge taper current comparator (OCTIC) Threshold voltage V TH Function of 2.3 V REF, C- = CO -55 C to +125 C V/V Input bias current I IB OVCTP = 2.3 V -55 C to +125 C Logic 5 V (VLOGIC) Logic voltage V LOGIC V CC = 15 V -55 C to +125 C V Line regulation V LN 8.8 V V CC 35 V -55 C to +125 C mv Load regulation V LD 0 I O 10 m -55 C to +125 C mv Reference comparator turn-on threshold -55 C to +125 C V Short circuit current I OS V REF = 0 V -55 C to +125 C m Output stage I SINK continuous I SINK +25 C typical m Peak current I PEK +25 C typical m Output low voltage V OL I O = 50 m -55 C to +125 C V Leakage current I LEK V OUT = 35 V -55 C to +125 C STT0 and STT1 open collector outputs Maximum sink current I SINK V OUT = 8.8 V -55 C to +125 C 01 5 m Saturation voltage V ST I OUT = 5 m -55 C to +125 C V Leakage current I LEK V OUT = 35 V -55 C to +125 C STTLV open collector outputs Maximum sink current I SINK V OUT = 5 V -55 C to +125 C 01 2 m Saturation voltage V ST I OUT = 2 m -55 C to +125 C V Leakage current I LEK V OUT = 5 V -55 C to +125 C 01 3 See footnotes at end of table. REV PGE 8

9 TBLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ Temperature, T Device type Min Limits Max Unit Under voltage lockout (UVLO) Turn on threshold -55 C to +125 C V Hysteresis -55 C to +125 C mv Supply current (I CC ) Supply current, run I CC(run) See figure 4-55 C to +125 C m Supply current, off I CC(off) V CC = 6.5 V -55 C to +125 C 01 2 typical m 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Unless otherwise specified, V CC = 15, timing capacitor (C T ) = 430 pf, R SET = 11.5 k, R10 = 10 k, R THM = 10 k, output no load, R STT0 = R STT1 = 10 k, CHGENB = OVCTP = VLOGIC, and T = T J. 3/ Not tested in production. 4/ Input offset voltage (V IO ) is measured prior to packaging with internal probe pad. 5/ Thermistor initial accuracy is measured and trimmed with respect to V O ; V O = V -. REV PGE 9

10 Case X FIGURE 1. Case outline. REV PGE 10

11 Case X - continued. Symbol Inches Dimensions Millimeters Min Max Min Max b c D e.050 BSC 1.27 BSC E E L n NOTES: 1. Controlling dimensions are inch. Millimeter dimensions are given for reference only. 2. Body dimensions do not include mold flash or protrusion not to exceed.006 inch (0.15 mm). 3. Falls within JEDEC MS-013 variation C. FIGURE 1. Case outline Continued. REV PGE 11

12 Device type 01 Case outline Terminal number X Terminal symbol Description 1 RTHM 10 k thermistor is connected to ground and is thermally connected to the battery. The resistance will vary exponentially over temperature and its change is used to vary the internal 2.3 V reference by -3.9 mv/ C. 2 VLOGIC The precision reference voltage. It should be bypassed with a 0.1 F capacitor. 3 GND The reference point for the internal reference, all thresholds, and the return for the remainder of the device. The output sink transistor is wired directly to this pin. 4 V CC The input voltage to the chip. The chip is operational between 7.5 V and 40 V and should be bypassed with a 1 F capacitor. normal I CC versus temperature is shown in figure 4. 5 OUT The output of the pulse width modulator (PWM) driver which consists of an open collector output transistor with 100 m sink capability. 6 STT1 This open collector pin is the second decode bit used to decode the charge states. 7 STT0 This open collector pin is the first decode bit used to decode the charge states. 8 STTL This pin is high when the charger is in the float state. 9 OVCTP The overcharge current taper pin detects when the output current has tapered to the float threshold in the overcharge state. 10 CHGENB The input to a comparator that detects when battery voltage is the low and places the charger in a trickle charge state. The charge enable comparator makes the output of the voltage error amplifier a high impedance while forcing a fixed 10 m into the inverting input to the current error amplifier (C-) to set the trickle charge current. FIGURE 2. Terminal connections. REV PGE 12

13 Device type 01 Case outline X Terminal number Terminal symbol Description 11 VO The output of the voltage error amplifier. The upper output clamp voltage of this amplifier is 5 V. 12 V- The inverting input to the voltage error amplifier. 13 C- The inverting input to the current error amplifier. 14 CO The output of the current error amplifier which is internally clamped to approximately 4 V. It is internally connected to the inverting input of the pulse width modulator (PWM) comparator. 15 CSO The output of the current sense amplifier which is internally clamped to approximately 5.7 V. 16 CS+ The non-inverting input to the current sense amplifier. This amplifier has a fixed gain of five and a common mode voltage range of from -250 mv to V CC. 17 CS- The inverting input to the current sense amplifier. This amplifier has a fixed gain of five and a common mode voltage range of from -250 mv to V CC. 18 RSET resistor to ground programs the oscillator charge current and the trickle control current for the oscillator ramp. The oscillator charge current is approximately: 1.75 / R SET. The trickle control current (I TRCK_CONTROL ) is approximately: / R SET. 19 OSC The oscillator ramp pin which has a capacitor (C T ) to ground. The ramp oscillates between approximately 1 V to 3 V and the frequency is approximated by: frequency = 1 / (1.2 C T R SET ). 20 R10 Input used to establish a differential voltage corresponding to the temperature of the thermistor. Connect a 10 k resistor to ground from this point. FIGURE 2. Terminal connections - continued. REV PGE 13

14 Charge state STT1 STT0 Trickle charge 0 0 Bulk charge 0 1 Over charge 1 0 Float charge 1 1 STT0 and STT1 are open collector outputs. The output is approximately 0.2 V for a logic 0. FIGURE 3. Charge state decode table. FIGURE 4. I CC versus temperature. REV PGE 14

15 4. VERIFICTION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPRTION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DL Land and Maritime maintains an online database of all current sources of supply at Vendor item drawing administrative control number 1/ 2/ 3/ Device manufacturer CGE code Top side marking Vendor part number -01XE UC2909EP UC2909MDWREP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ For the most current package and ordering information, see the package option addendum at the end of the manufacturer s data sheet, or contact the manufacturer. 3/ Package drawings, standard packaging quantities, thermal data, symbolization, and printed circuit board (PCB) design guidelines are available from the manufacturer. CGE code Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box Dallas, TX REV PGE 15