DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.

Transcription

1 REISIONS LTR DESCRIPTION DTE PPROED Update boilerplate to current MIL-PRF requirements. - PHN Thomas M. Hess B Correct number of pin in section PHN Thomas M. Hess Prepared in accordance with SME Y14.24 endor item drawing RE PGE RE PGE RE STTUS OF PGES RE B B B B B B B B B B B B B B PGE PMIC N/ PREPRED BY Phu H. Nguyen DL LND ND MRITIME Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen PPROED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITL, CURRENT LIMITED POWER DISTRIBUTION SWITCH, MONOLITHIC SILICON CODE IDENT. NO. 62/11620 RE B PGE 1 OF 14 DISTRIBUTION STTEMENT. pproved for public release. Distribution is unlimited. MSC N/

2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance current limited power distribution switch microcircuit, with an operating temperature range of -55 C to +125 C. 1.2 endor Item Drawing dministrative Control Number. The manufacturer s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: Device type(s). 62/ X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) Device type Generic Circuit function 01 TPS2041B-EP Current limited power distribution switch Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 5 JEDEC MO-178 Plastic small outline package Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator B C D E F Z Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Tin-lead alloy Other DL LND ND MRITIME 62/11620 RE B PGE 2

3 1.3 bsolute maximum ratings. 1/ Input voltage range (IN) (I(IN)) to +6 2/ Output voltage range (OUT) () to +6 2/ Input voltage range (EN ) () to +6 oltage range (OC ) (I(OC)) to +6 Continuous output current (I)... Internally limited Continuous total power dissipation... See dissipation ratings table. Operating virtual junction temperature range (TJ) C to 125 C Storage temperature range (Tstg) C to 150 C Lead temperature, soldering (1.6 mm (1/16 in) from case for 10 s) C Electrostatic discharge (ESD) protection: Human Body Model (HBM) (H2) Machine Model (MM) (M0) Charged Device Model (CDM) (C5) Dissipating ratings table: Package T 25 C Power ratings Derating factor bove T = 25 C T = 25 C Power rating T = 85 C Power rating Case X 285 mw 2.85 mw/ C 155 mw 114 mw 1.4 Recommended operating conditions. Input voltage (IN) (I(IN)) to 5.5 Input voltage (EN ) ()... 0 to 5.5 Continuous output current (OUT) (I)... 0 m to 500 m Operating virtual junction temperature (TJ) C to 125 C 2. PPLICBLE DOCUMENTS JEDEC SOLID STTE TECHNOLOGY SSOCITION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (pplications for copies should be addressed to the Electronic Industries lliance, 3103 North 10th Street, Suite 240 S, rlington, or online at 1/ Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2/ ll voltage are with respect to GND DL LND ND MRITIME 62/11620 RE B PGE 3

4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer s part number as shown in 6.3 herein and as follows:. Manufacturer s name, CGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer s part number and with items and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams Case outline. The case outline shall be as shown in and figure Terminal connections and terminal functions. The terminal connections and terminal functions shall be as shown in figure Functional block diagram. The functional block diagram shall be as shown in figure Test circuit and voltage waveforms. The test circuit and voltage waveforms shall be as shown in figure Turn on delay and rise time with 1 µf load. The turn on delay and rise time with 1 µf load shall be as shown in figure Turn off delay and fall time with 1 µf load. The turn off delay and fall time with 1 µf load shall be as shown in figure Turn on delay and rise time with 100 µf load. The turn on delay and rise time with 100 µf load shall be as shown in figure Turn off delay and fall time with 100 µf load. The turn off delay and fall time with 100 µf load shall be as shown in figure Short circuit current, device enables into short. The short circuit current, device enabled into short shall be as shown in figure Inrush current with different load capacitance. The inrush current with different load capacitance shall be as shown in figure Ω load connected to enabled device. The 3 Ω load connected to enabled device shall be as shown in figure Ω load connected to enabled device. The 2 Ω load connected to enabled device shall be as shown in figure 12. DL LND ND MRITIME 62/11620 RE B PGE 4

5 Power Switch TBLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ 3/ TJ Limits Unit Static drain source on state rds(on) I(IN) = 5 or 3.3, IO = C TJ 125 C 135 mω resistance, 5 or 3.3 operation Static drain source on state I(IN) = 2.7, IO = C TJ 125 C 150 resistance, 2.7 operation 4/ Rise time, output 4/ tr I(IN) = 5.5 TJ = 25 C 1.5 ms I(IN) = 2.7 CL = 1 µf 1 Fall time, output 4/ tf I(IN) = 5.5 RL = 10 Ω I(IN) = Enable Input (EEEE ) High level input voltage IH 2.7 I(IN) Low level input voltage IL 2.7 I(IN) Input current II = 0 or µ Turn on time 4/ ton CL = 100 µf, RL = 10 Ω 3 ms Turn off time 4/ toff CL = 100 µf, RL = 10 Ω 10 ms Current limit Short circuit output current Supply current Supply current, low level output Supply current, high level output I(IN) = 5, OUT connected to GND, device enable into short circuit No load on OUT, = 5.5 or = 0 No load on OUT, = 0 or = 5.5 Min Max TJ = 25 C C TJ 125 C TJ = 25 C 1 µ -55 C TJ 125 C 5 TJ = 25 C 60 µ -55 C TJ 125 C 70 Leakage current OUT connected to ground, -55 C TJ 125 C 1 TYP µ = 5.5 or = 0 Reverse leakage current I(OUT) = 5.5, IN = ground TJ = 25 C 0 TYP µ Under voltage lockout Low level input voltage, IN Hysteresis, IN TJ = 25 C 75 TYP m Overcurrent (OOOO ) Output low voltage, OL(/OC) IO(OC) = 5 m 0.4 Off state current 4/ O(OC) = 5 or µ OC deglitch 4/ OC assertion or deassertion 4 15 ms See footnotes at end of table. DL LND ND MRITIME 62/11620 RE B PGE 5

6 TBLE I. Electrical performance characteristics - Continuous. 1/ Thermal shutdown 5/ Test Symbol Conditions 2/ 3/ TJ Limits Unit Min Max Thermal shutdown threshold 4/ 135 C Recovery from thermal shutdown 4/ 125 C Hysteresis 4/ 10 TYP C 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Over recommended operating junction temperature range, I(IN) = 5.5, IO = 0.5, = 0 (unless otherwise noted). 3/ Pulse testing techniques maintain junction temperature close to ambient temperature; thermal effects must be accounted for separately. 4/ Specified by design. 5/ The thermal shutdown only reacts under overcurrent conditions. DL LND ND MRITIME 62/11620 RE B PGE 6

7 Case X b 5 PLS 0.20M c 5 4 PIN 1 INDEX RE 1 3 E E 1 GGE PLNE 0-8 e L L 1 D SEE DETIL DETIL SETING PLNE Dimensions Symbol Millimeters Symbol Millimeters Min Max Min Max 1.45 E E b e 0.95 BSC c L D L TYP NOTES: 1. ll linear dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side. 4. Falls within JEDEC MO-178 ariation. FIGURE 1. Case outline. DL LND ND MRITIME 62/11620 RE B PGE 7

8 Terminal number Terminal symbol I/O Terminal Functions 1 OUT O Power switch output 2 GND Ground 3 OC O Overcurrent, Open drain output, active low 4 EN I Enable input, logic low turns on power switch 5 IN I Input voltage FIGURE 2. Terminal connections and terminal functions. IN CS SEE NOTE OUT CHRGE PUMP EN DRIER CURRENT LIMIT OC ULO GND THERML SENSE DEGLITCH NOTICE:. CS = Current sense. FIGURE 3. Functional block diagram. DL LND ND MRITIME 62/11620 RE B PGE 8

9 OUT t r t f R L C L 90% 10% TEST CIRCUIT 50% 50% t on t off t on t off 90% 10% 90% 10% FIGURE 4. Test circuit and voltage waveforms. DL LND ND MRITIME 62/11620 RE B PGE 9

10 5 /div R L = 10 C L = 1 F T = 25 C 2 /div t - TIME s/div FIGURE 5. Turn-On delay and rise time with 1 µf load. 5 /div 2 /div R L = 10 C L = 1 F T = 25 C t - TIME s/div FIGURE 6. Turn-Off delay and fall time with 1 µf load. DL LND ND MRITIME 62/11620 RE B PGE 10

11 5 /div R L = 10 C L = 100 T = 25 C F 2 /div t - TIME s/div FIGURE 7. Turn-On delay and rise time with 100 µf load. 5 /div 2 /div R L = 10 C L = 100 T = 25 C F t - TIME s/div FIGURE 8. Turn-Off delay and fall time with 100 µf load. DL LND ND MRITIME 62/11620 RE B PGE 11

12 5 /div I 500 m/div t - TIME s/div FIGURE 9. Short circuit current, device enabled into short. 5 /div I = 5 R L = 10 T = 25 C 220 F I 500 m/div 100 F 470 F t - TIME s/div FIGURE 10. Inrush current with different load capacitance. DL LND ND MRITIME 62/11620 RE B PGE 12

13 O(OC) 2 /div I 500 m/div t - TIME - 2 ms/div FIGURE Ω Load connected to enable device. O(OC) 2 /div I 500 m/div t - TIME - 2 ms/div FIGURE Ω Load connected to enable device. DL LND ND MRITIME 62/11620 RE B PGE 13

14 4. ERIFICTION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPRTION FOR DELIERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DL Land and Maritime maintains an online database of all current sources of supply at endor item drawing administrative control number 1/ Device manufacturer CGE code endor part number Top Side Marking 62/ XE TPS2041BMDBTEP PXM 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CGE code Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box Dallas, TX DL LND ND MRITIME 62/11620 RE B PGE 14