V62/04613 DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO TITLE MICROCIRCUIT, DIGITAL, PC CARD CONTROLLERS, MONOLITHIC SILICON

Transcription

1 REVISIONS LTR DESCRIPTION DTE PPROVED dd new device case outline Y. Update boilerplate to current revision. - CFS Thomas M. Hess B Correct lead finish on last page. -CFS Thomas M. Hess C Update boilerplate paragraphs to current requirements. - phn Thomas M. Hess CURRENT DESIGN CTIVITY CGE CODE HS CHNGED NMES TO: DL LND ND MRITIME Prepared in accordance with SME Y14.24 Vendor item drawing REV PGE REV PGE REV STTUS OF PGES PMIC N/ Original date of drawing YY MM DD REV C C C C C C C C C C C C C C PGE PREPRED BY Phu H. Nguyen CHECKED BY Phu H. Nguyen PPROVED BY Thomas M. Hess CODE IDENT. NO TITLE MICROCIRCUIT, DIGITL, PC CRD CONTROLLERS, MONOLITHIC SILICON REV C PGE 1 OF 14 MSC N/ 5962-V030-12

2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance controllers microcircuit, with an operating temperature range of -40 C to +85 C. 1.2 Vendor Item Drawing dministrative Control Number. The manufacture rs PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: Device type(s). 1/ - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) Device type Generic Circuit function 01 PCI1520-EP PC card controllers Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 209 Plastic ball grid array Y 208 JEDEC MO-136 Plastic quad flatpack Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator B C D E Z Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other 1.3 bsolute maximum ratings. 2/ Supply voltage range, (V CC) V to +4.6 V Clamping voltage range, (V CCP, V CC, V CCB) V to +6.0 V Input voltage range, (V I): PCI, miscellaneous V to V CCP+0.5 V Card V to V CC+0.5 V Card B V to V CCB+0.5 V Fail safe V to V CC+0.5 V Output voltage range (V O): PCI, miscellaneous V to V CCP+0.5 V Card V to V CC+0.5 V Card B V to V CCB+0.5 V Fail safe V to V CC+0.5 V Input clamp current, I IK (V I < 0 or V I > V CC)... ±20 m 3/ Output clamp current, I OK (V O < 0 or V O >V CC)... ±20 m 4/ Storage temperature range, (T STG) C to +150 C 1/ Users are cautioned to review the manufacturers data manual for additional user information relating to this device. 2/ Stresses beyond those listed under absolute maximum rating may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. REV C PGE 2

3 1.4 Recommended operating conditions. 5/ Operation Min Max Unit Core voltage, (V CC) Commercial 3.3 V V PCI and miscellaneous I/O clamp voltage, 3.3 V V (V Commercial CCP) 5.0 V I/O clamp voltage, (V CC, V 3.3 V V CCB) Commercial 5.0 V High level input voltage, (V IH) 6/ PCI 3.3 V 0.5V CCP V CCP 5.0 V 2.0 V CCP 3.3 V 0.475V CC(/B) V CC(/B) 5.0 V 2.4 V CC(/B) V Low level input voltage, (V IL) 6/ Input voltage, (V I) Output voltage, (V O) 8/ Miscellaneous 7/ 2.0 V CC PCI 3.3 V 0 0.3V CCP 5.0 V V V CC(/B) 5.0 V Miscellaneous 7/ PCI 0 V CCP 0 V CC(/B) Miscellaneous 7/ 0 V CC PCI 0 V CC 0 V CC V V V Miscellaneous 7/ 0 V CC PCI and 1 4 Input transition time, (t t) (t r and t f) ns Miscellaneous 7/ 0 6 Operating ambient temperature range, (T ) PCI C 3/ pplies for external input and bidirectional buffers. V I > V CC does not apply to fail safe terminals. PCI terminals and miscellaneous terminals are measured with respect to V CCP instead of V CC. terminals are measured with respect to V CC or V CCB. The limit specified applies for a dc conditions. 4/ pplies for external output and bidirectional buffers. V O > V CC does not apply to fail safe terminals. PCI terminals and miscellaneous terminals are measured with respect to V CCP instead of V CC. terminals are measured with respect to V CC or V CCB. The limit specified applies for a dc conditions. 5/ Unused terminals (input or I/O) must be held high or low to prevent them from floating. 6/ pplies to external inputs and bidirectional buffers without hysteresis. 7/ Miscellaneous terminals are 15, 56, 68, 75, 83, 124, 137, 144, 158, and 177 for the PDV packaged device, and C11, C15, G18, H05, J15, L18, P07, P09, U08, and U11 for the GHK packaged device ( SUSPEND, GRST, CDx, and VSx terminals). 8/ pplies to external output buffers. REV C PGE 3

4 2. PPLICBLE DOCUMENTS JEDEC SOLID STTE TECHNOLOGY SSOCITION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at or from JEDEC Solid State Technology ssociation, 3103 North 10th Street, Suite 240 S, rlington, V ) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer s part number as shown in 6.3 herein and as follows:. Manufacturer s name, CGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer s part number and with items and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams Case outlines. The case outlines shall be as shown in and figure Terminal connections. The terminal connections shall be as shown in figure Block diagram. The block diagram shall be as specified in figure 3. REV C PGE 4

5 TBLE I. Electrical performance characteristics. 1/ Test Symbol Test condition -40 C T +85 C 3.0 V V CC 3.6 V 3.0 V V CC(P//B) 3.6 V 2/ 4.75 V V CC(P//B) 5.25 V 3/ PCI Operation Limits Unit unless otherwise noted I OH = -0.5 m 2/ 0.9V CC V I OH = -2.0 m 3/ 2.4 Min Max High level output voltage SPKROUT V OH I OH = -0.5 m 2/ 0.9V CC I OH = -1.0 m 3/ 2.4 I OH = m 2/ 0.9V CC I OH = m 3/ 2.4 Miscellaneous I OH = -4.0 m V CC-0.6 PCI I OL = 1.5 m 2/ 0.1V CC I OL = 6.0 m 3/ 0.55 Low level output voltage V OL I OL = 0.7 m 2/ 0.1V CC I OL = 0.7 m 3/ 0.55 SPKROUT I OL = 1.0 m 2/ 0.1V CC I OL = 1.0 m 3/ 0.55 Miscellaneous I OL = 4.0 m 0.5 High impedance, low level 4/ -1 µ output current Output terminals I OZL V I = V CC 5/ -1 High impedance, high 4/ 10 level output current Output terminals I OZH V I = V CC 6/ 5/ 25 Input terminals -1 Low level input current I/O terminals I IL V I = GND -10 Pullup terminals / 10 High level input current Input terminals I IH V I = V CC 7/ 5/ 20 I/O terminals 4/ 10 5/ 25 See footnotes at end of table. REV C PGE 5

6 TBLE I. Electrical performance characteristics - Continued. 1/ Test Symbol lternate Symbol PCI Clock/Reset timing requirements Test condition -40 C T +85 C 3.0 V V CC 3.6 V 3.0 V V CC(P//B) 3.6 V 2/ 4.75 V V CC(P//B) 5.25 V 3/ unless otherwise noted Cycle time, PCLK t c t cyc 30 ns Pulse duration (width), PCLK high t w(h) t high 11 Pulse duration (width), PCLK low t w(l) t low 11 Slew rate, PCLK t r, t f v/ t 1 4 V/ns Pulse duration (width), PRST Min Limits Max t w t rst 1 ms Setup time, PCLK active at end of PRST t su t rst-clk 100 µs Propagation delay time 8/ PCLK to shared signal valid delay time PCLK to shared signal invalid delay time PCI Timing Requirements t pd t val C L = 50 pf 8/ t inv 2 Enable time, high impedance to active delay time from PCLK t en t on 2 Disable time, active to high impedance delay time from PCLK t dis t off 28 Setup time before PCLK valid t su t su 7 Hold time after PCLK high t h t h 0 Unit 11 ns 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ For 3.3 V operation. 3/ For 5.0 V operation. 4/ For 3.6 V operation. 5/ For 5.25 V operation. 6/ For PCI and miscellaneous terminals, V I = V CCP. For terminals, V I = V CC(/B). 7/ For I/O terminals, input leakage (I IL and I IH) includes I OZ leakage of the disabled output. 8/ PCI shared signals are D31-D0, C/ BE3 -C/ BE 0, FRME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PR. REV C PGE 6

7 Case X Notes: 1. ll linear dimensions are in millimeters. 2. This drawing is subject to change without notice. Millimeters Symbol Min Max b D/E D1/E TYP e 0.80 TYP FIGURE 1. Case outlines. REV C PGE 7

8 Case Y Millimeters Symbol Min Max TYP b c 0.13 NOM D/E D1/E D2/E2 Notes: 1. ll linear dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. Falls within JEDEC MO-136. e TYP 0.50 TYP L FIGURE 1. Case outlines - Continued. REV C PGE 8

9 Case X 4 D12 D12 D1 D10 D10 G1 V CC V CC 5 PR PR D19 MFUNC0 MFUNC0 G2 D0 D0 6 GND GND E1 GND GND G3 D1 D1 7 V CC V CC E2 D7 D7 G5 D4 D4 8 D18 D18 E3 D9 D9 G6 C/ BE 0 C/ BE 0 9 GND GND E5 NC NC G14 _CD28 _D8 10 V CCP V CCP E6 D14 D14 G15 _CD30 _D9 11 D29 D29 E7 PERR PERR G17 _CD27 _D0 12 V CC V CC E8 FRME FRME G18 _ CCD 2 _ CD 2 13 REQ REQ E9 D19 D19 G19 V CC V CC 14 GND GND E10 IDSEL IDSEL H1 B_CD1 B_D4 15 MFUNC5 MFUNC5 E11 D27 D27 H2 B_CD2 B_D11 16 MFUNC1 MFUNC1 E12 D31 D31 H3 B_CD0 B_D3 B5 D15 D15 E13 RI _ OUT / PME RI _ OUT / PME H5 B_ CCD 1 B_ CD 1 B6 STOP STOP E14 MFUNC2 MFUNC2 H6 D2 D2 B7 IRDY IRDY E17 DT DT H14 _CSTSCHG _BVD1( B8 D17 D17 E18 LTCH LTCH H15 STSCHG / RI ) _ CCLKRUN _WP( IOIS 16 ) B9 D22 D22 E19 _CD13 _CD13 H17 _CUDIO _BVD2( SPKR ) B10 D24 D24 F1 D3 D3 H18 _ CSERR _ WIT B11 D28 D28 F2 D5 D5 H19 _ CINT _REDY( IREQ ) B12 D11 D11 F3 D6 D6 J1 B_CD4 B_D12 B13 GNT GNT F5 D8 D8 J2 B_CD3 B_D5 B14 C/ BE 3 C/ BE 3 F6 C/ BE 1 C/ BE 1 J3 B_CD6 B_D13 B15 MFUNC4 MFUNC4 F7 DEVSEL DEVSEL J5 B_CD5 B_D6 C5 D13 D13 F8 C/ BE 2 C/ BE 2 J6 B_RSVD B_D14 C6 SERR SERR F9 D20 D20 J14 _CD26 _0 C7 TRDY TRDY F10 D23 D23 J15 _CVS1 C8 D16 D16 F11 D26 D26 J17 _CD25 _1 C9 D21 D21 F12 D25 D25 J18 _CD24 _2 C10 PCLK PCLK F13 MFUNC3/IRQSER MFUNC3/IRQSER J19 V CC V CC C11 GRST GRST F14 SPKROUT SPKROUT K1 GND GND C12 D30 D30 F15 CLOCK CLOCK K2 B_CD7 B_D7 _ VS 1 C13 PRST PRST F17 _RSVD _D2 K3 B_CD8 B_D15 C14 MFUNC6/ CLKRUN MFUNC6/ CLKRUN F18 _CD29 _D1 K5 B_CC/ BE 0 B_ CE 1 C15 SUSPEND SUSPEND F19 GND GND K6 B_CD9 B_10 FIGURE 2. Terminal connections. REV C PGE 9

10 Case X Continued. K14 _CC/ BE 3 _ REG P1 GND GND U5 B_CD18 B_7 K15 _CD23 _3 P2 B_ CSTOP B_20 U6 B_CD21 B_5 K17 _ CREQ _ INPCK P3 B_ CDEVSEL B_21 U7 B_CC/ BE 3 B_ REG K18 _CD22 _4 P5 B_ CIRDY B_15 U8 B_CVS1 B_ VS 1 K19 VR_PORT VR_PORT P6 B_CCLK B_16 U9 B_CSTSCHG B_BVD1( STSCHG / RI ) L1 VR _ EN VR _ EN P7 B_CVS2 B_ VS 2 U10 B_CD29 B_D1 L2 B_CD10 B_ CE 2 P8 B_CD23 B_3 U11 _ CCD 1 _ CD 1 L3 B_CD11 B_ OE P9 B_ CCD 2 B_ CD 2 U12 _CD3 _D5 L5 B_CD13 B_ IORD P10 B_RSVD B_D2 U13 _CD7 _D7 L6 B_CD12 B_11 P11 _CD0 _D3 U14 _CD10 _ CE 2 L14 _CD21 _5 P12 _CD6 _D13 U15 _CD14 _9 L15 _ CRST _RESET P13 _CD8 _D15 V5 B_CD20 B_6 L17 _CD20 _6 P14 _CD12 _11 V6 B_CD22 B_4 L18 _CVS2 _ VS 2 P15 _CPR _13 V7 B_CD24 B_2 L19 _CD19 _25 P17 _ CSTOP _20 V8 B_ CINT B_REDY( IREQ ) M1 B_CD15 B_ IOWR P18 _ CGNT _ WE V9 B_CUDIO B_BVD2( SPKR ) M2 B_CD14 _9 P19 V CC V CC V10 B_CD28 B_D8 M3 B_CD16 B_17 R1 V CCB V CCB V11 B_CD31 B_D10 M5 B_RSVD B_18 R2 B_ CTRDY B_22 V12 _CD4 _D12 M6 B_CC/ BE 1 B_8 R3 B_ CFRME B_23 V13 _RSVD _D14 M14 _CCLK _16 R6 B_CD19 B_25 V14 _CC/ BE 0 _ CE 1 M15 _ CFRME _23 R7 B_ CREQ B_ INPCK V15 _CD13 _ IORD M17 _CC/ BE 2 _12 R8 B_CD26 B_0 W4 B_CD17 B_24 M18 _CD17 _24 R9 B_ CCLKRUN B_WP( IOIS 16 ) W5 B_ CRST B_RESET M19 _CD18 _7 R10 B_CD30 B_D9 W6 GND GND N1 V CC V CC R11 _CD2 _D11 W7 B_CD25 B_1 N2 B_CPR B_13 R12 _CD5 _D6 W8 V CC V CC N3 B_ CBLOCK B_19 R13 _CD9 _10 W9 B_ CSERR B_ WIT N5 B_ CGNT B_ WE R14 _CD15 _ IOWR W10 B_CD27 B_D0 N6 B_ CPERR B_14 R17 _RSVD _18 W11 NC 1/ NC 1/ N14 _ CBLOCK _19 R18 _ CPERR _14 W12 _CD1 _D4 N15 _ CDEVSEL _21 R19 GND GND W13 V CC V CC N17 _ CTRDY _22 T1 B_CC/ BE 2 B_12 W14 GND GND N18 _ CIRDY _15 T19 _CC/ BE 1 _8 W15 _CD11 _ OE N19 V CC V CC W16 _CD16 _17 1/ Terminal W11 is an NC on the PCI1520 to allow for terminal compatibility with the next generation of the devices. FIGURE 2. Terminal connections - Continued. REV C PGE 10

11 Case Y 1 D10 D10 36 B_CD16 B_17 71 B_CSERR B_WIT 2 D9 D9 37 B_CC/BE1 B_8 72 B_CUDIO B_BVD2(SPKR) 3 D8 D8 38 B_RDVD B_18 73 B_CSTSCHG B_BVD1 (STSCHG/RI) 4 C/BE0 C/BE0 39 V CC V CC 74 B_CCLKRUN B_WP(IOIS16) 5 D7 D7 40 B_CPR B_13 75 B_CCD2 B_CD2 6 GND GND 41 B_CBLOCK B_19 76 B_CD27 B_D0 7 D6 D6 42 B_CPERR B_14 77 B_CD28 B_D8 8 D5 D5 43 GND GND 78 B_CD29 B_D1 9 D4 D4 44 B_CSTOP B_20 79 B_CD30 B_D9 10 D3 D3 45 B_CGNT B_WE 80 B_RSVD B_D2 11 D2 D2 46 B_CDEVSEL B_21 81 NC 1/ NC 1/ 12 D1 D1 47 V CCB V CCB 82 B_CD31 B_D10 13 D0 D0 48 B_CCLK B_16 83 _CCD1 _CD1 14 V CC V CC 49 B_CTRDY B_22 84 _CD0 _D3 15 B_CCD1 B_CD1 50 B_CIRDY B_15 85 _CD2 _D11 16 B_CD0 B_D3 51 B_CFRME B_23 86 _CD1 _D4 17 B_CD2 B_D11 52 B_CC/BE2 B_12 87 _CD4 _D12 18 B_CD1 B_D4 53 B_CD17 B_24 88 _CD3 _D5 19 B_CD4 B_D12 54 B_CD18 B_7 89 _CD6 _D13 20 B_CD3 B_D5 55 B_CD19 B_25 90 _CD5 _D6 21 B_CD6 B_D13 56 B_CVS2 B_VS2 91 V CC V CC 22 B_CD5 B_D6 57 B_CD20 B_6 92 _RSVD _D14 23 B_RSVD B_D14 58 B_CRST B_RESET 93 _CD7 _D7 24 GND GND 59 B_CD21 B_5 94 _CD8 _D15 25 B_CD7 B_D7 60 B_CD22 B_4 95 GND GND 26 B_CD8 B_D15 61 B_CREQ B_INPCK 96 _CC/BE0 _CE1 27 B_CC/BE0 B_CE1 62 GND GND 97 _CD9 _10 28 B_CD9 B_10 63 B_CD23 B_3 98 _CD10 _CE2 29 VR_EN VR_EN 64 B_CC/BE3 B_REG 99 _CD11 _OE 30 B_CD10 B_CE2 65 B_CD24 B_2 100 _CD12 _11 31 B_CD11 B_OE 66 B_CD25 B_1 101 _CD13 _IORD 32 B_CD12 B_11 67 B_CD26 B_0 102 _CD15 _IOWR 33 B_CD13 B_IORD 68 B_CVS1 B_VS1 103 _CD14 _9 34 B_CD15 B_IOWR 69 B_CINT B_REDY(IREQ) 104 _CD16 _17 35 B_CD14 B_9 70 V CC V CC 105 _CC/BE1 _8 1/ Terminal 81 is an NC on the PCI1520 to allow for terminal compatibility with the next generation of devices. FIGURE 2. Terminal connections - Continued. REV C PGE 11

12 Case Y Continued. 106 _RSVD _ _CSTSCHG _BVD1 (STSCHG/RI) 176 D28 D _CPR _ _CCLKRUN _WP(IOIS16) 177 GRST GRST 108 _CBLOCK _ V CC V CC 178 D27 D _CPERR _ _CCD2 _CD2 179 D26 D GND GND 145 _CD27 _D0 180 V CCP V CCP 111 _CSTOP _ _CD28 _D8 181 D24 D _CGNT _WE 147 GND GND 182 PCLK PCLK 113 _CDEVSEL _ _CD29 _D1 183 IDSEL IDSEL 114 V CC V CC 149 _CD30 _D9 184 D23 D _CCLK _ _RSVD _D2 185 GND GND 116 _CTRDY _ _CD31 _D D22 D _CIRDY _ SPKROUT SPKROUT 187 D21 D V CC V CC 153 LTCH LTCH 188 D20 D _CFRME _ CLOCK CLOCK 189 D19 D _CC/BE2 _ DT DT 190 D18 D _CD17 _ MFUNC0 MFUNC0 191 D17 D _CD18 _7 157 MFUNC1 MFUNC1 192 D16 D _CD19 _ SUSPEND SUSPEND 193 C/BE2 C/BE2 124 _CVS2 _VS2 159 MFUNC2 MFUNC2 194 FRME FRME 125 _CD20 _6 160 MFUNC3/IRQSER MFUNC3/IRQSER 195 V CC V CC 126 _CRST _RESET 161 MFUNC4 MFUNC4 196 IRDY IRDY 127 _CD21 _5 162 MFUNC5 MFUNC5 197 TRDY TRDY 128 VR_PORT VR_PORT 163 MFUNC6/CLKRUN MFUNC6/CLKRUN 198 DEVSEL DEVSEL 129 _CD22 _4 164 C/BE3 C/BE3 199 GND GND 130 _CREQ _INPCK 165 RI_OUT/PME RI_OUT/PME 200 STOP STOP 131 _CD23 _3 166 GND GND 201 PERR PERR 132 _CC/BE3 _REG 167 D25 D SERR SERR 133 V CC V CC 168 PRST PRST 203 PR PR 134 _CD24 _2 169 GNT GNT 204 C/BE1 C/BE1 135 _CD25 _1 170 REQ REQ 205 D15 D _CD26 _0 171 D31 D D14 D _CVS1 _VS1 172 D30 D D13 D _CINT _REDY (IREQ) 139 _CSERR _WIT 174 V CC V CC 140 _CUDIO _BVD2 (SPKR) 173 D11 D D12 D D29 D29 FIGURE 2. Terminal connections - Continued. REV C PGE 12

13 Note: The interface is 68 terminals for and 16 bit s. In zoomed video mode 23 terminals are used for routing the zoomed video signals to the VG controller and audio system. FIGURE 3. Block diagram. REV C PGE 13

14 4. VERIFICTION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPRTION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CGE code Vendor part number Top-Side Marking -01X PCI1520IGHKEP PCI1520IEP -01YE PCI1520IPDVEP PCI1520IEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CGE code Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box Dallas, TX Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX REV C PGE 14