VNS3NV04DP-E. OMNIFET II fully autoprotected Power MOSFET. Features. Description SO-8

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1 VNS3NV4DP-E OMNIFET II fully autoprotected Power MOSFET Features Max on-state resistance (per ch.) R ON 2 mω Current limitation (typ) I LIMH 3.5 A Drain-source clamp voltage V CLAMP 4 V ECOPACK : lead free and RoHS compliant Automotive Grade: compliance with AEC guidelines Linear current limitation Thermal shutdown Short circuit protection Integrated clamp Low current drawn from input pin Diagnostic feedback through input pin ESD protection Direct access to the gate of the Power MOSFET (analog driving) Compatible with standard Power MOSFET Description SO-8 The VNS3NV4DP-E device is made up of two monolithic chips (OMNIFET II) housed in a standard SO-8 package. The OMNIFET II is designed using STMicroelectronics VIPower M-3 technology and is intended for replacement of standard Power MOSFETs in up to 5 khz DC applications. Built-in thermal shutdown, linear current limitation and overvoltage clamp protect the chip in harsh environments. Fault feedback can be detected by monitoring voltage at the input pin Table. Device summary Package Tube Order codes Tape and reel SO-8 VNS3NV4DP-E VNS3NV4DPTR-E September 23 Doc ID 8529 Rev 2 /2

2 Contents VNS3NV4DP-E Contents Block diagram and pin description Electrical specifications Absolute maximum ratings Thermal data Electrical characteristics Electrical characteristics curves Protection features Overvoltage clamp protection Linear current limiter circuit Overtemperature and short circuit protection Status feedback Package and packing information ECOPACK packages SO-8 mechanical data SO-8 packing information Revision history /2 Doc ID 8529 Rev 2

3 VNS3NV4DP-E List of tables List of tables Table. Device summary Table 2. Absolute maximum ratings Table 3. Thermal data Table 4. Off Table 5. On Table 6. Dynamic Table 7. Switching Table 8. Source drain diode Table 9. Protections Table. SO-8 mechanical data Table. Document revision history Doc ID 8529 Rev 2 3/2

4 List of figures VNS3NV4DP-E List of figures Figure. Block diagram Figure 2. Configuration diagram (top view) Figure 3. Current and voltage conventions Figure 4. Switching time test circuit for resistive load Figure 5. Test circuit for diode recovery times Figure 6. Unclamped inductive load test circuits Figure 7. Input charge test circuit Figure 8. Unclamped inductive waveforms Figure 9. Source-drain diode forward characteristics Figure. Static drain-source on resistance Figure. Derating curve Figure 2. Static drain-source on resistance vs input voltage (part ) Figure 3. Static drain-source on resistance vs input voltage (part 2) Figure 4. Transconductance Figure 5. Static drain-source on resistance vs Id Figure 6. Transfer characteristics Figure 7. Turn-on current slope (part ) Figure 8. Turn-on current slope (part 2) Figure 9. Input voltage vs input charge Figure 2. Turn-off drain source voltage slope (part ) Figure 2. Turn-off drain-source voltage slope (part 2) Figure 22. Capacitance variations Figure 23. Switching time resistive load (part ) Figure 24. Switching time resistive load (part ) Figure 25. Output characteristics Figure 26. Normalized on resistance vs temperature Figure 27. Normalized input threshold voltage vs temperature Figure 28. Normalized current limit vs junction temperature Figure 29. Step response current limit Figure 3. SO-8 package dimension Figure 3. SO-8 tube shipment (no suffix) Figure 32. Tape and reel shipment (suffix TR ) /2 Doc ID 8529 Rev 2

5 VNS3NV4DP-E Block diagram and pin description Block diagram and pin description Figure. Block diagram DRAIN DRAIN2 OVERVOLTAGE CLAMP OVERVOLTAGE CLAMP INPUT GATE CONTROL GATE CONTROL INPUT2 OVER TEMPERATURE LINEAR CURRENT LIMITER LINEAR CURRENT LIMITER OVER TEMPERATURE SOURCE SOURCE2 Figure 2. Configuration diagram (top view) SOURCE INPUT SOURCE 2 INPUT DRAIN DRAIN DRAIN 2 DRAIN 2 Doc ID 8529 Rev 2 5/2

6 Electrical specifications VNS3NV4DP-E 2 Electrical specifications Figure 3. Current and voltage conventions I IN R IN I D INPUT DRAIN I V IN2 R IN IN2 INPUT 2 DRAIN 2 I D2 V DS V IN2 SOURCE SOURCE 2 V DS 2. Absolute maximum ratings Stressing the device above the rating listed in the Absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to Absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE program and other relevant quality document. Table 2. Absolute maximum ratings Symbol Parameter Value Unit V DSn Drain-Source Voltage (V INn = V) Internally clamped V V INn Input voltage Internally clamped V I INn Input current +/- 2 ma R IN MINn Minimum input series impedance 22 Ω I Dn Drain current Internally limited A I Rn Reverse DC output current -5.5 A V ESD Electrostatic discharge (R =.5 KΩ, C = pf) 4 V V ESD2 Electrostatic discharge on output pins only (R = 33 Ω, C=5pF) 65 V P tot Total dissipation at T c =25 C 4 Ω T j Operating junction temperature Internally limited C T c Case operating temperature Internally limited C T stg Storage temperature -55 to 5 C 6/2 Doc ID 8529 Rev 2

7 VNS3NV4DP-E Electrical specifications 2.2 Thermal data Table 3. Thermal data Symbol Parameter Max value Unit R thj-lead Thermal resistance junction-lead (per channel) 3 C/W R thj-amb Thermal resistance junction-ambient 8 () C/W. When mounted on a standard single-sided FR4 board with 5mm 2 of Cu (at least 35 μm thick) connected to all DRAIN pins of the relative channel 2.3 Electrical characteristics Values specified in this section are for -4 C < T j < 5 C, unless otherwise stated. Table 4. Off Symbol Parameter Test conditions Min Typ Max Unit V CLAMP V CLTH V INTH I ISS V INCL I DSS Drain-source clamp voltage Drain-source clamp threshold voltage Input threshold voltage Supply current from input pin Input-source clamp voltage Zero input voltage drain current (V IN =V) V IN =V; I D =.5 A V V IN =V; I D =2mA 36 V V DS =V IN ; I D =ma V V DS =V; V IN = 5 V 5 µa I IN =ma V I IN =-ma V V DS =3V; V IN =V; T j =25 C 3 µa V DS =25V; V IN =V 75 µa Table 5. On Symbol Parameter Test conditions Min Typ Max Unit R DS(on) Static drain-source on resistance V IN =5V; I D =.5 A; T j = 25 C 2 mω V IN =5V; I D =.5 A 24 mω T j = 25 C, unless otherwise specified Table 6. Dynamic Symbol Parameter Test conditions Min Typ Max Unit g () Forward fs V transconductance DD =3V; I D =.5A 5. S C OSS Output capacitance V DS =3V; f=mhz; V IN =V 5 pf Doc ID 8529 Rev 2 7/2

8 Electrical specifications VNS3NV4DP-E Table 7. Switching Symbol Parameter Test conditions Min Typ Max Unit t d(on) Turn-on delay time 9 3 ns t V DD =5V; I D =.5A; r Rise time ns V gen =5V; R gen =R IN t d(off) Turn-off delay time MIN = 22 Ω (see Figure 4) ns t f Fall time ns t d(on) Turn-on delay time µs t V DD =5V; I D =.5A; r Rise time µs V gen =5V; R gen =2.2KΩ t d(off) Turn-off delay time (see Figure 4) 3.3. µs t f Fall time µs (di/dt) on Q i Turn-on current slope Total input charge V DD =5V; I D =.5A; V gen =5V; R gen =R IN MIN = 22 Ω V DD =2V; I D =.5 A; V IN =5V; I gen =2.3mA (see Figure 7) 4.7 A/µs 8.5 nc Table 8. Source drain diode Symbol Parameter Test conditions Min Typ Max Unit V () SD t rr Q rr I RRM Forward on voltage I SD =.5A; V IN =V.8 V Reverse recovery time Reverse recovery charge Reverse recovery current I SD =.5 A; di/dt = 2 A/µs; V DD =3V; L=2µH (see Figure 5) 7 ns 37 µc.7 A. Pulsed: Pulse duration = 3 µs, duty cycle.5% -4 C < T j < 5 C, unless otherwise specified Table 9. Protections Symbol Parameter Test conditions Min Typ Max Unit I lim Drain current limit V IN =5V; V DS =3V A t dlim Step response current limit V IN =5V; V DS = 3 V µs T jsh Overtemperature shutdown C T jrs Overtemperature reset 35 C I gf Fault sink current V IN =5V; V DS =3V; T j =T jsh 5 2 ma E as Single pulse avalanche energy Starting T j =25 C; V DD =24V; V IN =5V; R gen =R IN MIN =22Ω; L=24mH (see Figure 6 and Figure 8) mj 8/2 Doc ID 8529 Rev 2

9 VNS3NV4DP-E Electrical specifications Figure 4. Switching time test circuit for resistive load V D R gen V gen I D 9% t r % V gen t d(on) td(off) t f t t Figure 5. Test circuit for diode recovery times D A A I OMNIFET FAST DIODE L=uH S B B 22Ω R gen I OMNIFET D V DD V gen S 8.5 Ω Doc ID 8529 Rev 2 9/2

10 Electrical specifications VNS3NV4DP-E Figure 6. Unclamped inductive load test circuits R GEN V IN P W Figure 7. Input charge test circuit VIN GEN ND83 /2 Doc ID 8529 Rev 2

11 VNS3NV4DP-E Electrical specifications Figure 8. Unclamped inductive waveforms Doc ID 8529 Rev 2 /2

12 Electrical specifications VNS3NV4DP-E 2.4 Electrical characteristics curves Figure 9. Source-drain diode forward characteristics Figure. Static drain-source on resistance Vsd (mv) 5 Vin=V Rds(on) (mohms) 9 8 Tj=-4ºC Vin=2.5V Tj=25ºC Tj=5ºC Id (A) Id(A) Figure. Derating curve Figure 2. Static drain-source on resistance vs input voltage (part ) Rds(on) (mohms) Tj=5ºC Id=3.5A Id=A Tj=25ºC Tj=-4ºC Id=3.5A Id=A Id=3.5A Id=A Vin(V) Figure 3. Static drain-source on resistance vs input voltage (part 2) Figure 4. Transconductance Rds(on) (mohms) Gfs (S) Id=.5A Tj=5ºC Vds=3V Tj=-4ºC Tj=25ºC Tj=5ºC 4 75 Tj=25ºC Tj=-4ºC Vin(V) Id (A) 2/2 Doc ID 8529 Rev 2

13 VNS3NV4DP-E Electrical specifications Figure 5. Static drain-source on resistance vs Id Figure 6. Transfer characteristics Rds(on) (mohms) Vin=5V 2 Tj=5ºC Tj=25ºC 75 5 Tj= - 4ºC Id (A) Idon (A) Vds=3.5V Tj=5ºC Tj=-4ºC Tj=25ºC Vin (V) Figure 7. Turn-on current slope (part ) Figure 8. Turn-on current slope (part 2) di/dt(a/us) 5 di/dt(a/usec) Vin=5V Vdd=5V Id=.5A.5.25 Vin=3.5V Vdd=5V Id=.5A Rg(ohm) Rg(ohm) Figure 9. Input voltage vs input charge Figure 2. Turn-off drain source voltage slope (part ) Vin (V) dv/dt(v/usec) Vds=V Id=.5A Vin=5V Vdd=5V Id=.5A Qg (nc) Rg(ohm) Doc ID 8529 Rev 2 3/2

14 Electrical specifications VNS3NV4DP-E Figure 2. Turn-off drain-source voltage slope (part 2) Figure 22. Capacitance variations dv/dt(v/usec) Vin=3.5V Vdd=5V Id=.5A C(pF) f=mhz Vin=V Rg(ohm) Vds(V) Figure 23. Switching time resistive load (part ) Figure 24. Switching time resistive load (part ) t(usec) 4 t(nsec) Vdd=5V Id=.5A Vin=5V td(off) tr tr Vdd=5V Id=.5A Rg=22ohm tf td(on) td(off) tf td(on) Rg(ohm) Vin(V) Figure 25. Output characteristics Figure 26. Normalized on resistance vs temperature Id (A) Vin=5V Vin=4V Vin=3V Rds(on) (mohm) Vin=5V Id=.5A Vds (V) Tc )ºC) 4/2 Doc ID 8529 Rev 2

15 VNS3NV4DP-E Electrical specifications Figure 27. Normalized input threshold voltage vs temperature Figure 28. Normalized current limit vs junction temperature Vinth (V) Ilim (A) Vds=Vin Id=mA Vin=5V Vds=3V Tc (ºC) Tc (ºC) Figure 29. Step response current limit Tdlim(usec) Vin=5V Rg=22ohm Vdd(V) Doc ID 8529 Rev 2 5/2

16 Protection features VNS3NV4DP-E 3 Protection features During normal operation, the INPUT pin is electrically connected to the gate of the internal power MOSFET through a low impedance path. The device then behaves like a standard power MOSFET and can be used as a switch from DC up to 5 KHz. The only difference from the user s standpoint is that a small DC current I ISS (typ. µa) flows into the INPUT pin in order to supply the internal circuitry. The following sections describe the device features. 3. Overvoltage clamp protection Internally set at 45 V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads. 3.2 Linear current limiter circuit Limits the drain current I D to I lim whatever the INPUT pin voltages. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold T jsh. 3.3 Overtemperature and short circuit protection These are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs in the range 5 to 9 C, a typical value being 7 C. The device is automatically restarted when the chip temperature falls of about 5 C below shutdown temperature. 3.4 Status feedback In the case of an overtemperature fault condition (T j > T jsh ), the device tries to sink a diagnostic current I gf through the INPUT pin in order to indicate fault condition. If driven from a low impedance source, this current may be used in order to warn the control circuit of a device shutdown. If the drive impedance is high enough so that the INPUT pin driver is not able to supply the current I gf, the INPUT pin falls to V. This however not affects the device operation: no requirement is put on the current capability of the INPUT pin driver except to be able to supply the normal operation drive current I ISS. Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL Logic circuit. 6/2 Doc ID 8529 Rev 2

17 VNS3NV4DP-E Package and packing information 4 Package and packing information 4. ECOPACK packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. 4.2 SO-8 mechanical data Table. Dim. SO-8 mechanical data mm Min. Typ. Max. A.75 A..25 A2.25 b c.7.23 D () E E (2) e.27 h.25.5 L.4.27 L.4 k 8 ccc.. Dimension D does not include mold Flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed.5 mm in total (both side). 2. Dimension E does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed.25 mm per side. Doc ID 8529 Rev 2 7/2

18 Package and packing information VNS3NV4DP-E Figure 3. SO-8 package dimension 623 D 8/2 Doc ID 8529 Rev 2

19 VNS3NV4DP-E Package and packing information 4.3 SO-8 packing information Figure 3. SO-8 tube shipment (no suffix) B C A Base Q.ty Bulk Q.ty 2 Tube length (±.5) 532 A 3.2 B 6 C (±.).6 All dimensions are in mm. Figure 32. Tape and reel shipment (suffix TR ) REEL DIMENSIONS Base Q.ty 25 Bulk Q.ty 25 A (max) 33 B (min).5 C (±.2) 3 F 2.2 G (+ 2 / -) 2.4 N (min) 6 T (max) 8.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 48 rev. A, Feb. 986 Tape width W 2 Tape Hole Spacing P (±.) 4 Component Spacing P 8 Hole Diameter D (±./-).5 Hole Diameter D (min).5 Hole Position F (±.5) 5.5 Compartment Depth K (max) 4.5 Hole Spacing P (±.) 2 All dimensions are in mm. End Start Top cover tape No components 5mm min Components Empty components pockets saled with cover tape. No components 5mm min User direction of feed Doc ID 8529 Rev 2 9/2

20 Revision history VNS3NV4DP-E 5 Revision history Table. Document revision history Date Revision Changes 9-Mar-2 Initial release. 8-Sep-23 2 Updated Disclaimer 2/2 Doc ID 8529 Rev 2

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