Precise Pulse Width Measurement in Write Pre-compensation Test

Transcription

1 Precise Pulse Width Measurement in Write Pre-compensation Test Hideo Okawara Agilent Technologies International Japan, Ltd. Tokyo, Japan Abstract Bit density on platters in hard disk drives gets so crowded that the signal stream read out of the magnetic media involves inter-symbol interference. In order to reduce the effect write data timing is tweaked according to specific bit patterns. This "write pre-compensation" is a tiny pulse width modification. Device manufacturers test this functionality by generating a special clock stream whose pulse width is very narrow. Time interval analyzers (TIA) can measure this pulse width precisely. However, the drawback of this is the requirement of a wide analog bandwidth and the need to compensate for a DC signal offset. Compared to a TIA approach, the use of a waveform sampler is shown to be simple, less costly and provides an appropriate capability. This article describes that phase increments of the fundamental frequency component can indicate pulse width increments. A data processing based on fast Fourier transform is described. DC shift has no influence in this method. A measurement instrument does not need a wide analog bandwidth. 1. Introduction 1.1 Write Pre-compensation Data density on magnetic media of hard disk drives (HDD) is increasing yearly. Magnetic transitions in track sectors is getting extremely packed to the extent that the signal read out of the media often encounters inter-symbol interference (ISI) according to specific bit patterns.[1] Figure 1 explains how ISI occurs in reading magnetic media. When a write current in a magnetic head appears as a square waveform shown in Figure 1(a), the media is magnetized according to the head current direction. (Figure 1(b)) When reading data from the media, the head picks up bipolar pulse signals at magnetization boundaries (dotted mountain-shaping waveforms in Figure 1(c)). When the adjacent read-out pulses are too close, the two pulses are combined and induce ISI as shown as a bold line in Figure 1(c). ISI affects original peak locations that carry information. Thus, the peak shifts cause bit error eventually. In order to mitigate the ISI effect, a tiny timing tweak is applied in advance when writing data on the magnetic media. That is, at specific bit sequences, anticipated peak shift affected by ISI is accounted for in the write operation by timing shift of a finite amount. This operation is called "write pre-compensation." (Figure 2) Figure 1 Inter-symbol Interference When HDD are shipped from manufacturers, each module is tested, and most appropriate timing-tweak values of the module depicted as t a, t b and t c in Figure 2 are stored inside the drive. Figure 2 Write Pre-compensation The write pre-compensation is realized by precisely modifying of pulse width of a unit length of bit denoted by T in Figure 2. When certain susceptible bit sequences appear, the pulse width T is modified (extended or shrunk). For instance, if the bit rate of a read channel is 1Gbps, the 972 ITC INTERNATIONAL TEST CONFERENCE /04 $20.00 Copyright 2004 IEEE

2 nominal T is 1ns. Then adjustable timing usually ranges from tens of pico-seconds to hundreds of pico-seconds. 1.2 The Test Problem and Basic DFT Setup Testing of the write pre-compensation is a measurement of accurate narrow pulse widths. The pulse width T discussed here ranges, for instance, about 1ns or less than that. The width is modified in the order of 10ps. Figure 4 A test mode bit sequence: The paper is organized as follows: Section 2 outlines a traditional approach and drawbacks of using a TIA; as further background. Section 3 discusses the pros & cons of a time domain test using waveform sampler. Section 4 discusses the new low cost method employing phase analysis via a waveform sampler. Sections 5 & 6 present comments and conclusions. Figure 3 Test Setup of Write Pre-compensation Design for testability (DFT) is provided in actual read channel 1 devices. A simplified test setup is shown in Figure 3. A device pin OSC is supplied a heart beat clock by a digital channel. The clock is raised up to the bit rate of the read channel by a phase locked loop (PLL) circuit. For the write pre-compensation test, the device is set up a test mode, in which the device generates repetition of pre-selected test-bit sequences such as 1000, or So it becomes a clock stream whose frequency is much lower than the bit rate, such as 1/4 or 1/6, depending on the set of bit sequences. For instance, if the bit rate is 1Gbps, the test signal frequency is 250MHz or 166MHz in the patterns above. And duty ratio of the clock is 25%, 16% or 33%. These clocks can be monitored at the differential output pins named WRD and WRDb in Figure 3. The pulse width with no delay is the reference width. It is T for or 2T for When a register built in the device is set a certain value, the pulse width is slightly modified as T+t 1, t 2, t 3, etc. in Figure 4. The register consists of 4 or 5 bits space. The pulse width can be modified by 16 or 32 different values. The reference width T that is no delay condition is one of them. The issue reduces to testing the ability to write reference pulses incremented by t 1, t 2, t 3, etc. Then the linearity of the widths vs. register values is evaluated. 1 Conventionally called read channel actually includes both read and write functions. 2. Measurement by TIA 2.1 Basic Instrument for Time Measurement The first option that we select for the pulse width measurement is a time interval analyzer (TIA). This resource sets an appropriate threshold level in the mid range of the pulse swing as described in Figure 4. When a test signal crosses over the threshold, the instrument starts/stops counting the width of the pulse. Figure 5 Clock Stream 2.2 Analog Bandwidth Required The sampled signal traverses a transmission network in order to reach the measurement instrument. Thus, it is important that care be taken not to degrade the observed (1) 973

3 waveform. To do this, the signal routing path must have very wide analog bandwidth. Consider the following situation; Figure 5 shows an ideal clock signal whose duty ratio is 2a/T o. Equation (1) describes the waveform.[2] The equation is an infinite series of cos(nωt). Actual signal paths have a certain analog bandwidth so that the series is limited at a certain number of harmonics. 2.3 DC Blocking Capacitor & Setting TIA Threshold A read channel device is a single power supply device, so the output of the write function has a DC offset. Usually it is a differential output with impedance approximately 100ohms. The output driver in the device may not have power to drive 50-ohm terminations connected to the ground at both differential output pins. Thus, DC blocking capacitors are often employed to pick up AC signal stream as shown in Figure 8. Figure 6 Waveform Constructed with up to 15 th Harmonics Figure 6(a) shows the waveform of constructed containing the fundamental and harmonics up to the 15 th. Figure 8 DC Blocking Capacitors If the DC offset is removed, the positive area and the negative area of the AC signal are balanced eventually. Figure 9 Effect of DC Blocking Figure 7 Pulse Width Error vs. Harmonics Figure 7 shows a simulation result of the accuracy of incremental pulse width of T calculated vs. harmonics numbers. The graph (b) shows T errors when T=0.5T. The result is that, in order to achieve less than 10% of accuracy, the signal path should be designed having at least 7 times wider than the clock frequency. This bandwidth is greater than 1GHz when T=1ns so that special care may be necessary in designing DUT board and its material selection. As Figure 9 shows, the test signal location varies across voltage direction according to the duty ratio of the signal. This is extremely inconvenient for TIA because it requires a strict threshold to catch instances that the signal crosses over it. That is, an appropriate threshold level to measure correct pulse widths must be adjusted every time. It is almost impossible for the instrument to do the job without knowing the waveform information in advance. This is a weak point of the threshold-base approach. 974

4 3. Waveform Analysis by Sampler Direct Pulse Width Calculation 3.1 Measurement with Waveform Sampler When whole waveform should be measured, a real time digitizer or under-sampling sampler is suitable instrument. In the cases targeted here, the test signal clock frequency discussed is usually higher than the input analog bandwidth of regular real time digitizers. Therefore, under-sampling type samplers are appropriate to cope with the test signals. If the sampling condition is carefully programmed, a single and whole cycle of the clock waveform can be reconstructed by reshuffling the sampled points in order of phase angle. When a single cycle of the clock waveform is reconstructed, calculation of the pulse width is simple (as will be shown). Note that a TIA is a dedicated resource while a sampler is more general purpose. Thus, utilizing samplers can lead to a reduced test cost. This is an advantage of using a sampler over TIA. 3.2 Waveform Reconstruction Procedure Figure 10 Waveform Reconstruction Figure 10 shows the waveform reconstruction procedure. The test signal has a period of Tsignal. A sampler runs at a rate of Fs (1/Fs=Ts), which is Teqs longer than K(=2) cycles of the test signal. Teqs is an equivalent sampling rate. It captures Npoints(=16) of data total, being aligned into Ncycles(=3) of the test signal waveform. In order to reconstruct a single cycle of the original waveform, you need to reshuffle the raw data by 3. Mixed signal testers usually provide a dedicated data processing command for reshuffling. For successful processing, Ncycles and Npoints must have no common divisors [3]. Npoints is usually a number of 2 n for conventional fast Fourier transform (FFT), and then Ncycles should be selected to be an odd number. The sampling conditioning is expanded as follows. Npoints*Teqs=Ncycles*Tsignal (2) Teqs=Tsignal*Ncycles/Npoints (3) Ts=K*Tsignal+Teqs (4) The actual sampling rate is derived combining Equations (3) and (4) as follows. Fs=Fsignal*Npoints/(K*Npoints+Ncycles) (5) Fsignal=Fs*(K+Ncycles/Npoints) (6) When multiple cycles (Ncycles) of a test signal are captured, these can be reshuffled by Ncycles to reconstruct the primitive or a single cycle of fundamental waveform. The time step is now Tsignal/Npoints. 3.3 Pulse Width Calculation The pulse width can then be found by simply calculating the time difference between rising and falling edges. Figure 7(a) helps to understand the procedure. Select a threshold as the pulse width becomes the nominal width of T when no delay. With calculating each pulse width of reconstructed waveforms at the same threshold, T is calculated by subtracting T. Then T linearity can be evaluated. Recall from section 2 that, if test signal paths employ DC blocking capacitors, the position of captured waveform would shift vertically. In sampler applications the whole waveform is reconstructed so that finding the maximum and the minimum levels of the waveform can do adjusting the waveform location in the vertical direction. Since the pulse width is measured by calculating the time difference between rising and falling edges, the whole waveform itself must be maintained in its original shape in this method too (as discussed in the TIA section). If the analog bandwidth of the path between chip-signal to instrument is not wide enough, some harmonics would be filtered and the signal deteriorates. This is a weakness of direct pulse width measurement. Therefore, here the drawback of an analog bandwidth requirement is similar to that required for the TIA method. That is a bandwidth that is several times wider than the fundamental frequency of the clock. In calculating the pulse width, limited parts of rising and falling edges are counted so that most of the sampling points cannot contribute to calculation. This could affect accuracy and stability of the result. 975

5 4. Phase Analysis by Sampler Indirect Pulse Width Calculation 4.1 Orthogonal Demodulation Method A frequency/phase movement analysis method using a real time digitizer has been introduced in ITC2002.[4] It is called Orthogonal Demodulation Method (ODM) in the article. It includes an experiment of single edge movement detection. The discussion was limited to real-time digitizers. Figure 11 shows the data processing procedure used in the ODM. In this method only the fundamental component of the test signal clock was analyzed to detect the edge shift, and still it obtained consistent results. However, the results showed a half value of the actual shifting quantity. At the time of the article, no reason for this was offered. In the subsequent section, the effect is explained and used. The Fourier transform of x(t) in Equation (1), X(ω) is shown in Equation (8). Then the Fourier transform of the delayed waveform in Figure 12 can be expressed as Equation (9) by the rule of time shift in Fourier transform pair.[5] (9) By comparing Equations (8) to (9), the time shift of a causes each one of the frequency components to be rotated by ωa. This means that you can determine how much the clock is delayed by analyzing the rotation of the fundamental component. Figure 13 explains the whole story. (8) Figure 11 ODM Data Processing Diagram Figure 13 Calculation Sequence 4.2 Pulse Width vs. Delay When the waveform shown in Figure 5 is delayed by the time of a across the time axis, the waveform can be shown in Figure 12, and then Equation (1) is modified into Equation (7). The waveform itself does not change, and the pulse width is 2a. Considering the situation of write pre-compensation, the rising edge of a clock train is fixed while the falling edge is incremented by small amount of time. As the bottom diagram in Figure 13, when substituting a to (a+ ), the phase rotation becomes -ω(a+ ). Also the pulse width 2a is replaced with 2(a+ )=2a+2. Therefore when you find the phase increment of the fundamental by ω, it means the pulse width is increased by 2. This is why ODM detected a half of the increment of an edge shift. When using ODM, if the phase increment is obtained, the correct edge shift increment can be calculated by doubling the phase increment as 2. Figure 12 Delayed Clock Pulse Train (7) ODM looks at only the fundamental component of the clock. If the bandwidth of the signal path is so narrow that only the fundamental component can go through it, the waveform looks a simple sinusoidal waveform. Even if it looks a simple sine wave, analyzing the phase rotation of the fundamental can extract the increment of pulse width. From the other angle, limited bandwidth of a signal transmission path still retains correct pulse width 976

6 information. And in this method, all the sampled data points are used in the calculation so that the result is more robust than the method based on rising/falling edges. These are advantages over the direct pulse width calculation discussed in previous section. The calculation procedure of ODM was fairly complicated as shown in Figure 11. The measured waveform was multiplied by a cos and a sin arrays. Each of them was processed with digital filtering, arctangent and differentiation operations. Cumbersome data processing can demand more test time or cost. However, even if it is a single-shot event, ODM can detect the edge shift. If an event is single-shot, a real-time digitizer must be employed for measurements. The phase analysis work discussed in the subsequent text eliminates this problem. 4.3 Phase Analysis Method Write pre-compensation testing can be executed under the test mode and a continuous clock stream. Once the pulse width is modified, it can be maintained and repeated until the register is refreshed with a different value. Therefore an under-sampling type sampler can perform measurement so that a testable frequency range is extended. With this FFT phase analysis method can be applied to a DC eliminated measurement path described in Figure 8. This is because the DC component bears no impact. This is an important benefit of the method. Write pre-compensation test is a relative measurement of pulse width, looking at the reference width T. All the measurement sequences including register setups should be done continuously by a single shot execution without interrupting the test signal clock every time. If 16 different pulse widths are available, all the 16 register- writings and the measurements should be done during a single execution. If every time a sampler would be triggered independently, the capturing might start at different timing location of the signal. Then you cannot compare phase increments. From the throughput's point of view, it is a good practice to have all the measurements completed during a single execution without stopping the clock. For the test, the phase information of the fundamental component is required -- an FFT is good enough to do the job. FFT is the most typical signal processing in mixed signal tests. More than 99% of signal processing is based on FFT so that mixed signal testers provide FFT and related commands. The procedure involves selecting an appropriate sampler according to the frequency range required for the fundamental component. Then, capture the waveform and use the FFT to extract the phase of the fundamental spectrum. Figure 14 Continuous Measurement Sequence An integer number of cycles (Ncycles) of test signal clocks must be captured in the sampled waveform array. The sampling condition can be decided following the process of section 3.2. The fundamental component appears at the bin number Ncycles in a spectrum data array of FFT result. It is a complex number, describing Hn. complex(hn) = Xn + j * Yn (10) phase(hn) = arctangent( Yn / Xn ) = Pn (11) Phase Pn can be calculated as the sequences of (10) and (11). When two measurements are executed at two different pulse widths, supposing that phases of Pn 0 and Pn 1 are derived. The pulse width increment deltapw can be calculated as follows. Figure 14 shows the continuous measurement strategy. The register is set up the pulse widths sequentially as PW1, PW2, and so forth. Then the device generates clock trains of PW1, PW2, and so on, while the sampler captures the whole clock train waveforms. Pick up valid areas from the captured waveform, and do FFT. Each FFT segment must contain an integer number of cycles of test signal clock. As the graph (c) describes, the discarded time spaces between adjacent FFT segments should correspond to the time of a multiple of FFT unit period to maintain the consistent relative phase relationship among all the FFT segments. deltapw = 2 * ( Pn 0 - Pn 1 ) (12) The phase increment detected should be doubled to convert it into the increment of the pulse width as depicted in Figure

7 Figure 16 Imperfect Rising by Low Slew Rate Figure 15 Example Result A simulated test result example is shown in Figure 15. The test signal clock is T=1ns and then 6T clock period is 6ns or MHz. A sampler captures the clock with a rate of approximately 9.8Msps. With capturing 256 points of data per segment, nine sequential measurements are supposed to be done in a single execution. This is the case that 9 different pulse widths are programmed and all the 9 segments are cascaded in series. The waveform is created with components up to 5 th harmonics. Figure 15(a) shows 9-combined waveform that is supposed to be captured by a sampler. Each segment is constructed with 256 points. The graph (b) is provided for comprehension, showing each one of the segments reconstructed and overlaid. The width increment is T/16. The maximum shift T corresponds to T/2. The graph (c) is the test result, showing the pulse width increments calculated using FFT and phase analysis of the fundamental component as discussed in Equations (10), (11) and (12). It gives a very good result. Popular FFT and simple phase calculation can extract precise pulse width increments. Since valid segments can contain multiple cycles of clock pulses and also all the sampled points contribute the phase calculation, it is equivalent to averaging and affects precision and stability. 5. Discussions 5.1 Estimation of the Virtual Edge The FFT and phase analysis method proposed in the previous section needs only the fundamental component of the test signal. However, when the bandwidth of the signal path is not wide enough for the signal, a slew rate of the signal is degraded so that a rise time gets longer. If the slew rate is too slow, a falling action may start before the rising edge reaches its saturated high level of the signal as depicted in Figure 16. When the pulse width of Ideal Waveform is wide enough, deteriorated Actual Waveform (Pulse A) can reach the high level. When the ideal width gets narrower, the falling edge starts decreasing before hitting the ceiling, and then the pulse height is suppressed as Pulse B shows. Then the pulse width decrement T measured ( T(fake)) does not show the true value ( T(true)) that is an expected value. TIA or threshold-type time measurement cannot cope with the case of Figure 16. Even if the height of the pulse is low, the phase of the pulse B is the same as where it should be (dotted triangle). In this case, the FFT phase analysis method has a possibility to estimate the dotted triangle whose falling edge would show an expected location. Then the true T may be calculated. Thus, it may be possible to compensate for the bandwidth issue of the measurement path. 5.2 Alternative: Digital Capture & Potential Disadvantage As a measurement instrument, a waveform sampler is discussed in the proposed method. Under-sampling can be applied. The point is the phase analysis of the fundamental component of the test signal clock. Digital capture function is usually provided in mixed signal testers. It can capture the clock signal as a data stream of 1 s and 0 s. Even if it is 1/0 stream, it can be processed using FFT, showing frequency spectrum. So digital capture functionality also has a possibility to derive the phase and pulse width increment of the test signal with the method proposed. However, digital capture gives only two states of 1 s and 0 s. It has no precise resolution across the vertical direction. So in order to achieve fine resolution across the time direction, a huge number of samples should be acquired. (Over-sampling) Then data downloading and processing would take lots of time. Throughput is one of the most important factors in testing, so it should become 978

8 a bottleneck. Since the test signal clock synchronizes to the digital master clock in the tester, applying digital capture may have difficulties in flexibility of sampling conditions. Therefore, the digital capture sampling tends to fall in a metastable condition to the test signal clock so that over-sampling cannot work correctly as expected. 6. Conclusions This paper describes testing of write pre-compensation applied in a read channel device integrated in a HDD. Testing of this functionality is a very narrow- pulse clock signal measurement. TIA is not necessarily a good enough instrument because of its measurement mechanism. Instead of TIA, waveform samplers can capture the whole waveform, and the pulse width can be calculated directly by looking at the rising edge and the falling edge. In order to capture a nice looking waveform of the test signal, the signal path and the sampler needs analog bandwidth several times the clock frequency. Analyzing the phase rotation increment of the fundamental component corresponds to the pulse width increment by a ratio of 1:2. Therefore traditional FFT and phase analysis is good enough to test the write pre-compensation. When employing the FFT method, a wide analog bandwidth is not necessarily required. A limited bandwidth that at least the fundamental component goes through is good enough to calculate the pulse width modification. All the required measurements should be completed continuously with a single execution. Utilizing samplers instead of TIA would contribute to reducing cost of tests. 7. Acknowledgements The Author thank to my colleagues Fabio Pizza and Keita Gunji giving many pieces of advice and suggestions in read channel testing. And the Author especially thank to Fidel Muradali and Linda Miquelon giving valuable editorial suggestions. 8. References [1] Kanu G. Ashar Magnetic Disk Drive Technology, IEEE Press 1997, pp [2] Shin ichi Oh ishi Fourier Analysis, Iwanami- Shoten 1989, p.56 [3] Matthew Mahoney, DSP-BASED TESTING of Analog and Mixed-Signal Circuits, IEEE Computer Society Press, 1987, pp [4] Hideo Okawara Frequency/Phase Movement Analysis by Orthogonal Demodulation, Proceedings IEEE International Test Conference, 2002, pp [5] Charles L. Phillips, et al. Signals, Systems, And Transforms, Prentice Hall, 2003, p