DVB-S2X Modulator IP Core Specifcatoon
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1 DVB-S2X Modulator IP Core Specifcatoon
2 DVB-S2X Modulator IP Core Release Ionformatoon Features Deliverables IP Core Structure Port Map DVB-S2X Modulator IP Core Release Ionformatoon Name Version 2.0 DVB-S2X Modulator IP Core Build date Ordering code Specification revision ip-dvb-s2x-modulator r1383 Features Deliverables IP Core Structure The IP core is a digital DVB-S2/DVB-S2X modulator and is fully compatible with this standard: ETSI EN (v1.1.1) The DVB-S2X Modulator IP Core includes: EDIF/NGC/QXP/VQM netlist for Xilinx Vivado/ISE, Intel (Altera) Quartus, Lattice Diamond or Microsemi (Actel) Libero SoC IP Core testbench scripts Design examples for Xilinx, Intel (Altera), Lattice, and Microsemi (Actel) evaluation boards Figure 1 shows the DVB-S2X Modulator IP Core block diagram. TS Interface CRC-8 Encoder Slicer Base-Band Header Base-Band Scrambler BCH Encoder LDPC Encoder Bit Interleaver Bit Mapping PL Header Insertion Pilots Insertion PL Scrambler Pulse Shaping Filter Fractional Resampler Quadrature Modulator NCO DDS Figure 1. The DVB-S2X Modulator IP Core block diagram Port Map Figure 2 shows a graphic symbol, and Table 1 describes the ports of the DVB-S2X Modulator IP Core. 2
3 DVB-S2X Modulator IP Core iclk idat ifreq igain imodcod ipilot irdy iroll irst isample isize isop ival ivlsnr_mode odati odatq ordy Figure 2. The DVB-S2X Modulator port map 3
4 IP Core Parameters DVB-S2X Modulator IP Core Table 1. The DVB-S2X Modulator port map description Port Width Description iclk 1 The main system clock. The IP Core operates on the rising edge of iclk. idat 8 input (information) data ifreq 32 output intermediate frequency igain 16 output gain control imodcod 8 MODCOD value. See Annex A for values. ipilot 1 pilot mode: 0 - without pilot 1 - with pilot irdy 1 Modulator output data request. iroll 3 RRC filter roll-off factor: 0 - alpha= alpha= alpha= alpha= alpha= alpha=0.05 irst 1 The IP Core synchronously reset when irst is asserted high. isample 32 bandwidth control (symbol rate): 0.01% to 50% of iclk isize 1 LDPC frame size (only for DVB-S2): 0 - Normal FECFrame (Nldpc = bits) 1 - Short FECFrame (Nldpc = bits) isop 1 input sync-word byte marker (0x47 TS) ival 1 input data valid ivlsnr_mode 3 VL-SNR type. See Annex A for values. odati W_DAC modulator output at baseband (I channel) or at an intermediate frequency odatq W_DAC modulator output at baseband (Q channel) ordy 1 ready to accept input data IP Core Parameters Table 2 describes the DVB-S2X Modulator IP Core parameters, which must be set before synthesis. 4
5 DVB-S2X Modulator IP Core Table 2. The DVB-S2X Modulator IP Core parameters description Parameter W_DAC Description Width of output DAC symbols (odati/odatq) Increasing the width of odati/odatq, increases the quality of waveform but also increases FPGA required resource 5
6 IP Core Description Performaonce aond Resource Utliiatoon IP Core Ionterface Descriptoon IP Core Descriptoon Performaonce aond Resource Utliiatoon The values were obtained by automated characterization, using standard tool flow options and the floorplanning script delivered with the IP Core. The IP Core fully supports all Xilinx and Altera FPGA families, including Spartan, Zynq, Artix, Kintex, Virtex, Cyclone, Arria, MAX, Stratix. Table 3 summarizes the DVB-S2X Modulator IP Core measurement results. Table 3. The DVB-S2X Modulator performance IP Core parameters W_DAC=16 W_DAC=16 FPGA type Resource Altera Cyclone V 5CEFA ALMs (14%) 114 M10K RAM blocks (17%) 15 DSP (18x18) (10%) Xilinx Virtex-7 XC7VX330T 6126 Slices (12%) 58 18K RAM blocks (4%) 14 DSP (18x18) (2%) Speed grade, maximal system frequency -8, Fmax -7, Fmax -6, Fmax 96.0 MHz 48.0 Msymb/s MHz 55.5 Msymb/s MHz 66.0 Msymb/s -1, Fmax -2, Fmax -3, Fmax MHz 72.5 Msymb/s MHz 88.0 Msymb/s MHz 98.0 Msymb/s IP Core Ionterface Descriptoon IP core has two ways of forming the output spectrum: Baseband (using odati and odatq), ifreq equal 0 Intermediate frequency (using odati), ifreq not equal 0 Digital-to-analog converters must operate synchronously with the DVB-S2X Modulator IP core. Figure 3 shows the DAC connection diagram for baseband mode and Figure 4 shows the timing diagram for this mode. DVB-S2X odati DAC I Quad ifreq Modulator odatq DAC Q Mod =0 iclk FPGA PLL Ref Figure 3. The DAC connection diagram for baseband mode. 6
7 IP Core Descriptoon iclk ifreq 0 odati DACI0 DACI1 DACI2 DACI3 DACI4 odatq DACQ0 DACQ1 DACQ2 DACQ3 DACQ4 Figure 4. The timing diagram for baseband mode. Figure 5 shows the DAC connection diagram for IF mode and Figure 6 shows the timing diagram for this mode. The output intermediate frequency port ifreq sets the central frequency for odati modulator output port. DVB-S2X Modulator odati DAC ifreq 0 iclk FPGA PLL Ref Figure 5. The DAC connection diagram for IF mode. iclk ifreq frequency odati DAC0 DAC1 DAC2 DAC3 DAC4 Figure 6. The timing diagram for IF mode. Figure 7 shows an example of the waveform of the input interface. Handshake port ordy controls input dataflow. Input data is read from the input idat only when ordy is equal to logical one ("1"). 7
8 IP Core Descriptoon iclk ordy isop idat TS187 0x47 TS1 TS2 TS3 TS4 Figure 7. The timing diagram of the IP Core input interface. 8
9 Contacts Upgrade aond Techonical Support Feedback Revisioon history Coontacts Upgrade aond Techonical Support Free remote technical support is provided for 1 year and includes consultation via phone, and Skype. The maximum time for processing a request for technical support is 1 business day. For up-to-date information on the IP Core visit this web page Feedback IPrium LLC 39, via Umberto I, Ischitella (FG), 71010, Italy Tel.: +39(334) info@iprium.com Skype: fpgahelp website: Revisioon history Version Date Changes Added support for AD9361, AD9363, AD9364, AD9371, AD9375 and AD Official release 9
10 Annex A MODCOD setup Aononex A MODCOD setup Table A.1 shows the correct settings for imodcod, isize, ipilot, and ivlsnr_mode ports. 10
11 Aononex A Table A.1. The DVB-S2/DVB-S2X Modulator settings DVB-S2 Modes, ipilot controls Pilot Mode Off and On MODCOD Mode Code Type and Pilot imodcod = 1 imodcod = 2 QPSK 1/4 QPSK 1/3 isize: 0 - Normal FEC block (64800 bits) 1 - Short FEC block (16200 bits) imodcod = 3 QPSK 2/5 ipilot: 0 - Pilot Off imodcod = 4 QPSK 1/2 1 - Pilot On imodcod = 5 QPSK 3/5 imodcod = 6 QPSK 2/3 imodcod = 7 QPSK 3/4 imodcod = 8 QPSK 4/5 imodcod = 9 QPSK 5/6 imodcod = 10 QPSK 8/9 imodcod = 11 QPSK 9/10 imodcod = 12 8PSK 3/5 imodcod = 13 8PSK 2/3 imodcod = 14 8PSK 3/4 imodcod = 15 8PSK 5/6 imodcod = 16 8PSK 8/9 imodcod = 17 8PSK 9/10 imodcod = 18 16APSK 2/3 imodcod = 19 16APSK 3/4 imodcod = 20 16APSK 4/5 imodcod = 21 16APSK 5/6 imodcod = 22 16APSK 8/9 imodcod = 23 16APSK 9/10 imodcod = 24 32APSK 3/4 imodcod = 25 32APSK 4/5 11
12 Aononex A imodcod = 26 32APSK 5/6 imodcod = 27 32APSK 8/9 imodcod = 28 32APSK 9/10 DVB-S2X VL-SNR set1 Modes, ipilot does not work in this mode MODCOD Canonical MODCOD name Implementation MODCOD name Code Type imodcod = 129 ivlsnr_mode = 0 imodcod = 129 ivlsnr_mode = 1 imodcod = 129 ivlsnr_mode = 2 imodcod = 129 ivlsnr_mode = 3 imodcod = 129 ivlsnr_mode = 4 imodcod = 129 ivlsnr_mode = 5 QPSK 2/9 QPSK 2/9 Normal BPSK 1/5 p/2 BPSK 1/5 Medium BPSK 11/45 p/2 BPSK 11/45 Medium BPSK 1/3 p/2 BPSK 1/3 Medium BPSK-S 1/5 p/2 BPSK 1/5 SF 2 Short BPSK-S 11/45 p/2 BPSK 11/45 SF 2 Short DVB-S2X VL-SNR set2 Modes, ipilot does not work in this mode MODCOD Canonical MODCOD name Implementation MODCOD name Code Type imodcod = 131 ivlsnr_mode = 0 imodcod = 131 ivlsnr_mode = 1 imodcod = 131 ivlsnr_mode = 2 BPSK 1/5 p/2 BPSK 1/5 Short BPSK 4/15 p/2 BPSK 4/15 Short BPSK 1/3 p/2 BPSK 1/3 Short DVB-S2X Modes, ipilot controls Pilot Mode Off and On MODCOD Canonical MODCOD name Implementation MODCOD name Code Type imodcod = 132 QPSK 13/45 QPSK 13/45 Normal imodcod = 134 QPSK 9/20 QPSK 9/20 Normal imodcod = 136 QPSK 11/20 QPSK 11/20 Normal imodcod = 138 8APSK 5/9-L 2+4+2APSK 100/180 Normal 12
13 Aononex A imodcod = 140 8APSK 26/45-L 2+4+2APSK 104/180 Normal imodcod = 142 8PSK 23/36 8PSK 23/36 Normal imodcod = 144 8PSK 25/36 8PSK 25/36 Normal imodcod = 146 8PSK 13/18 8PSK 13/18 Normal imodcod = APSK 1/2-L 8+8APSK 90/180 Normal imodcod = APSK 8/15-L 8+8APSK 96/180 Normal imodcod = APSK 5/9-L 8+8APSK 100/180 Normal imodcod = APSK 26/ APSK 26/45 Normal imodcod = APSK 3/5 4+12APSK 3/5 Normal imodcod = APSK 3/5-L 8+8APSK 18/30 Normal imodcod = APSK 28/ APSK 28/45 Normal imodcod = APSK 23/ APSK 23/36 Normal imodcod = APSK 2/3-L 8+8APSK 20/30 Normal imodcod = APSK 25/ APSK 25/36 Normal imodcod = APSK 13/ APSK 13/18 Normal imodcod = APSK 7/9 4+12APSK 140/180 Normal imodcod = APSK 77/ APSK 154/180 Normal imodcod = APSK 2/3-L rbAPSK 2/3 Normal imodcod = APSK 32/ APSK 128/180 Normal imodcod = APSK 11/ APSK 132/180 Normal imodcod = APSK 7/ APSK 140/180 Normal imodcod = APSK 32/45-L APSK 128/180 Normal imodcod = APSK 11/ APSK 132/180 Normal imodcod = APSK 7/ APSK 7/9 Normal imodcod = APSK 4/ APSK 4/5 Normal imodcod = APSK 5/ APSK 5/6 Normal imodcod = APSK 3/4 128APSK 135/180 Normal imodcod = APSK 7/9 128APSK 140/180 Normal 13
14 Aononex A imodcod = APSK 29/45-L 256APSK 116/180 Normal imodcod = APSK 2/3-L 256APSK 20/30 Normal imodcod = APSK 31/45-L 256APSK 124/180 Normal imodcod = APSK 32/45 256APSK 128/180 Normal imodcod = APSK 11/15-L 256APSK 22/30 Normal imodcod = APSK 3/4 256APSK 135/180 Normal imodcod = 216 QPSK 11/45 QPSK 11/45 Short imodcod = 218 QPSK 4/15 QPSK 4/15 Short imodcod = 220 QPSK 14/45 QPSK 14/45 Short imodcod = 222 QPSK 7/15 QPSK 7/15 Short imodcod = 224 QPSK 8/15 QPSK 8/15 Short imodcod = 226 QPSK 32/45 QPSK 32/45 Short imodcod = 228 8PSK 7/15 8PSK 7/15 Short imodcod = 230 8PSK 8/15 8PSK 8/15 Short imodcod = 232 8PSK 26/45 8PSK 26/45 Short imodcod = 234 8PSK 32/45 8PSK 32/45 Short imodcod = APSK 7/ APSK 7/15 Short imodcod = APSK 8/ APSK 8/15 Short imodcod = APSK 26/ APSK 26/45 Short imodcod = APSK 3/5 4+12APSK 3/5 Short imodcod = APSK 32/ APSK 32/45 Short imodcod = APSK 2/ rbAPSK 2/3 Short imodcod = APSK 32/ rbAPSK 32/45 Short 14
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