PCE04I Inmarsat Turbo Encoder. Small World Communications. PCE04I Features. Introduction. Signal Descriptions

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1 P4I Inmarsat Turbo Encoder Product Specification P4I Features 16 state Inmarsat compatible turbo encoder Rate 1/2 to 1/5 ata lengths from 8 to 2,764 bits Up to 484 MHz internal clock Up to 242 Mbit/s encoding speed Parallel encoded data out 127 LUTs for Virtex 5, Virtex 6, Spartan 6 and 7 Series. Available as EIF core and VHL simulation core for ilinx Virtex II, Spartan, Virtex 4, Virtex 5, Virtex 6, Spartan 6 and 7 Series FPGAs under SignOnce IP License. Actel, Altera and Lattice FPGA cores available on request. Available as VHL core for ASICs Introduction The P4I is a 16 state Inmarsat [1,2] compatible turbo encoder. ata lengths from 8 to 2,764 bits can be implemented. Turbo code rates from 1/2 to 1/5 can be selected. The sequential data is terminated with a tail. The data and this tail are interleaved. The input data block size is K. The interleaver size is K+4. The number of coded bits is n(k+4) where the nominal code rate is 1/n. Figure 1 shows the schematic symbol for the P4I encoder. The EIF core can be used with ilinx Integrated Software Environment (ISE) software to implement the core in ilinx FPGA s. The VHL core can be used in ASIC designs. Table 1 shows the performance achieved for various ilinx parts. T cp is the minimum clock pe- I[14:] K[14:] N[1:] QS MOE RST IA[14:] A[14:] [4:] FINISH Figure 1: P4I schematic symbol. riod over recommended operating conditions. These performance figures may change due to device utilisation and configuration. Table 1: Example performance Part T cp (ns) Speed (Mbit/s) QS = QS = 1 C6SL C6SL C5VL C5VL C5VL C6VL75T C6VL75T C6VL75T C7A1T C7A1T C7A1T C7K7T C7K7T C7K7T C7Z C7Z C7Z Signal escriptions Clock Enable Encoder Clock FINISH Encoder Finish I Interleaver Address Input IA Interleaver Address ROM Address Interleaver Address ROM Ready K ata Length (8 to 2,764) MOE = small interleaver (A[14:1] = ) 1 = large interleaver N 2 = Rate 1/2 = Rate 1/ = Rate 1/4 1 = Rate 1/5 QS Second Parity Select = Second encoded output is, P and Q 1 = Second encoded output is Q RST Synchronous Reset 1

2 P4I Tail 1 Tail Registers P 1 P A A[1:] Q Input ata RAM Q 1 Q 2 4 External Circuitry Figure 2: P4I 16 state turbo encoder. Encoder Start ata In A ata In Address ata In Ready ata Out ata Out Read Encoder Figure 2 gives a block diagram of the P4I Inmarsat 16 state turbo encoder. is the data input and to 4 are the coded outputs. ata is clocked during the low to high transition of. Separate internal clock enables (1 and 2) are used to clock the data into each encoder. Non interleaved data is clocked into the first encoder and interleaved data is clocked into the second encoder. The vertical lines indicate multiplexers The data is first input in the sequence k where k is the data at time k from to K 1. The encoder then forms the tail bits k from k = K to K which are stored in the Tail Registers. Encoded data is also output, with k k, 1 k P 1 k P 2 k, regardless of the value of N[1:]. If QS =, the data is then input in the sequence k I(k ) from k = to K where I(k) is the interleaved address. Table 2 shows the output sequence for the various code rates. For rate 1/ and 1/5, k is incremented by one from to K. For rate 1/2 and 1/4, k is incremented by two. If QS = 1, the data is then input in the interleaved sequence I(k ) from k = to K. The encoded output is k I(k), 1 k Q 1 k Q 2 k, regardless of the value of N[1:]. Table 2: Output sequence (QS = ) Rate Sequence 1/2 k k 1 Q 1 k 1 1/ k 2 Q 1 k 1/4 k k 1 P 1 k 1 2 P 2 k Q 1 k 1 Q 2 k Q 2 k 1 1/5 k 2 P 2 k Q 1 k 4 Q 2 k Figure shows the initial timing diagram for encoding a block of data of length K = 122. The encoder starts and ends in state. When the encod- 2

3 P4I A QS = QS = Figure : P4I Initial Encoder Timing (K = 122). er requires data to be read from the input RAM, the data ready signal goes high (except for the first symbol) and A[14:] selects the data bit. After a signal is initiated goes high after one clock cycle. All signals are held if goes low. It is assumed that the data is stored in a synchronous read RAM with ( OR ) AN used to control the read enable input of the RAM. An asynchronous read RAM can also be used by registering the RAM output. For QS = 1, the encoded data ready signal goes high two clock cycles after a signal is initiated. is high for both the data block and tail. For QS =, stays low until the second encoded output. Figures 4 and 5 shows the second block encoding for QS = and 1, respectively. Symbol 1 k represents outputs with k k, 1 k P 1 k and 2 k P 2 k. Symbol 2 k represents outputs with k I(k), 1 k Q 1 k Q 2 k,. Symbol k represents the outputs given in Table 2. For QS =, the nominal encoder speed f e is f f e E (1) 15 K where f E = 1/T cp is the encoder clock speed. For QS = 1 the encoder speed is f e f E 2 8 K. (2) Ordering Information SW P4I SOS (SignOnce Site License) SW P4I SOP (SignOnce Project License) SW P4I VH (VHL ASIC License) All licenses include ilinx EIF and VHL simulation cores. The ilinx VHL simulation core can only be used for simulation in the SignOnce licenses. The SignOnce Project (SOP) license allows unlimited instantiations for a specified project. The Sign Once Site (SOS) license allows unlimited instantiations and projects for a specified development site. Note that Small World Communications only provides software and does not provide the actual devices themselves. Please contact Small World Communications for a quote. References [1] University of South Australia, Reduced bandwidth study of the High Speed ata Service Final Report, SCRC , Sep [2] u ouyun, Luo Hanwen, Song Wentao, Application of TC in the Inmarsat mobile satellite communication systems, Mobile Communication, 1999, rd.

4 P4I IA 1 2 I I() I(1) I(2) I(125) A 125 I() 1 I(1) 2 I(2) I(125) I() 1 I(1) I(125) FINISH Figure 4: P4I Second Encoder Timing (K = 122, QS =, = 1). Small World Communications does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under its copyrights or any rights of others. Small World Communications reserves the right to make changes, at any time, in order to improve performance, function or design and to supply the best product possible. Small World Communications will not assume responsibility for the use of any circuitry described herein. Small World Communications does not represent that devices shown or products described herein are free from patent infringement or from any other third party right. Small World Communications assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Small World Communications will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user. 214 Small World Communications. All Rights Reserved. ilinx, Spartan and Virtex are registered trademark of ilinx, Inc. All C prefix product designations are trademarks of ilinx, Inc. Supply of this IP core does not convey a license nor imply any right to use turbo code patents owned by France Telecom, GET or TF. Please contact France Telecom for information about turbo codes licensing program at the following address: France Telecom R& VAT/Turbocodes, 8 rue du Général Leclerc, Issy Moulineaux Cedex 9, France. Small World Communications, 6 First Avenue, Payneham South SA 57, Australia. info@sworld.com.au ph fax Version History. 28 September 214. Preliminary product specification..1 October 214. Corrected schematic symbol and encoder diagram November 214. Added LUT complexity and example performance values. Added FIN- ISH output to encoder symbol and timing diagrams. Corrected Table 2. 4

5 P4I IA I I() I(1) I(2) I() I(4) I(124) I(125) A I() I(1) I(2) I() I(12) I(124) I(125) 121 I() I(1) I(2) I(122) I(12) I(124) I(125) FINISH Figure 5: P4I Second Encoder Timing (K = 122, QS = 1, = 1). 5

VA04D 16 State DVB S2/DVB S2X Viterbi Decoder. Small World Communications. VA04D Features. Introduction. Signal Descriptions. Code

VA04D 16 State DVB S2/DVB S2X Viterbi Decoder. Small World Communications. VA04D Features. Introduction. Signal Descriptions. Code 16 State DVB S2/DVB S2X Viterbi Decoder Preliminary Product Specification Features 16 state (memory m = 4, constraint length 5) tail biting Viterbi decoder Rate 1/5 (inputs can be punctured for higher