SystemVue - DVB2 Baseband Verification Library. SystemVue DVB2 Baseband Verification Library

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2 SystemVue DVB2 Baseband Verification Library 1

3 Agilent Technologies, Inc Page Mill Road, Palo Alto, CA USA No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Agilent Technologies, Inc as governed by United States and international copyright laws Acknowledgments Mentor Graphics is a trademark of Mentor Graphics Corporation in the US and other countries Microsoft, Windows, MS Windows, Windows NT, and MS-DOS are US registered trademarks of Microsoft Corporation Pentium is a US registered trademark of Intel Corporation PostScript and Acrobat are trademarks of Adobe Systems Incorporated UNIX is a registered trademark of the Open Group Java is a US trademark of Sun Microsystems, Inc SystemC is a registered trademark of Open SystemC Initiative, Inc in the United States and other countries and is used with permission MATLAB is a US registered trademark of The Math Works, Inc HiSIM2 source code, and all copyrights, trade secrets or other intellectual property rights in and to the source code in its entirety, is owned by Hiroshima University and STARC Errata The SystemVue product may contain references to "HP" or "HPEESOF" such as in file names and directory names The business entity formerly known as "HP EEsof" is now part of Agilent Technologies and is known as "Agilent EEsof" To avoid broken functionality and to maintain backward compatibility for our customers, we did not change all the names and labels that contain "HP" or "HPEESOF" references Warranty The material contained in this document is provided "as is", and is subject to being changed, without notice, in future editions Further, to the maximum extent permitted by applicable law, Agilent disclaims all warranties, either express or implied, with regard to this manual and any information contained herein, including but not limited to the implied warranties of merchantability and fitness for a particular purpose Agilent shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein Should Agilent and the user have a separate written agreement with warranty terms covering the material in this document that conflict with these terms, the warranty terms in the separate agreement shall control Technology Licenses The hardware and/or software described in this document are furnished under a license and may be used or copied only in accordance with the terms of such license Portions of this product is derivative work based on the University of California Ptolemy Software System In no event shall the University of California be liable to any party for direct, indirect, special, incidental, or consequential damages arising out of the use of this software and its documentation, even if the University of California has been advised of the possibility of such damage The University of California specifically disclaims any warranties, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose The 2

4 software provided hereunder is on an "as is" basis and the University of California has no obligation to provide maintenance, support, updates, enhancements, or modifications Portions of this product include code developed at the University of Maryland, for these portions the following notice applies In no event shall the University of Maryland be liable to any party for direct, indirect, special, incidental, or consequential damages arising out of the use of this software and its documentation, even if the University of Maryland has been advised of the possibility of such damage The University of Maryland specifically disclaims any warranties, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose the software provided hereunder is on an "as is" basis, and the University of Maryland has no obligation to provide maintenance, support, updates, enhancements, or modifications Portions of this product include the SystemC software licensed under Open Source terms, which are available for download at This software is redistributed by Agilent The Contributors of the SystemC software provide this software "as is" and offer no warranty of any kind, express or implied, including without limitation warranties or conditions or title and non-infringement, and implied warranties or conditions merchantability and fitness for a particular purpose Contributors shall not be liable for any damages of any kind including without limitation direct, indirect, special, incidental and consequential damages, such as lost profits Any provisions that differ from this disclaimer are offered by Agilent only With respect to the portion of the Licensed Materials that describes the software and provides instructions concerning its operation and related matters, "use" includes the right to download and print such materials solely for the purpose described above Restricted Rights Legend If software is for use in the performance of a US Government prime contract or subcontract, Software is delivered and licensed as "Commercial computer software" as defined in DFAR (June 1995), or as a "commercial item" as defined in FAR 2101(a) or as "Restricted computer software" as defined in FAR (June 1987) or any equivalent agency regulation or contract clause Use, duplication or disclosure of Software is subject to Agilent Technologies standard commercial license terms, and non-dod Departments and Agencies of the US Government will receive no greater than Restricted Rights as defined in FAR (c)(1-2) (June 1987) US Government users will receive no greater than Limited Rights as defined in FAR (June 1987) or DFAR (b)(2) (November 1995), as applicable in any technical data 3

5 4 DVBS2_BCHEncoder Part 5 DVBS2 BCHEncoder 5 DVBS2_BitInterleaver Part 8 DVBS2 BitInterleaver 8 DVBS2_LDPCEncoder Part 11 DVBS2 LDPCEncoder 11 DVBS2_Mapper Part 16 DVBS2 Mapper 16 DVBS2_CRCEncoder Part 21 DVBS2 CRCEncoder 21 DVBS2_MergerSlicer Part 23 DVBS2 MergerSlicer 23 DVBS2_PLFramer Part 27 DVBS2 PLFramer 27 DVBS2_PLScrambler Part 31 DVBS2 PLScrambler 31 DVBS2_Demapper Part 34 DVBS2 Demapper 34 DVBS2_FrameSync Part 36 DVBS2 FrameSync 36 DVBS2_LDPCDecoder Part 38 DVBS2 LDPCDecoder 38 DVBS2_PLDemuxFrame Part 41 DVBS2_PLDemuxFrame 41 DVBS2_Receiver Part 43 DVBS2 Receiver 43 DVBS2_Source Part 45 DVBS2 Source 45 DVBT2_P1_Gen Part 48 DVBT2 P1 Gen 48 DVBT2_P2_Data_Gen Part 51 DVBT2 P2 Data Gen 51 DVBT2_Source Part 54 DVBT2 Source 54 DVBS2_BBScrambler Part 58 DVBS2 BBScrambler 58

6 DVBS2_BCHEncoder Part Categories: FEC Encoding (dvb2ver) The models associated with this part are listed below To view detailed information on a model (description, parameters, equations, notes, etc), please click the appropriate link Model Description DVBS2_BCHEncoder (dvb2ver) BCH encoder for DVB-S2 DVBS2 BCHEncoder Description: BCH encoder for DVB-S2 Domain: Untimed C++ Code Generation Support: NO Associated Parts: DVBS2 BCHEncoder Part (dvb2ver) Model Parameters Name Description Default Units Type Runtime Tunable FecFrame frame mode: Normal, Short Normal Enumeration NO CodeRate code rate for LDPC: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10 Input Ports Port Name Signal Type Optional 1 input int NO Output Ports Port Name Signal Type Optional 2 output int NO Notes/Equations 1/4 Enumeration NO 1 2 This model is to implement the outer channel coding: BCH encoder Each firing, N bch bits output tokens are generated and K bch bits input tokens consumed The FEC sub-system shall perform outer coding (BCH), Inner Coding (LDPC) and Bit interleaving The input stream shall be composed of BBFRAMEs and the output stream of FECFRAMEs Each BBFRAME (K bch bits) shall be processed by the FEC coding subsystem, to generate a FECFRAME (N ldpc bits) The parity check bits 5

7 (BCHFEC) of the systematic BCH outer code shall be appended after the BBFRAME, and the parity check bits (LDPCFEC) of the inner LDPC encoder shall be appended after the BCHFEC field, as shown in the figure below 3 The tables below give the FEC coding parameters for the normal FECFRAME (nldpc = bits) and the short FECFRAME (nldpc = bits) 4 In this model, A t-error correcting BCH (N bch, K bch ) code shall be applied to each BBFRAME (K bch ) to generate an error protected packet The BCH code parameters for nldpc = and for nldpc = are given in tables below The generator polynomial of the t error correcting BCH encoder is obtained by multiplying the first t polynomials in table 6a for nldpc = and in table 6b for nldpc =

8 5 BCH encoding of information bits m = (m Kbch-1, m Kbch-2,, m 1, m 0 ) onto a codeword: c = (m Kbch-1, m Kbch-2,, m 1, m 0, d Nbch-Kbch-1, d Nbch-Kbch-2,, d 1, d 0 ) is achieved as follows: Multiply the message polynomial m(x) = m Kbch-1 x Kbch-1 + m Kbch-2 x Kbch m 1 x + m 0 by x Nbch-Kbch Divide x Nbch-Kbch m(x) by g(x), the generator polynomial Let d(x) = d Nbch- Kbch-1 x Nbhc-Kbch d 1 x + d 0 be the remainder Set the codeword polynomial c(x) = x Nbch-Kbch m(x) + d(x) References 1 ETSI EN , "Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications" Version 112, Jun

9 DVBS2_BitInterleaver Part Categories: FEC Encoding (dvb2ver) The models associated with this part are listed below To view detailed information on a model (description, parameters, equations, notes, etc), please click the appropriate link Model Description DVBS2_BitInterleaver (dvb2ver) Bit interleaver for DVB-S2 DVBS2 BitInterleaver Description: Bit interleaver for DVB-S2 Domain: Untimed C++ Code Generation Support: NO Associated Parts: DVBS2 BitInterleaver Part (dvb2ver) Model Parameters Name Description Default Units Type Runtime Tunable FecFrame frame mode: Normal, Short Normal Enumeration NO ModType modulation type: QPSK, 8PSK, 16APSK, 32APSK QPSK Enumeration NO CodeRate code rate for LDPC: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10 8 1/4 Enumeration NO Direction Interleaver or Deinterleaver: Interlv, Deinterlv Interlv Enumeration NO Input Ports Port Name Signal Type Optional 1 input real NO Output Ports Port Name Signal Type Optional 2 output real NO Notes/Equations 1 This model is to implement the bit level interleaver or deinterleaver for 8PSK, 16APSK, and 32APSK modulation formats For QPSK, the interleaer is disabled and the output is directly connected with the input Each firing, N ldpc bits output tokens 2 are generated and N ldpc bits input tokens consumed For 8PSK, 16APSK, and 32APSK modulation formats, the output of the LDPC encoder

10 shall be bit interleaved using a block interleaver Data is serially written into the interleaver column-wise, and serially read out row-wise (the MSB of BBHEADER is read out first, except 8PSK rate 3/5 case where MSB of BBHEADER is read out third) as shown in figures below 3 The configuration of the block interleaver for each modulation format is specified in the table below 9

11 4 SystemVue - DVB2 Baseband Verification Library Both interleaver and deinterleaver functions are implemented in this model They are chosen by parameter Direction References 1 ETSI EN , "Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications" Version 112, Jun

12 DVBS2_LDPCEncoder Part Categories: FEC Encoding (dvb2ver) The models associated with this part are listed below To view detailed information on a model (description, parameters, equations, notes, etc), please click the appropriate link Model Description DVBS2_LDPCEncoder (dvb2ver) The LDPC Encoder for DVB- S2 DVBS2 LDPCEncoder Description: The LDPC Encoder for DVB-S2 Domain: Untimed C++ Code Generation Support: NO Associated Parts: DVBS2 LDPCEncoder Part (dvb2ver) Model Parameters Name Description Default Units Type Runtime Tunable FecFrame frame mode: Normal, Short Normal Enumeration NO CodeRate code rate for LDPC: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10 Input Ports Port Name Signal Type Optional 1 input int NO Output Ports Port Name Signal Type Optional 2 output int NO Notes/Equations 1/4 Enumeration NO 1 2 This model is to implement the inner channel coding: LDPC encoder Each firing, Nldpc bits output tokens are generated and K ldpc (=N bch ) bits input tokens consumed The FEC sub-system shall perform outer coding (BCH), Inner Coding (LDPC) and Bit interleaving The input stream shall be composed of BBFRAMEs and the output stream of FECFRAMEs Each BBFRAME (K bch bits) shall be processed by the FEC coding subsystem, to generate a FECFRAME (N 11 bits) The parity check bits

13 ldpc (BCHFEC) of the systematic BCH outer code shall be appended after the BBFRAME, and the parity check bits (LDPCFEC) of the inner LDPC encoder shall be appended after the BCHFEC field, as shown in the figure below 3 The tables below give the FEC coding parameters for the normal FECFRAME (nldpc = bits) and the short FECFRAME (nldpc = bits) 4 The task of the LDPC encoder is to determine N ldpc -K ldpc parity bits ( p 0, p 1,, p Nldpc-Kldpc-1 ) for every block of K ldpc information bits (i 0, i 1,, i Kldpc-1 ) The procedure is as follows: Initialize p 0 = p 1 = p 2 = = p Nldpc-Kldpc-1 = 0 Accumulate the first information bit, i 0, at parity bit addresses specified in the first row of tables B1 through B11 in annex B of Reference [1] For example, for rate 2/3 (table B6), (all additions are in GF(2)) 12

14 p 0 = p 0 + i 0 p 2767 = p i 0 p = p i 0 p 240 = p i 0 p = p i 0 p = p i 0 p 506 = p i 0 p 9279 = p i 0 p = p i 0 p = p i 0 p 8065 = p i 0 p = p i 0 p 8226 = p i 0 For the next 359 information bits, i m, m =1, 2,, 359 accumulate im at parity 13

15 bit addresses (x + (m mod 360) * q)mod(n ldpc -K ldpc ) where x denotes the address of the parity bit accumulator corresponding to the first bit i0, and q is a code rate dependent constant specified in table 7a/7b Continuing with the example, q = 60 for rate 2/3 So for example for information bit i1, the following operations are performed, p 60 = p 60 + i 1 p 2827 = p i 1 p = p i 1 p 300 = p i 1 p = p i 1 p = p i 1 p 566 = p i 1 p 9339 = p i 1 p = p i 1 p = p i 1 p 8125 = p i 1 p = p i 1 5 p 8286 = p i 1 For the 361st information bit i 360, the addresses of the parity bit accumulators are given in the second row of the tables B1 through B11 In a similar manner the addresses of the parity bit accumulators for the following 359 information bits i m, m = 361, 362,, 719 are obtained using the formula (x + (m mod 360) * q)mod(n ldpc -K ldpc ) where x denotes the address of the parity bit accumulator corresponding to the information bit i 360, ie the entries in the second row of the tables B1 through B11 In a similar manner, for every group of 360 new information bits, a new row from tables B1 through B11 are used to find the addresses of the parity bit accumulators After all of the information bits are exhausted, the final parity bits are obtained as follows: Sequentially perform the following operations starting with i = 1 p i = p i + p i-1, i = 1,2,,N ldpc -K ldpc -1 Final content of p i, i = 0,1,,N ldpc -K ldpc -1 is equal to the parity bit p i References 14

16 1 ETSI EN , "Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications" Version 112, Jun

17 DVBS2_Mapper Part Categories: Mapping (dvb2ver) The models associated with this part are listed below To view detailed information on a model (description, parameters, equations, notes, etc), please click the appropriate link Model Description DVBS2_Mapper (dvb2ver) The constellation mapper for DVB-S2 DVBS2 Mapper Description: The constellation mapper for DVB-S2 Domain: Untimed C++ Code Generation Support: NO Associated Parts: DVBS2 Mapper Part (dvb2ver) Model Parameters Name Description Default Units Type Runtime Tunable FecFrame frame mode: Normal, Short Normal Enumeration NO ModType modulation type: QPSK, 8PSK, 16APSK, 32APSK QPSK Enumeration NO CodeRate code rate for LDPC: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10 Input Ports Port Name Signal Type Optional 1 input int NO Output Ports Port Name Signal Type Optional 2 output complex NO Notes/Equations 1/4 Enumeration NO 1 2 This model is used to implement the constellation mapper Each FECFRAME (which is a sequence of bits for normal FECFRAME, or bits for short FECFRAME), shall be serial-to-parallel converted (parallelism level = η, 2 for QPSK, 3 for 8PSK, 4 for 16APSK, 5 for 32APSK), in figures 9 to 12, the MOD MSB of the FECFRAME is mapped into the MSB of the first parallel sequence Each parallel sequence shall be mapped into constellation, generating a (I,Q) sequence of variable length depending on the selected modulation efficiency η 16

18 3 4 SystemVue - DVB2 Baseband Verification Library The input sequence shall be a FECFRAME, the output sequence shall be a XFECFRAME (complex FECFRAME), composed of /η MOD (normal XFECFRAME) or /η MOD MOD (short XFECFRAME) modulation symbols Each modulation symbol shall be a complex vector in the format (I,Q) (I being the in-phase component and Q the quadrature component) For QPSK, the System shall employ conventional Gray-coded QPSK modulation with absolute mapping (no differential coding) Bit mapping into the QPSK constellation shall follow figure 9 The normalized average energy per symbol shall be equal to 1 Two FECFRAME bits are mapped to a QPSK symbol ie bits 2i and 2i+1 determines the ith QPSK symbol, where i = 0,1, 2,, (N/2)-1 and N is the coded LDPC block size 5 For 8PSK, the System shall employ conventional Gray-coded 8PSK modulation with absolute mapping (no differential coding) Bit mapping into the 8PSK constellation shall follow figure 10 The normalized average energy per symbol shall be equal to 1 Bits 3i, 3i+1, 3i+2 of the interleaver output determine the ith 8PSK symbol where i = 0, 1, 2, (N/3)-1 and N is the coded LDPC block size 17

19 6 The 16APSK modulation constellation (figure 11) shall be composed of two concentric rings of uniformly spaced 4 and 12 PSK points, respectively in the inner ring of radius R1 and outer ring of radius R2 The ratio of the outer circle radius to the inner circle radius (γ =R2/R1) shall comply with table 9 If 4R R2 2 = 16 the average signal energy becomes 1 Bits 4i, 4i+1, 4i+2 and 4i+3 of the interleaver output determine the ith 16APSK symbol, where i = 0, 1, 2,, (N/4)-1 and N is the coded LDPC block size 18

20 7 The 32APSK modulation constellation (see figure 12) shall be composed of three concentric rings of uniformly spaced 4, 12 and 16 PSK points, respectively in the inner ring of radius R1, the intermediate ring of radius R2 and the outer ring or radius R3 Table 10 defines the values of γ 1 = R2/R1 and γ 2 = R3/R1 If 4R R R3 2 = 32 the average signal energy becomes equal to 1 Bits 5i, 5i+1, 5i+2, 5i+3 and 5i+4 of the interleaver output determine the ith 32APSK symbol, where i = 0, 1, 2, (N/5)-1 19

21 References 1 ETSI EN , "Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications" Version 112, Jun

22 DVBS2_CRCEncoder Part Categories: Mode Adaptation (dvb2ver) The models associated with this part are listed below To view detailed information on a model (description, parameters, equations, notes, etc), please click the appropriate link Model Description DVBS2_CRCEncoder (dvb2ver) The CRC encoder for DVB-S2 DVBS2 CRCEncoder Description: The CRC encoder for DVB-S2 Domain: Untimed C++ Code Generation Support: NO Associated Parts: DVBS2 CRCEncoder Part (dvb2ver) Input Ports Port Name Signal Type Optional 1 input int NO Output Ports Port Name Signal Type Optional 2 output int NO Notes/Equations This model is used to implement CRC-8 encoder defined in clause 514 in Reference [1] for broadcasting Each firing, 188*8 bits output tokens are generated and the same number input tokens consumed UPL = 188*8 the input stream is a sequence of User Packets of length UPL bits, preceded by a sync-byte (the sync-byte being = 0D when the original stream did not contain a sync-byte) The useful part of the UP (excluding the sync-byte) shall be processed by a systematic 8-bit CRC encoder The generator polynomial shall be: g(x) = (X 5 +X 4 +X 3 +X 2 +1)(X 2 +X+1)(X+1) = X 8 +X 7 +X 6 +X 4 +X 2 +1 The CRC encoder output shall be computed as: CRC = remainder(x 8 u(x):g(x)) Where u(x) is the input sequence (UPL-8 bits) to be systematically encoded The figure below gives a possible implementation of the CRC generator by means of a shift register (Note: the register shall be initialized to all zeros before the first bit of each sequence enters the circuit) The computed CRC-8 shall replace the sync-byte of the following UP 21

23 As described in DVBS2 MergerSlicer (dvb2ver), the sync-byte is copied into the SYNC field of the BBHEADER for transmission References 1 ETSI EN , "Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications" Version 112, Jun

24 DVBS2_MergerSlicer Part Categories: Mode Adaptation (dvb2ver) The models associated with this part are listed below To view detailed information on a model (description, parameters, equations, notes, etc), please click the appropriate link Model Description DVBS2_MergerSlicer (dvb2ver) Segment the input signals in to DFLs and insert head for DVB- S2 DVBS2 MergerSlicer Description: Segment the input signals in to DFLs and insert head for DVB-S2 Domain: Untimed C++ Code Generation Support: NO Associated Parts: DVBS2 MergerSlicer Part (dvb2ver) Model Parameters Name Description Default Units Type Runtime Tunable FecFrame frame mode: Normal, Short Normal Enumeration NO CodeRate code rate for LDPC: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10 NumOfLdpcBlocks the number of LDPC blocks, to fullfill NumOfLdpcBlocks*DFL/(188*8) is an integer value rollofffactor Input Ports Port Name Signal Type Optional 1 input int NO Output Ports Port Name Signal Type Optional 2 output int NO Notes/Equations roll off factor for the root raised cosine filter: 035, 025, 020 1/4 Enumeration NO 188 Integer NO 035 Enumeration NO 1 This Merger/Slicer input stream is organised as Packetized Input Stream Each firing, NumOfLdpcBlocks*K bch bits output tokens are generated and NumOfLdpcBlocks*DFL 23

25 SystemVue - DVB2 Baseband Verification Library bits input tokens consumed According to the figure below, The UP length is UPL bits (where UPL = 0 is not supported) The input stream shall be buffered until the Merger/Slicer may read them The Slicer shall read (ie slice) from its input (support single input stream) a DATA FIELD, composed of DFL bits (Data Field Length), where: K bch -(10x8) DFL 0 (K bch is described in DVBS2 BCHEncoder (dvb2ver), 80 bits are dedicated to the BBHEADER In this DVB-S2 library, we only support DFL = K bch -80 The Merger shall concatenate, in a single output, different data fields read and sliced from its input In presence of a single stream, only the slicing functionality applies A DATA FIELD shall be composed of bits taken from a single input port and shall be transmitted in a homogeneous transmission mode (FEC code and modulation) In this Broadcast services applications, the Merger/Slicer shall allocate a number of input bits equal to the maximum DATAFIELD capacity (DFL = K bch -80), thus breaking UPs in subsequent DATAFIELDs In the same time, this model consumes NumOfLdpcBlocks*K bch bits each firing, selecting the NumOfLdpcBlocks to make the NumOfLdpcBlocks*K bch could be divided by UPL to porcess an integer number of UPs each firing After Sync-byte replacing by CRC-8 (see DVBS2 CRCEncoder (dvb2ver)), it is necessary to provide the receiver a method to recover UP synchronization (when the receiver is already synchronized to the DATA FIELD) Therefore the number of bits from the beginning of the DATA FIELD and the beginning of the first complete UP (first bit of the CRC-8) shall be detected by the Merger/Slicer and stored in SYNCD field (ie SYNC Distance) of the Base-Band Header For example, SYNCD = 0D means that the first USER PACKET is aligned to the DATA FIELD 8 A fixed length base-band Header (BBHEADER) of 10 bytes shall be inserted in front of the DATA FIELD, describing its format (the maximum efficiency loss introduced by the BBHEADER is 025 % for nldpc = and 1 % for nldpc = assuming inner code rate 1/2) 9 MATYPE (2 bytes): describes the input stream(s) format, the type of Mode Adaptation and the transmission Roll-off factor, as explained in the table below 10 First byte (MATYPE-1): 24

26 SystemVue - DVB2 Baseband Verification Library TS/GS field (2 bits): Transport Stream Input or Generic Stream Input (packetized or continuous) SIS/MIS field (1 bit): Single Input Stream or Multiple Input Stream CCM/ACM field (1 bit): Constant Coding and Modulation or Adaptive Coding and Modulation (VCM is signalled as ACM) ISSYI (1 bit), (Input Stream Synchronization Indicator): ISSYI = 0 = not-active in this library right now NPD (1 bit): Null-packet deletion active/not active RO (2 bits): Transmission Roll-off factor (α) In this library, the first 6 bits are constant value: , while the last 2 bits is decided by the roll-off factor Second byte (MATYPE-2): If SIS/MIS = Multiple Input Stream, then second byte = Input Stream Identifier (ISI); else second byte reserved In this library, the second byte is reserved to be UPL (2 bytes): User Packet Length in bits, in the range [0,65535] EXAMPLE 1: 0000HEX = continuous stream EXAMPLE 2: 000AHEX = UP length of 10 bits EXAMPLE 3: UPL = 188x8D for MPEG transport stream packets In this library, the 2 bytes UPL is 188x8D = B DFL (2 bytes): Data Field Length in bits, in the range [0,58112] EXAMPLE: 000AHEX = Data Field length of 10 bits In this library, the DFL = K bch -80 SYNC (1 byte): copy of the User Packet Sync-byte EXAMPLE 1: SYNC = 47HEX for MPEG transport stream packets EXAMPLE 2: SYNC = 00HEX when the input Generic packetized stream did not contain a sync-byte (therefore the receiver, after CRC-8 decoding, shall remove the CRC-8 field without reinserting the Sync-byte) In this library, the SYNC byte is 47HEX EXAMPLE 3: SYNC = not relevant for Generic continuous input streams SYNCD (2 bytes): distance in bits from the beginning of the DATA FIELD and the first UP from this frame (first bit of the CRC-8) SYNCD = 65535D means that no UP starts in the DATA FIELD CRC-8 (1 byte): error detection code applied to the first 9 bytes of the BBHEADER CRC-8 shall be computed using the encoding circuit of the figure in DVBS2 CRCEncoder (dvb2ver) (switch in A for 72 bits, in B for 8 bits) The BBHEADER transmission order is from the MSB of the TS/GS field Table below shows the BBHEADER and the slicing policy for a Single Transport Stream Broadcast Service which is implemented in this library 25

27 References 1 ETSI EN , "Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications" Version 112, Jun

28 DVBS2_PLFramer Part Categories: PL Framing (dvb2ver) The models associated with this part are listed below To view detailed information on a model (description, parameters, equations, notes, etc), please click the appropriate link Model Description DVBS2_PLFramer (dvb2ver) The physical layer framing for DVB- S2 DVBS2 PLFramer Description: The physical layer framing for DVB-S2 Domain: Untimed C++ Code Generation Support: NO Associated Parts: DVBS2 PLFramer Part (dvb2ver) Model Parameters Name Description Default Units Type Runtime Tunable FecFrame frame mode: Normal, Short Normal Enumeration NO ModType modulation type: QPSK, 8PSK, 16APSK, 32APSK QPSK Enumeration NO CodeRate code rate for LDPC: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10 1/4 Enumeration NO InsertPilot Insert Pilot Block or not: NO, YES YES Enumeration NO Input Ports Port Name Signal Type Optional 1 input complex NO Output Ports Port Name Signal Type Optional 2 output complex NO Notes/Equations 1 2 This model is used to implement the Physical Layer framer process, according to the figure below The PLFraming sub-system shall generate a physical layer frame (named PLFRAME) by performing the following processes: XFECFRAME slicing into an integer number S of constant length SLOTs (length: 27

29 M = 90 symbols each); S shall be according to the table below PLHEADER generation and insertion before the XFECFRAME for receiver configuration PLHEADER shall occupy exactly one SLOT (length: M = 90 Symbols) Pilot Block insertion (for modes requiring pilots) every 16 SLOTS, to help receiver synchronization The Pilot Block shall be composed of P = 36 pilot symbols The PLFRAMING efficiency is η = 90S/[90(S+1)+ P int{(s-1)/16}], where P = 36 and int{} is the integer function The PLHEADER is intended for receiver synchronization and physical layer signalling NOTE: after decoding the PLHEADER, the receiver knows the PLFRAME duration and structure, the modulation and coding scheme of the XFECFRAME, the presence or absence of pilot symbols The PLHEADER (one SLOT of 90 symbols) shall be composed of the following fields: SOF (26 symbols), identifying the Start of Frame PLS code (64 symbol): PLS (Physical Layer Signalling) code shall be a nonsystematic binary code of length 64 and dimension 7 with minimum distance dmin = 32 It is equivalent to the first order Reed-Muller under permutation It transmits 7 bits for physical layer signalling purpose These 7 bits consists of two fields: MODCOD and TYPE defined as follows: MODCOD (5 symbols), identifying the XFECFRAME modulation and FEC rate; TYPE (2 symbols), identifying the FECFRAME length ( bits or bits) and the presence/absence of pilots The PLHEADER, represented by the binary sequence (y 1, y 2,y 90 ) shall be modulated into 90PI/2BPSK symbols according to the rule: I 2i-1 = Q 2i-1 = (1/sqrt(2))(1-2y 2i-1 ), I 2i = -Q 2i = -(1/sqrt(2))(1-2y 2i ) for i = 1, 2,, 45 28

30 6 7 SystemVue - DVB2 Baseband Verification Library SOF shall correspond to the sequence 18D2E82HEX ( in binary notation, the left-side bit being the MSB of the PLHEADER) MODCOD shall correspond to 5 bits, identifying code rates in the set η C = [1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10] and modulations in the set of spectrum efficiencies η MOD = [2, 3, 4, 5] according to the table below 8 9 The MSB of the TYPE field shall identify 2 FECFRAME sizes (0 = normal: bits; 1 = short: bits) The LSB of the TYPE field shall identify the pilot configurations (see clause 553) (0 = no pilots, 1 = pilots) The MODCODE and TYPE fields are bi-orthogonally coded with a (64,7) code Such code is constructed starting from a bi-orthogonal (32,6) code according to the construction in the figure below 10 The particular construction guarantees that each odd bit in the (64,7) code is either always equal to the previous one or is always the opposite Which of the two hypotheses is true depends on the bit b7 This fact can be exploited in case differentially coherent detection is adopted in the receiver The MODCOD and the MSB of the TYPE field shall be encoded by a linear block code of length 32 with the following generator matrix 29

31 11 12 The most significant bit of the MODCOD is multiplied with the first row of the matrix, the following bit with the second row and so on The 32 coded bits is denoted as ( y 1,y 2,,y 32 ) When the least significant bit of the TYPE field is 0, the final PLS code will generate ( y 1,y 1,y 2,y 2,,y 32,y 32 ) as the output, ie each symbol shall be repeated When the least significant bit of the TYPE field is 1, the repeated symbol is further binary complemented The 64 bits output of the PLS code is further scrambled by the binary sequence: Two PLFRAME configurations shall be possible: Without pilots; With pilots In this latter case a PILOT BLOCK shall be composed of P = 36 pilot symbols Each pilot shall be an un-modulated symbol, identified by I = (1/sqrt(2)), Q = (1/sqrt(2)) The first PILOT BLOCK shall be inserted 16 SLOTs after the PLHEADER, the second after 32 SLOTs and so on If the PILOT BLOCK position coincides with the beginning of the next SOF, then the PILOT BLOCK is not transmitted References 1 ETSI EN , "Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications" Version 112, Jun

32 DVBS2_PLScrambler Part Categories: PL Framing (dvb2ver) The models associated with this part are listed below To view detailed information on a model (description, parameters, equations, notes, etc), please click the appropriate link Model Description DVBS2_PLScrambler (dvb2ver) The physical layer scrambling for DVB-S2 DVBS2 PLScrambler Description: The physical layer scrambling for DVB-S2 Domain: Untimed C++ Code Generation Support: NO Associated Parts: DVBS2 PLScrambler Part (dvb2ver) Model Parameters Name Description Default Units Type Runtime Tunable FecFrame frame mode: Normal, Short Normal Enumeration NO ModType modulation type: QPSK, 8PSK, 16APSK, 32APSK QPSK Enumeration NO InsertPilot Insert Pilot Block or not: NO, YES YES Enumeration NO Direction Input Ports Scramble or Descramble: Scramble, Descramble Port Name Signal Type Optional 1 input complex NO Output Ports Port Name Signal Type Optional 2 output complex NO Notes/Equations Scramble Enumeration NO 1 This model is used to implement the physical framer scrambler or descrambler 2 Prior to carrier modulation, each PLFRAME, excluding the PLHEADER, shall be randomized for energy dispersal by multiplying the (I+jQ) samples by a complex randomization sequence (C I + jc Q ): ISCRAMBLED = (I*C I - Q*C Q ); QSCRAMBLED = (I*C Q + Q*C I ) 3 NOTE: The randomization sequence rate corresponds to the I-Q PLFRAME symbol 31

33 4 SystemVue - DVB2 Baseband Verification Library rate, thus it has no impact on the occupied signal bandwidth The randomization sequence has a period greater than the maximum required duration of about symbols) The randomization sequence shall be reinitialized at the end of each PLHEADER (see the figure below) The PLFRAME duration depends on the modulation selected, thus the randomization sequence length shall be truncated to the current PLFRAME length 5 The scrambling code sequences shall be constructed by combining two real m- sequences (generated by means of two generator polynomials of degree 18) into a complex sequence The resulting sequences thus constitute segments of a set of Gold sequences 6 Let x and y be the two sequences respectively The x sequence is constructed using the primitive (over GF(2)) polynomial 1+x 7 + x 18 The y sequence is constructed using the polynomial 1+ y 5 + y 7 + y 10 + y 18 7 The sequence depending on the chosen scrambling code number n is denoted zn in the sequel Furthermore, let x(i), y(i) and z n (i) denote the i th symbol of the sequence x, y, and z n respectively The m-sequences x and y are constructed as: Initial conditions: x is constructed with x(0) = 1, x(1) = x(2) = = x(16) = x(17) = 0 y(0) = y(1) == y(16) = y(17) = 1 Recursive definition of subsequent symbols: x(i+18) = x(i+7) + x(i) modulo 2, i = 0,, y(i+18) = y(i+10) + y(i+7) + y(i+5) + y(i) modulo 2, i = 0,, The nth Gold code sequence zn n = 0,1,2,,2 18-2, is then defined as: z n (i) = [x((i+n) modulo (2 18-1)) + y(i) ] modulo 2, i = 0,, These binary sequences are converted to integer valued sequences R n (R n assuming values 0, 1, 2, 3) by the following transformation: R n (i) = 2*z n ((i ) modulo (2 18-1)) + z n (i) i = 0, 1,, Finally, the n th complex scrambling code sequence C I (i) + jc Q (i) is defined as: 32

34 11 The figure below gives a possible block diagram for PL scrambling sequences generation for n = In case of broadcasting services, n = 0 shall be used as default sequence, to avoid manual receiver setting or synchronization delays Both scrambler and descrambler functions are implemented in this model They are chosen by parameter Direction References 1 ETSI EN , "Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications" Version 112, Jun

35 DVBS2_Demapper Part Categories: Receiver (dvb2ver) The models associated with this part are listed below To view detailed information on a model (description, parameters, equations, notes, etc), please click the appropriate link Model Description DVBS2_Demapper (dvb2ver) The constellation demapper for DVB- S2 DVBS2 Demapper Description: The constellation demapper for DVB-S2 Domain: Untimed C++ Code Generation Support: NO Associated Parts: DVBS2 Demapper Part (dvb2ver) Model Parameters Name Description Default Units Type Runtime Tunable FecFrame frame mode: Normal, Short Normal Enumeration NO ModType modulation type: QPSK, 8PSK, 16APSK, 32APSK QPSK Enumeration NO CodeRate code rate for LDPC: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/ /4 Enumeration NO EsNo Es versus noise density 1 Float NO Input Ports Port Name Signal Type Optional 1 input complex NO Output Ports Port Name Signal Type Optional 2 output real NO Notes/Equations 1 This model implements the constellation demapper First it transforms received symbol values into log-likelihoods; then performs soft demapping (converts M-ary symbol likelihoods to bitwise LLRs) 2 The linear approximation to log-map is used

36 References 1 ETSI EN , "Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications" Version 112, Jun

37 DVBS2_FrameSync Part Categories: Receiver (dvb2ver) The models associated with this part are listed below To view detailed information on a model (description, parameters, equations, notes, etc), please click the appropriate link Model Description DVBS2_FrameSync (dvb2ver) The frame synchronization for DVB- S2 DVBS2 FrameSync Description: The frame synchronization for DVB-S2 Domain: Untimed C++ Code Generation Support: NO Associated Parts: DVBS2 FrameSync Part (dvb2ver) Model Parameters Name Description Default Units Type Runtime Tunable FecFrame frame mode: Normal, Short Normal Enumeration NO ModType modulation type: QPSK, 8PSK, 16APSK, 32APSK QPSK Enumeration NO CodeRate code rate for LDPC: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10 1/4 Enumeration NO InsertPilot Insert Pilot Block or not: NO, YES YES Enumeration NO SymbolRate Symbol rate 1e7 Integer NO Input Ports Port Name Signal Type Optional 1 input complex NO Output Ports Port Name Signal Type Optional 2 output complex NO 3 index int NO 4 DeltaF real NO Notes/Equations 1 A scheme to correlate on both the SOF and PLSCODE differentially is used for frame 36

38 2 3 SystemVue - DVB2 Baseband Verification Library synchronization The shift registers in the circuit can be partitioned into two sections The first is associated with SOF, the second with PLSCODE There are in total 57 taps associated with the 89 registers In the first part, 25 of them are associated with the pair-wise difference of SOF In the second part, 32 nonzero taps are associated with PLSCODE since only 32 out of the 64 differentials are known The taps associated with the shift register for computing the correlation can be obtained as follows First set all the registers to zero, then shift the modulated SOF and a modulated and scrambled codeword of PLSCODE into the circuit Once the rightmost register becomes nonzero, the tap associated with a register is just the complex conjugate of the content of the corresponding register Given that the modulated SOF and PLSCODE take only ±1, ±i, the taps only take these four possible values as well When used for frame synchronization, the incoming signal arriving at the correlator is sampled at one sample per symbol It is first differentially decoded and the resulting samples are then sequentially shifted into a shift register of length 89 The contents of the shift register are multiplied with the taps The first 25 and the last 32 values at the output of the multipliers are separately summed together in two different branches The outputs of the two summers are respectively added and subtracted to produce two values The maximum of the absolute value out of the two branches is the final output of this correlation circuit The output is then further processed by a peak search algorithm References 1 ETSI EN , "Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications" Version 112, Jun

39 DVBS2_LDPCDecoder Part Categories: Receiver (dvb2ver) The models associated with this part are listed below To view detailed information on a model (description, parameters, equations, notes, etc), please click the appropriate link Model Description DVBS2_LDPCDecoder (dvb2ver) The LDPC Decoder for DVB- S2 DVBS2 LDPCDecoder Description: The LDPC Decoder for DVB-S2 Domain: Untimed C++ Code Generation Support: NO Associated Parts: DVBS2 LDPCDecoder Part (dvb2ver) Model Parameters Name Description Default Units Type Runtime Tunable FecFrame frame mode: Normal, Short Normal Enumeration NO CodeRate code rate for LDPC: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10 DecodeAlgorithm decoding algorithm for LDPC: Sum Product, Normalized Min-Sum, Offset Min-Sum Input Ports Port Name Signal Type Optional 1 Input real NO 2 sigma real NO Output Ports Port Name Signal Type Optional 3 Output int NO Notes/Equations 1/4 Enumeration NO Sum Product Enumeration NO 1 2 This model is to implement the inner channel decoding: LDPC decoder Each firing, Nldpc bits input tokens are consumed and K ldpc (=N bch ) bits output are generated Sum Product decoding algorithm for LDPC codes is described here The parity check 38

40 matrix H can be viewed as a bipartite graph with two kinds of nodes: N variable nodes corresponding to the encoded variables, and M parity check nodes corresponding to the parity checks represented by the rows of the matrix H Each variable is connected to d s parity check nodes and each parity check node is connected to d v variable nodes, furthermore, for LDPC codes in DVB-S2, both d s and d v aren t constant The decoding of LDPC codes, Belief Propagation (BP) algorithm, is based on passing messages between variable nodes and parity check nodes along the edges through which they are connected in an iterative manner The messages represent estimates of the codeword bits based on the received signals and form the parity check constraints Two different computations have to be performed during a decoding iteration, namely the variable node update and parity check node update Assume that L mn represent the parity check to variable message along the i th edge connected to the n th parity check node during the q th iteration (we will not explicitly use the index n to denote quantities associated with the n th node as operations are identical at all nodes) Similarly, let Z mn represent the variable to parity check message along the i th edge connected to the n th variable node during the q th iteration Also denote the set of parity check nodes connected to variable nodes n as M n and the set of variable nodes connected to parity check node m as N(m) Then each iteration i of the Sum Product decoding includes the following steps: a) Initialization: after transmission through the channel, compute the posteriori probability of each variable node n as L n (0)=L c y n, where y n is received vector Assuming the AWGN channel with noise variance σ 2, the reliability value is L c =2/σ 2 The initialization is done in every position (m,n) of the parity check matrix H, where H m,n =1 b) Processing in parity check nodes c) Processing in variable nodes d) Posteriori probabilities The Min-Sum algorithm uses simplified processing in parity check nodes Normalized Min-Sum(NMS) decoding algorithm for LDPC codes: the parity check node processing could be improved by dividing with a constant smaller than 1 Offset Min-Sum (OMS) decoding algorithm for LDPC codes is another approach to improve the accuracy of the extrinsic messages passing by the Min-Sum algorithm It reduces the reliability values by a positive constant References 1 2 ETSI EN , "Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications" Version 112, Jun 2006 Hu, X-Y, Eleftheriou, E, Arnold, D-M, and Dholakia, A: EEfficient Implementations of the Sum-Product Algorithm for Decoding LDPC codes, IEEE Transactions on Communications, 2005, 53, (8) 39

41 3 4 SystemVue - DVB2 Baseband Verification Library M Fossorier, M Mihaljevic, H lmai, Reduced complexity iterative decoding of low density parity codes based on Belief Propagation, IEEE Transactions on Communications, vol 47, May 1989 Jinghu Chen and M Fossorier, Density Evolution for BP-Based Decoding Algorithm of LDPC Codes and Their Quantized Versions, IEEE Commun Lett, vol 6, No 5, May

42 DVBS2_PLDemuxFrame Part Categories: Receiver (dvb2ver) The models associated with this part are listed below To view detailed information on a model (description, parameters, equations, notes, etc), please click the appropriate link Model Description DVBS2_PLDemuxFrame (dvb2ver) The physical layer framing demux for DVB- S2 DVBS2_PLDemuxFrame Description: The physical layer framing demux for DVB-S2 Domain: Untimed C++ Code Generation Support: NO Associated Parts: DVBS2 PLDemuxFrame Part (dvb2ver) Model Parameters Name Description Default Units Type Runtime Tunable FecFrame frame mode: Normal, Short Normal Enumeration NO ModType modulation type: QPSK, 8PSK, 16APSK, 32APSK QPSK Enumeration NO CodeRate code rate for LDPC: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10 1/4 Enumeration NO InsertPilot Insert Pilot Block or not: NO, YES YES Enumeration NO Input Ports Port Name Signal Type Optional 1 input complex NO Output Ports Port Name Signal Type Optional 2 output complex NO Notes/Equations 1 This model is used to implement the Physical Layer frame demux process It's the reverse procedure of DVBS2_PLFramer It removes the PLHeader and pilots References 41

43 1 SystemVue - DVB2 Baseband Verification Library ETSI EN , "Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications" Version 112, Jun

44 DVBS2_Receiver Part DVBS2 baseband receiver Categories: Receiver (dvb2ver) The models associated with this part are listed below To view detailed information on a model (description, parameters, equations, notes, etc), please click the appropriate link Model DVBS2_Receiver (dvb2ver) DVBS2 Receiver Description: DVBS2 baseband receiver Associated Parts: DVBS2 Receiver Part (dvb2ver) Model Parameters Name Description Default Units Type Runtime Tunable FecFrame frame mode: Normal, Short Normal Enumeration NO ModType modulation type: QPSK, 8PSK, 16APSK, 32APSK CodeRate code rate for LDPC: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10 rollofffactorindex roll off factor index for the root raised cosine filter 16APSK Enumeration NO 8/9 Enumeration NO 0 Float NO InsertPilot Insert Pilot Block or not: NO, YES YES Enumeration NO SymbolRate complex symbol rate Hz Float NO OverSamplingRatio oversampling ratio 2 Float NO SNR signal to noise ratio 3 db Float NO Input Ports Port Name Description 1 input Terminal: Standard Data Port Terminal Output Ports Signal Type Optional complex NO 43

45 Port Name Description 2 output Terminal: Standard Data Port Terminal Notes/Equations SystemVue - DVB2 Baseband Verification Library Signal Type Optional int NO 1 2 This subnetwork completes DVB-S2 baseband receiver The DVBS2_Receiver schematic is shown below: 3 4 This subnetwork contains these features: Base-Band Filtering, Frame synchronization, Descrambler, De-framing, Demapper, Deinterleaver, LDPC Decoder and BCH Decoder It outputs decoded data to calculate BER and PER The referenced PER curve for different FecFrame, ModType and CodeRate are shown in References References 1 2 ETSI EN , "Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications" Version 112, Jun 2006 ETSI TR , "Digital Video Broadcasting (DVB) User guidelines for the second generation system for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications (DVB-S2)" Version 111, Feb

46 DVBS2_Source Part DVBS2 baseband signal source Categories: Source (dvb2ver) SystemVue - DVB2 Baseband Verification Library The models associated with this part are listed below To view detailed information on a model (description, parameters, equations, notes, etc), please click the appropriate link Model DVBS2_Source (dvb2ver) DVBS2 Source Description: DVBS2 baseband signal source Associated Parts: DVBS2 Source Part (dvb2ver) Model Parameters Name Description Default Units Type Runtime Tunable FecFrame frame mode: Normal, Short Normal Enumeration NO ModType modulation type: QPSK, 8PSK, 16APSK, 32APSK CodeRate code rate for LDPC: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10 NumOfLdpcBlocks rollofffactorindex the number of LDPC blocks, to fullfill NumOfLdpcBlocks*DFL/(188*8) is an integer value roll off factor index for the root raised cosine filter 45 16APSK Enumeration NO 8/9 Enumeration NO 188 Float NO 0 Float NO InsertPilot Insert Pilot Block or not: NO, YES YES Enumeration NO SymbolRate complex symbol rate Hz Float NO OverSamplingRatio oversampling ratio 2 Float NO Output Ports Port Name Description Signal Type Optional 1 output Terminal: Standard Data Port Terminal 2 beforebch Terminal: Standard Data Port Terminal Notes/Equations complex int NO NO

47 1 SystemVue - DVB2 Baseband Verification Library This subnetwork completes DVB-S2 baseband signal source A functional block diagram of DVB-S2 system is illustrated below: 2 The DVBS2_Source schematic is shown below: Forward Error Correction (FEC) Encoding shall be carried out by the concatenation of BCH outer codes and LDPC (Low Density Parity Check) inner codes (rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10) Depending on the application area, the FEC coded block shall have length n ldpc = bits or bits Bit interleaving shall be applied to FEC coded bits for 8PSK, 16APSK and 32APSK Mapping into QPSK, 8PSK, 16APSK and 32APSK constellations shall be applied, depending on the application area Gray mapping of constellations shall be used for QPSK and 8PSK Physical layer framing shall be applied, synchronous with the FEC frames, to provide Dummy PLFRAME insertion, Physical Layer (PL) Signalling, pilot symbols insertion (optional) and Physical Layer Scrambling for energy dispersal Dummy PLFRAMEs are transmitted when no useful data is ready to be sent on the channel The System provides a 46

48 6 SystemVue - DVB2 Baseband Verification Library regular physical layer framing structure, based on SLOTs of M = 90 modulated symbols, allowing reliable receiver synchronization on the FEC block structure A slot is devoted to physical layer signalling, including Start-of-Frame delimitation and transmission mode definition Carrier recovery in the receivers may be facilitated by the introduction of a regular raster of pilot symbols (P = 36 pilot symbols every 16 SLOTs of 90 symbols), while a pilot-less transmission mode is also available, offering an additional 2,4 % useful capacity Base-Band Filtering and Quadrature Modulation shall be applied, to shape the signal spectrum (squared-root raised cosine, roll-off factors 0,35 or 0,25 or 0,20) and to generate the RF signal References 1 ETSI EN , "Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications" Version 112, Jun

49 DVBT2_P1_Gen Part DVBT2 P1 baseband signal source Categories: Source (dvb2ver) The models associated with this part are listed below To view detailed information on a model (description, parameters, equations, notes, etc), please click the appropriate link Model DVBT2_P1_Gen (dvb2ver) DVBT2 P1 Gen Description: DVBT2 P1 baseband signal source Associated Parts: DVBT2 P1 Gen Part (dvb2ver) Model Parameters Name Description Default Units Type Runtime Tunable S1_Index index of S1 modulation pattern 1 Positive integer S2_Index index of S2 modulation pattern 1 Positive integer OversamplingRatio oversampling ratio: x1, x2, x4, x8 x2 Enumeration NO Output Ports NO NO Port Name Description 1 Output Terminal: Standard Data Port Terminal Notes/Equations Signal Type Optional complex NO 1 This subnetwork generates DVB-T2 P1 preamble symbol according to section 98 in [1] The P1 symbol structure is in the following figure 48

50 2 The scheme in the following figure shows how the P1 symbol is generated: 3 The DVBT2_P1_Gen schematic is shown below: 49

51 References SystemVue - DVB2 Baseband Verification Library 1 ETSI EN "Digital Video Broadcasting (DVB); Frame structure channel coding and modulation for a second generation digital terrestrial tellevision broadcasting system (DVB-T2)" Version 111, Oct

52 DVBT2_P2_Data_Gen Part DVBT2 P2 and Data baseband signal source Categories: Source (dvb2ver) The models associated with this part are listed below To view detailed information on a model (description, parameters, equations, notes, etc), please click the appropriate link Model DVBT2_P2_Data_Gen (dvb2ver) DVBT2 P2 Data Gen Description: DVBT2 P2 and Data baseband signal source Associated Parts: DVBT2 P2 Data Gen Part (dvb2ver) Model Parameters Name Description Default Units Type Runtime Tunable Mode DVB-T2 Mode: 1K mode, 2K mode, 4K mode, 8K mode, 16K mode, 32K mode GuardInterval DVB-T2 Guard Interval: 1/128, 1/32, 1/16, 19/256, 1/8, 19/128, 1/4 1K mode Enumeration NO 1/16 Enumeration NO CarrierMode DVB-T2 Carrier Mode: Normal, Extended Normal Enumeration NO PilotPattern DVB-T2 Pilot Pattern for Scatter Pilot: PP1, PP2, PP3, PP4, PP5, PP6, PP7, PP8 PP4 Enumeration NO OversamplingRatio oversampling ratio: x1, x2, x4, x8 x1 Enumeration NO PAPR_RC PAPR reduction by using reserved carriers?: NO, YES NumDataSym number of OFDM symbols of data in T2- frame NO Enumeration NO 10 Positive integer PAPR_Vclip clip threshold for reserved carrier PAPR 2 Float NO RunMode Input Ports 0: Run with calculating Index array in equation; 1: Generate binary Index files and Run with binary Index files reading: Use equation Index arrays, Use binary Index files Use equation Index arrays NO Enumeration NO 51

53 Port Name Description Signal Type Optional 1 MappingData Terminal: Standard Data Port Terminal Output Ports complex NO Port Name Description 2 Output Terminal: Standard Data Port Terminal Notes/Equations Signal Type Optional complex NO 1 2 This subnetwork generates DVB-T2 P2 symbols and data symbols according to section 8 (except section 83,84 and 85) and section 9 in [1] The DVB-T2 frame structure is shown in following figure At the top level, the frame structure consists of super-frames, which are divided into T2-frames and these are further divided into OFDM symbols The super-frame may in addition have FEF parts (see clause 84) In this subnetwork, only T2-frame is implemented 3 4 The T2-frame comprises one P1 preamble symbol, followed by one or more P2 preamble symbols, followed by a configurable number of data symbols In certain combinations of FFT size, guard interval and pilot pattern (see clause 927), the last data symbol shall be a frame closing symbol The details of the T2-frame structure are described in clause 832) The P1 symbols are unlike ordinary OFDM symbols and are inserted later (see clause 98) The P2 symbol(s) follow immediately after the P1 symbol The main purpose of the P2 symbol(s) is to carry L1 signalling data The L1 signalling data to be carried is described in clause 72, its modulation and error correction coding are described in clause 73 and the mapping of this data onto the P2 symbol(s) is described in clause 835 Various cells within the OFDM frame are modulated with reference information whose transmitted value is known to the receiver Cells containing reference information are transmitted at "boosted" power level The information transmitted in these cells are scattered, continual, edge, P2 or frame-closing pilot cells The locations and amplitudes of these pilots are defined in clauses 923 to 927 for SISO transmissions, and are modified according to clause 928 for MISO transmissions The value of the pilot information is derived from a reference sequence, which is a series of values, one for each transmitted carrier on any given symbol (see clause 922) PAPR reduction using reserved carriers is also implemented in P2 and Data OFDM symbols part Parameter PAPR_RC can control whether to use this PAPR reduction algorithm or not 52

54 5 SystemVue - DVB2 Baseband Verification Library The DVBT2_P2_Data_Gen schematic is shown below: References 1 ETSI EN "Digital Video Broadcasting (DVB); Frame structure channel coding and modulation for a second generation digital terrestrial tellevision broadcasting system (DVB-T2)" Version 111, Oct