1000BASE-RH PHY system simulations

Size: px

Start display at page:

Download "1000BASE-RH PHY system simulations"

Linda Cox
5 years ago
Views:

1 1000BASE-RH PHY system simulations Rubén Pérez-Aranda

2 Simulation scheme

3 1000BASE-RH PHY simulation scheme GMIII 64B/65B Encoding Binary Scrambler Coded PAM16 Symbol Scrambler THP Payload data path Power Scaling PLL 325 MHz PMA, OAM Header Builder CRC-16 Binary Scrambler BCH Encoder BPSK PAM2 Modulation Pilot S1 Generation Header data path Power Scaling Pilots data path Power Scaling Multiplexer DAC PMD TX VOA 9 bits BWRC = 1 GHz Channel 1000BASE-RH TX Pilot S2 Generation Power Scaling 1000BASE-RH RX FRAC-N PLL 325 MHz Freq control SYNCH TR DSP THP to PMA PMD RX AAFLT PGA BUFFER ADC S1, S2 Equalizer S2 Symbol Descr. PAM16 MSD Binary Descr. 64B/65B Decod. GMII Gain control AGC 3

4 1000BASE-RH transmit block Transmit Block j Time CW 0 CW 1 CW 2 CW 3 CW 4 CW 5 CW 6 CW 7 CW 8 CW 9 CW 10 CW 11 CW 12 CW 13 CW 14 CW 15 CW 16 CW 17 CW 18 CW 19 CW 20 CW 21 CW 22 CW 23 CW 24 CW 25 CW 26 CW 27 CW 26 CW 29 CW 30 CW 31 CW 32 S1 Data sub-block 0 PHS 0 S2 0 PHS 1 S2 1 Pilot S1 and S2 x sub-blocks Physical header Sub-Frame sub-blocks Transmit Block j+1 Data sub-block 27 CW 193 CW 194 CW 195 CW 196 CW 197 CW 198 CW 199 CW 200 CW 201 CW 202 CW 203 CW 204 CW 205 CW 206 CW 207 CW 208 CW 209 CW 210 CW 211 CW 212 CW 213 CW 214 CW 215 CW 216 CW 217 CW 218 CW 219 CW 220 CW 221 CW 222 CW 223 CW 0 PHS 12 S2 12 PHS 13 S1 PHS 12 S2 12 S1 Figure BASE-H Transmit Block 4

5 PAM16 encoder 494 2D symb/cw MSymb/s 1976 bits/cw From Binary Scrambler 3150 bits/cw MLCC demux level 1 level 2 FIFO1 BCH encoder / shortening (1976, 1668, t=28, GF(2 11 )) QAM8 (RZ 2 lattice) mapper Transf bits/cw mapper Λ t 1 (1) FIFO bits/cw QAM16 Gray 2 bits/dim Transf. Λ 1 t (2) Transf. Λ 2 t RZ 2 to PAM multiplexer 988 1D symbols /CW PAM MSps 1.5 bits/dim 5

6 PAM16 encoder Level 1, QAM16 Level 2, QAM

7 PAM16 encoder After Λ 2 t, 128-QAM Basic numbers of constellation: 128 points in a 2D constellation log2(128) = 7 bits / 2D symbol 7 bits = 4 bits of 1 st MLCC level 3 bits of 2 nd MLCC level Each 2D symbol are transmitted at a rate of MSymb/s To transmit over 1D (i.e. intensity modulation of LED), the system does time interleaving of both coordinates of 2D constellation at double rate, that is 325 MSymb/s Each 2D point can be represented by 2 coordinates that can take 16 different values each one: {-15, -13, 13, 15} therefore, 16-PAM This is PAM16, but encoded with 3.5 bits/ 1D symbol (i.e. 7bits/2D) instead of 4 bits bits of 3.5 are information bits, the rest is parity for error correction and detection 7

8 PAM16 multi-stage decoder 325 MSymb/s 988 1D symbols/cw Equalized noisy PAM16 symbols MSymb/s PAM to RZ 2 demux Λ 2 t 494 2D symbols/cw 1976 bits/cw Info bits 1668 bits/cw FIFO1 Decoding failure flag Λ 1 t (1) mod-λ1 [-4, 4) QAM16 detector QAM16 de-mapper BCH decoder FIFO1,2 - Λ 1 t (1) 16-QAM mapper 1976 bits/cw 2 bits/dim Decoded codeword MLCC multiplexer 3150 bits/cw Λ 1 t (2) mod-λ2 [-4, 4) QAM8 detector QAM8 de-mapper 1482 bits/cw Info bits FIFO2 1.5 bits/dim 8

9 Eye diagrams

10 Eye diagrams for S1, PHS DAC output TP2 - Driver+LED output (worst case response) 10

11 Eye diagrams for S1, PHS TP3-15m + VOA AOPTP3 = dbm PD-TIA output (worst case, Tj=125ºC) 11

12 Eye diagrams for S1, PHS TP3-50m + VOA AOPTP3 = -17 dbm PD-TIA output (worst case, Tj=125ºC) 12

13 Eye diagrams for DATA without THP DAC output TP2 - Driver+LED output (worst case response) 13

14 Eye diagrams for S2 DAC output TP2 - Driver+LED output (worst case response) 14

15 Eye diagrams for DATA with THP DAC output TP2 - Driver+LED output (worst case response) 15

16 Eye diagrams for Test mode 2 DAC output TP2 - Driver+LED output (worst case response) 16

17 Eye diagrams for Test mode 3 DAC output TP2 - Driver+LED output (worst case response) 17

18 1000BASE-RH receiver operation 15 m of at sensitivity

19 1000BASE-RH PHY receiver operation FRAC-N PLL 325 MHz Freq control SYNCH TR DSP THP to PMA PMD RX AAFLT PGA BUFFER ADC S1, S2 Equalizer S2 Symbol Descram PAM16 MSD Binary Descr. 64B/65B Decod. GMII Gain control AGC 19

20 1000BASE-RH PHY estimated channel 15m at sensitivity 0.45 Channel response Time Hc 0 Channel response Freq (db) Hc

21 1000BASE-RH PHY estimated THP 15m at sensitivity Equalizer Time FFF FBF FFF FBF THP Equalizer Freq (db)

22 1000BASE-RH PHY receiver operation FRAC-N PLL 325 MHz Freq control SYNCH TR DSP THP to PMA PMD RX AAFLT PGA BUFFER ADC S1, S2 Equalizer S2 Symbol Descram PAM16 MSD Binary Descr. 64B/65B Decod. GMII Gain control AGC 22

23 1000BASE-RH PHY equalized 1D symbols 15m at sensitivity 400 Equalized symbols 1D Histogram shows the constellation expansion produced by THP

24 PAM16 multi-stage decoder 325 MSymb/s 988 1D symbols/cw Equalized noisy PAM16 symbols MSymb/s PAM to RZ 2 demux Λ 2 t 494 2D symbols/cw 1976 bits/cw Info bits 1668 bits/cw FIFO1 Decoding failure flag Λ 1 t (1) mod-λ1 [-4, 4) QAM16 detector QAM16 de-mapper BCH decoder FIFO1,2 - Λ 1 t (1) 16-QAM mapper 1976 bits/cw 2 bits/dim Decoded codeword MLCC multiplexer 3150 bits/cw Λ 1 t (2) mod-λ2 [-4, 4) QAM8 detector QAM8 de-mapper 1482 bits/cw Info bits FIFO2 1.5 bits/dim 24

25 PAM16 multi-stage decoder - PAM to 2D demux 15m at sensitivity 25

26 PAM16 multi-stage decoder 325 MSymb/s 988 1D symbols/cw Equalized noisy PAM16 symbols MSymb/s PAM to RZ 2 demux Λ 2 t 494 2D symbols/cw 1976 bits/cw Info bits 1668 bits/cw FIFO1 Decoding failure flag Λ 1 t (1) mod-λ1 [-4, 4) QAM16 detector QAM16 de-mapper BCH decoder FIFO1,2 - Λ 1 t (1) 16-QAM mapper 1976 bits/cw 2 bits/dim Decoded codeword MLCC multiplexer 3150 bits/cw Λ 1 t (2) mod-λ2 [-4, 4) QAM8 detector QAM8 de-mapper 1482 bits/cw Info bits FIFO2 1.5 bits/dim 26

27 PAM16 multi-stage decoder - 1 st level input 15m at sensitivity 27

28 PAM16 multi-stage decoder 325 MSymb/s 988 1D symbols/cw Equalized noisy PAM16 symbols MSymb/s PAM to RZ 2 demux Λ 2 t 494 2D symbols/cw 1976 bits/cw Info bits 1668 bits/cw FIFO1 Decoding failure flag Λ 1 t (1) mod-λ1 [-4, 4) QAM16 detector QAM16 de-mapper BCH decoder FIFO1,2 - Λ 1 t (1) 16-QAM mapper 1976 bits/cw 2 bits/dim Decoded codeword MLCC multiplexer 3150 bits/cw Λ 1 t (2) mod-λ2 [-4, 4) QAM8 detector QAM8 de-mapper 1482 bits/cw Info bits FIFO2 1.5 bits/dim 28

29 PAM16 multi-stage decoder - 2 nd level input 15m at sensitivity 29

30 1000BASE-RH receiver operation 50 m of at sensitivity

31 1000BASE-RH PHY receiver operation FRAC-N PLL 325 MHz Freq control SYNCH TR DSP THP to PMA PMD RX AAFLT PGA BUFFER ADC S1, S2 Equalizer S2 Symbol Descram PAM16 MSD Binary Descr. 64B/65B Decod. GMII Gain control AGC 31

32 1000BASE-RH PHY estimated channel 50m at sensitivity 0.4 Channel response Time Hc 0 Channel response Freq (db) Hc

33 1000BASE-RH PHY estimated THP 50m at sensitivity Equalizer Time FFF FBF FFF FBF THP Equalizer Freq (db)

34 1000BASE-RH PHY receiver operation FRAC-N PLL 325 MHz Freq control SYNCH TR DSP THP to PMA PMD RX AAFLT PGA BUFFER ADC S1, S2 Equalizer S2 Symbol Descram PAM16 MSD Binary Descr. 64B/65B Decod. GMII Gain control AGC 34

35 1000BASE-RH PHY equalized 1D symbols 50m at sensitivity 450 Equalized symbols 1D Histogram shows the constellation expansion produced by THP

36 PAM16 multi-stage decoder 325 MSymb/s 988 1D symbols/cw Equalized noisy PAM16 symbols MSymb/s PAM to RZ 2 demux Λ 2 t 494 2D symbols/cw 1976 bits/cw Info bits 1668 bits/cw FIFO1 Decoding failure flag Λ 1 t (1) mod-λ1 [-4, 4) QAM16 detector QAM16 de-mapper BCH decoder FIFO1,2 - Λ 1 t (1) 16-QAM mapper 1976 bits/cw 2 bits/dim Decoded codeword MLCC multiplexer 3150 bits/cw Λ 1 t (2) mod-λ2 [-4, 4) QAM8 detector QAM8 de-mapper 1482 bits/cw Info bits FIFO2 1.5 bits/dim 36

37 PAM16 multi-stage decoder - PAM to 2D demux 50m at sensitivity 37

38 PAM16 multi-stage decoder 325 MSymb/s 988 1D symbols/cw Equalized noisy PAM16 symbols MSymb/s PAM to RZ 2 demux Λ 2 t 494 2D symbols/cw 1976 bits/cw Info bits 1668 bits/cw FIFO1 Decoding failure flag Λ 1 t (1) mod-λ1 [-4, 4) QAM16 detector QAM16 de-mapper BCH decoder FIFO1,2 - Λ 1 t (1) 16-QAM mapper 1976 bits/cw 2 bits/dim Decoded codeword MLCC multiplexer 3150 bits/cw Λ 1 t (2) mod-λ2 [-4, 4) QAM8 detector QAM8 de-mapper 1482 bits/cw Info bits FIFO2 1.5 bits/dim 38

39 PAM16 multi-stage decoder - 1 st level input 50m at sensitivity 39

40 PAM16 multi-stage decoder 325 MSymb/s 988 1D symbols/cw Equalized noisy PAM16 symbols MSymb/s PAM to RZ 2 demux Λ 2 t 494 2D symbols/cw 1976 bits/cw Info bits 1668 bits/cw FIFO1 Decoding failure flag Λ 1 t (1) mod-λ1 [-4, 4) QAM16 detector QAM16 de-mapper BCH decoder FIFO1,2 - Λ 1 t (1) 16-QAM mapper 1976 bits/cw 2 bits/dim Decoded codeword MLCC multiplexer 3150 bits/cw Λ 1 t (2) mod-λ2 [-4, 4) QAM8 detector QAM8 de-mapper 1482 bits/cw Info bits FIFO2 1.5 bits/dim 40

41 PAM16 multi-stage decoder - 2 nd level input 50m at sensitivity 41

42 Coded PAM16 performance reminder Material presented in January 2015

43 Coded PAM16 - Performance 3.5 bits/dim, 16 PAM, b/s/hz/dim, MLCC 1976, Error rate vs. SNR norm SER Input BER Input SER Uncoded BER Uncoded Shannon Bound Capacity Bound BER Input level 1 BER Output level 1 BER Input level 2 BER Output level 2 MLCC BER Error Rate BER = Coding-gain 6.35 db SNRnorm (db) 43

44 Coded PAM16 - Performance analysis -- BER analysis: -- Channel: THP Level 1: BCH(1976, 1668, 28) m = 11 Spect. Eff.: b/s/hz/dim Shannon gap (BER = 1e-12): 5.87 db Capacity bound gap (BER = 1e-12): 4.56 db SNR (BER = 1e-12): db Uncoded gap (BER = 1e-12): 12.2 db Coding gain (BER = 1e-12): 6.35 db Input SER (BER = 1e-12): Input BER (BER = 1e-12): Input BER MLC level 1 (BER = 1e-12): Input BER MLC level 2 (BER = 1e-12): e MTTFPA analysis: -- MLC level 1:! MTBE (BER = 1e-12): 09 h:31 m:44 s! MTTFPA with FCS detect (BER = 1e-12): 4.7e+06 y! MTTFPA with BCH detect (BER = 1e-12): 1.1e+27 y! MTTFPA with BCH & FCS detect (BER = 1e-12): 4.7e+36 y MLC level 2:! MTBE (BER = 1e-12): 3.3e+10 y! MTTFPA with FCS detect (BER = 1e-12): 1.4e+20 y MLC as a whole:! MTBE (BER = 1e-12): 09 h:31 m:44 s! MTTFPA -PHY & FCS- (BER = 1e-12): 1.4e+20 y! MTTFPA -just PHY- (BER = 1e-12): 3.3e+10 y -- PER analysis: --! Eth Frame Size = 64 bytes, PER = 1.1e-10 (BER = 1e-12)! Eth Frame Size = 256 bytes, PER = 1.6e-10 (BER = 1e-12)! Eth Frame Size = 512 bytes, PER = 1.9e-10 (BER = 1e-12)! Eth Frame Size = 1024 bytes, PER = 3.7e-10 (BER = 1e-12)! Eth Frame Size = 1522 bytes, PER = 5.4e-10 (BER = 1e-12) High coding gain. Basically, it is responsible of 6 dbo of link budget, considering that the TIA has to implement an AGC based on trans-impedance control High input BER to Level 1.This is good for an implementation of Link Monitor able to determine the link quality accurately and fast. Bit errors corrected by the BCH decoder per codeword may be a good estimate of the received signal quality. FCS does not suffice to provide MTTFPA > age of universe. Error detection capability of BCH is needed. Error detection capability will also avoid error propagation in Ethernet frames encapsulation due to bad frame delimiters detection. MAC FCS is not required for MTTFPA. BCH suffices to detect packet errors, and the MTBE of second level is > age of universe. The MTTFPA is determined by the second level, which is the minimum. Low PER. Because the error arrives in bursts from FEC decoder and BCH error detection capability is used. PER < BER*PktSz/10 44

45 Coded PAM16 - Performance analysis Errors burst length statistics for an erroneous code-word event (MC simulation): FEC errors burst length histogram mean , std Bit errors per FEC CW 45

46 Coded PAM16 - Performance analysis Errors burst length statistics for an erroneous code-word event (MC simulation): FEC errors burst length histogram Level 2: mean 11.44, std 3.94 Level 1: mean 25.94, std Bit errors per MLC level 46

47 Coded PAM16 - Performance analysis Link budget, MTBE and MTTFPA as a function of BER: BER BER BER BER BER MTBE 5m:45s 57m:28s 9h:32m 4 days 39 days MTTFPA -PHY + FCS- (years) MTTFPA -only PHY- (years) 6, , , , , , , , , , Age of universe years 47

48 Questions?

Study of Undetected Error Probability of BCH codes for MTTFPA analysis

Study of Undetected Error Probability of BCH codes for MTTFPA analysis Dunia Prieto Rubén Pérez-Aranda rubenpda@kdpof.com Background & Objectives A binary BCH code is proposed to be used as component code