Datasheet EV10AS150B. High Linearity ADC 10-bit 2.6 Gsps with 1:4 DMUX 5 GHz Full Power Bandwidth

Transcription

1 High Linearity ADC 0-bit 2.6 Gsps with : DMUX 5 GHz Full Power Bandwidth Datasheet Features ADC 0-bit Resolution Up to 2.6 Gsps Sampling Rate Selectable : or :2 Demultiplexed Digital LVDS Outputs True Single Core Architecture (No Calibration Required) External Interleaving Possible Via 3-Wire Serial Interface Gain Adjust Offset Adjust Sampling Delay Adjust Full Scale Analog Input Voltage Span 500 mvpp 00Ω Differential Analog Input and Clock Input Differential Digital Outputs, LVDS Logic Compatibility Low Latency Pipeline Delay Test Mode for Output Data Registering (BIST) Power Management (Nap, Sleep Mode) EBGA37 (Enhanced Ball Grid Array) Package Performance Single Tone Performance in st Nyquist ( dbfs) ENOB = 8.0 bit, SFDR = 57 dbfs at 2.6 Gsps, Fin = 95 MHz ENOB = 7.9 bit, SFDR = 57 dbfs at 2.6 Gsps, Fin = 295 MHz Single Tone Performance in 2 nd Nyquist ( 3 dbfs): ENOB = 7.9 bit, SFDR = 59 dbfs at 2.6 Gsps, Fin = 2595 MHz 5 GHz Full Power Input Bandwidth ( 3 db) ±0.5 db Band Flatness from 0 MHz to 2.0 GHz Input VSWR =.25: from DC to 3 GHz Bit Error Rate: 0 2 at 2.6 Gsps Screening Temperature Range Commercial C Grade: Tamb > 0 C; T J < 90 C Industrial V Grade: Tamb > 0 C; T J < 0 C Applications Direct Broadband RF Down Conversion Wide Band Communications Receiver High Speed Instrumentation High Speed Data Acquisition Systems Visit our website: for the latest version of the datasheet

2 . Block Diagram The EV0AS50B combines a 0-bit 2.6 Gsps fully bipolar analog-to-digital converter chip, driving a fully bipolar DMUX chip with selectable Demultiplexing ratio (:2) or (:). The 5 GHz full power input bandwidth of the ADC allows the direct digitization of up to GHz broadband signals in the high IF region, in either L_Band or S_Band. The : demultiplexed digital outputs are LVDS logic compatible, which allows easy interface with standard FPGAs or DSPs. The EV0AS50B operates at up to 2.6 Gsps in DMUX : and up to 2.0 Gsps in :2 DMUX ratio (The speed limitation with :2 DMUX ratio is mainly dictated by external data flow exchange capability at 2 Gsps with available FPGAs). The EV0AS50B ADC+DMUX combo device is packaged in a mm Enhanced Ball Grid Array EBGA37. This Package is based on multiple layers which allows the design of low impedance continuous ground and power supplies planes, and the design of 50Ω controlled impedance lines (00Ω differential impedance). This package has the same Thermal Coefficient of Expansion (TCE) as FR application boards, thus featuring excellent long term reliability when submitted to repeated thermal cycles. Figure -. Functional Block Diagram DRR (ADC Reset) CLK CLKN 3 WSI RESET 00Ω CLKDACTRL ASYNCRST (Dmux Reset) 3 WSI SLDN SDATA SCLK 3-wire Serial Interface (3WSI) Timing Circuitry & SDA Sampling delay Gain Offset 8-bit DAC 8-bit DAC 8-bit DAC Tunable Delay line Tunable Delay line 20 2 Port A AOR/AORN DRA/DRAN VIN VINN 00Ω T/H 0 bit Quantifier Regeneration Logic & decod Demultiplexer :2 or : LVDS Buffers Port B BOR/BORN DRB/DRBN Port C COR/CORN DRC/DRCN Port D DOR/DORN DRD/DRDN 2 DR/DRN BIST (Pattern Generator) SLEEP (DMUX) STAGG (Latency) RS (Ratio Sel) DRTYPE (Dual Data Rate) 2

3 2. Specifications This section describes the device specifications in terms of: Absolute max ratings Recommended conditions of use Electrical operating characteristics Timings 2. Absolute Maximum Ratings Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are within specified operating conditions. Long exposure to maximum rating may affect device reliability. Maximum ratings on I/Os are defined with device powered ON. All integrated circuits have to be handled with appropriate care to avoid damages due to ESD. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure. Table 2-. Absolute Maximum Ratings Parameter Symbol Value Unit Analog.9V Power Supply voltage V CCA5 GND to 6.0 V Analog 3.25V Power Supply voltage V CCA3 GND to 3.6 V Digital 3.3V Power Supply Voltage V CCD GND to 3.6 V Output 2.5V Power Supply voltage V PLUSD GND to 3.0 V Minimum Analog input peak voltage () (with differential input) Maximum Analog input peak voltage () (with differential input) V IN or V INN 2.0 V V IN or V INN.0 V Maximum difference between V IN and V INN () (with differential input) V IN V INN 2.0 ( Vpp = +3 dbm in 00Ω) V Minimum Analog input peak voltage (2) (with single ended input) Maximum Analog input peak voltage (2) (with single ended input) V IN with V INN = 50Ω to GND or V INN with V IN = 50Ω to GND V IN with V INN = 50Ω to GND or V INN with V IN = 50Ω to GND 2.0 V.0 V (2) Maximum amplitude on V IN or V INN (with single ended input) Minimum Clock input peak voltage (with differential clock) Maximum Clock input peak voltage (with differential clock) V IN or V INN (2 Vpp = +0 dbm in 50Ω) V V CLK or V CLKN.5 V V CLK or V CLKN.0 V Maximum difference between V CLK and V CLKN (with differential clock) V CLK V CLKN.5 (3 Vpp) V 3WSI input voltage SDATA, SLDN, SCLK, RESET 0.3 to V CCA V 3

4 Table 2-. Absolute Maximum Ratings (Continued) Parameter Symbol Value Unit ADC Reset Voltage DRR 0.3 to V CCA V DMUX function input voltage RS, DRTYPE, SLEEP, STAGG, BIST 0.3 to V CCD V DMUX Asynchronous Reset ASYNCRST 0.3 to V CCD V DMUX Control Voltage CLKDACTRL 0.3 to V CCD V Maximum input voltage on DIODE DIODE ADC 700 mv Maximum input current on DIODE DIODE ADC ma Max Junction Temperature T J 35 C Storage temperature Tstg 55 to 50 C ESD protection (HBM) Notes:. See Section See Section on ADC inputs 500 on DMUX outputs V 2.. Analog Input Max Ratings in differential configuration Internal DC Common mode bias for differential analog inputs is: +3V (90.9% of V CCA3 ). Input impedance on V IN and V INN is: 55Ω // 550Ω = 50Ω. Max rating is ±V = 2 Vpp on each single ended input, corresponding to Vpp in differential. Vinput max = 3V + V = V Vinput min = 3V V = 2V With V IN = +V and V INN = +2V => V IN V INN = +2V With V INN = +V and V IN = +2V => V IN V INN = 2V Figure 2-. Analog Input Max Ratings in Differential Configuration EV0AS50B Differential analog input signals: Max rating differential inputs = ± 2 Vpeak = Vpeak to peak Maximum voltage on VIN or on VINN : + Volt: => ESD protections connected between VIN and VINN to +3.25V V CCA3 = +3.25V +0.7V max + 0 ma max V CCA5 = +.9V +3V DC common mode V CCA3 = +3.25V +0.7V max + 0 ma max V max 2V min +Vpeak VIN -Vpeak VINN DC blocking VIN DC blocking VINN 50Ω Line 50Ω Line ESD ESD 55Ω 550Ω ± 2Vpeak max diff 55Ω 550Ω ESD ESD VINN Max (VIN - VINN) = Volt peak-peak GND

5 2..2 Analog Input Max Ratings in Single Ended Configuration Internal DC common mode bias for differential analog inputs is +3V (90.9% of V CCA3 ). Input impedance on V IN (and V INN ) is: 55Ω // 550Ω = 50Ω Max rating is ±V on one single ended signal, corresponding to 2 Vpp on 50Ω Limiting parameter for maximum rating is not V IN V INN differential input voltage but V IN peak voltage value which shall not exceed +V to avoid turning on the ESD protection tied to V CCA3 = +3.25V. Vinput max = 3V (CM) + V (ESD) = V (If + Vp is applied, the ESD protections becomes forward biased: (+V 3.25V = +0.75V). Vinput min = 3V V = 2V The ESD diode can sustain up to 0 ma forward biasing without damage, but incoming signal will be clipped at +V = +3V (internal DC common mode) + V. Figure 2-2. Analog Input Max Ratings in Single Ended Configuration Single-ended analog input signal: Max rating differential inputs = ±Vpeak = 2 Vpeak to peak Maximum voltage on VIN: + Volt Minimum voltage on VIN: +2 Volt => ESD protections connected between VIN and VINN to +3.25V: +0.7 Volt max, + 0 ma max V max Vp VIN VIN DC blocking 50Ω Line V CCA3 = +3.25V ESD +0.7V max + 0 ma max 55Ω EV0AS50B V CCA5 = +.9V +3V DC common mode ± 2Vpeak max diff V CCA3 = +3.25V 55Ω +0.7V max + 0 ma max ESD VINN 2V min -Vp DC blocking VINN 50Ω Line ESD 550Ω 550Ω ESD 50Ω GND GND = 0V 5

6 2.2 Recommended Conditions of Use Table 2-2. Recommended Conditions of Use Parameter Symbol Comments Recommended Unit Power supplies Analog 3.25V Power Supply voltage V CCA3 No specific power supply 3.25 V Analog.9V Power Supply voltage V CCA5.75V to.9v V Digital 3.3V Power Supply voltage V CCD sequencing required during power ON / OFF 3.3 V Output 2.5V Power Supply voltage V PLUSD 2.5 V Analog Input Recommended Configuration Differential Analog input Clock Input Recommended Configuration Clock input power level P CLK P CLKN 00Ω differential clock Differential Clock input + dbm / 50Ω (Vpp in 00Ω) dbm External clock Duty cycle DCYC 50 % Control functions input level ADC 3WSI Inputs SDATA, SLDN, SCLK, RESET 0 to V CCA3 V ADC Reset DRR 0 to V CCA3 V DMUX Control Inputs SLEEP, STAGG, ASYNCRST, BIST, RS, DRTYPE, CLKDACTRL 0 to V CCD V Operating Temperature T J Best performances at highest temperatures Table 2-3. Recommended Configuration for Optimum Dynamic Performances 3WSI Register Recommended value comment State register SDA OFF For optimum SNR in 2 nd Nyquist zone if not used in interleaving mode Clock duty Cycle adjust register D.D0 35/65% For optimum SFDR and THD Clock adjust register D D0 +30 ps For optimum SFDR and THD Gain adjust D7...D0 Minimum gain For optimum SNR and SFDR SNR can be increased by around db if V CCA5 is decreased from.9v to.75v. SFDR in the 2 nd Nyquist is optimum near V CCA =.9V. Decreasing V CCA at.75v will degrade SFDR in the 2 nd Nyquist by around db. 6

7 2.3 Electrical Characteristics for Supplies, Inputs and Outputs Unless otherwise specified: Values are given over temperature and power supplies range. Table 2-. Electrical Characteristics for Supplies, Inputs and Outputs Parameter Test Level Symbol Min Typ Max Unit Power requirements Power Supply voltages Analog.9V Analog 3.25V Digital 3.3V Output 2.5V V CCA5 V CCA3 V CCD V PLUSD V V V V Power Supply current in :2 DMUX Analog V CCA5 =.9V Analog V CCA3 = 3.25V Digital V CCD = 3.3V Output V PLUSD = 2.5V I VCCA5 I I VCCD I ma ma ma ma Power Supply current in : DMUX Analog V CCA5 =.9V Analog V CCA3 = 3.25V Digital V CCD = 3.3V Output V PLUSD = 2.5V I VCCA5 I I VCCD I ma ma ma ma Power Supply current in NAP and SLEEP mode Analog V CCA5 =.9V Analog V CCA3 = 3.25V Digital V CCD = 3.3V Output V PLUSD = 2.5V I VCCA5 I I VCCD I ma ma ma ma Power dissipation - :2 DMUX - : DMUX - NAP & SLEEP mode (: or :2) 5.8 P D W W W Analog inputs Common mode compatibility for analog inputs () AC or DC (AC recommended) Analog inputs common voltage (internal) V CM 3.0 V Full-Scale input Voltage Range Differential mode V IN 25 V INN mv Full-Scale input Voltage Range Single ended mode with other input connected to ground through 50Ω resistors V IN or V INN mv Analog Input power Level (in 00Ω differential termination) P IN, INN dbm Vpp Analog Input power Level (in 50Ω single ended termination) P IN or P INN 2 dbm Analog input capacitance (die) C IN 0.3 pf Input leakage current I IN 0 µa 7

8 Table 2-. Electrical Characteristics for Supplies, Inputs and Outputs (Continued) Parameter Test Level Symbol Min Typ Max Unit Input resistance - Single-ended - Differential R IN R IN, INN Ω Ω Clock inputs Logic common mode compatibility for clock inputs Low phase noise sinewave at 2.6 GHz (> 55 dbc/hz) or low jitter LVDS/LVPECL (<00 fs rms) ADC intrinsic clock jitter (2) 20 fs rms 3.0 Clock inputs internal DC common mode voltage V CM 90.9% V % of V CCA3 Clock input voltage on each single ended input (2.6 GHz sinewave) Clock input voltage into 00Ω differential clock input (2.6 GHz sinewave) Clock input power level (2.6 GHz low phase noise sinewave input) in 50Ω Sinewave or Square wave Clock signal (minimum) slew-rate V CLK or V CLKN ±0.58 ±0.25 ±0.5 V V CLK V CLKN Vpp P CLK, CLKN dbm SR CLK, CLKN 5 8 GV/s Square Wave differential Clock input voltage on 00Ω input (LVDS & LVPECL compatible) VSQ CLK-CLKN Vpp Clock input capacitance (die) C CLK 0.3 pf Clock input Resistance - Single-ended - Differential R CLK R CLK, CLKN Ω Ω Digital Data Outputs Logic compatibility LVDS 50Ω transmission lines, 00Ω (2 50Ω) differential termination - Logic low - Logic high - Differential output - Common mode VOL VOH VODIFF VOCM V V mv V Control Function Inputs ASYNCRST (DEMUX Reset) input voltages and currents - Logic Low V IL I IL V µa - Logic High (reset mode) V IH.8 V CCD I IH 50 DRR (ADC reset) (3) Logic low Logic high Threshold V IL V IH V TH V CCA3 V µa V V V 8

9 Table 2-. Electrical Characteristics for Supplies, Inputs and Outputs (Continued) Parameter Test Level Symbol Min Typ Max Unit RS, BIST, STAGG, SLEEP, DRTYPE (Control Input Voltages) - Logic low () Resistor to ground Voltage level Input low current - Logic high () Resistor to ground Voltage level Input high current R IL V IL I IL R IH V IH I IH k Infinite 0 Ω V µa Ω V µa SDATA, SLDN, SCLK, RESET Logic low Logic high V IL V IH V CCA3 V V CLKDACTRL input voltage /3 V CCD 2/3 V CCD V Notes:. The DC analog common mode voltage is provided by ADC. 2. Measured with SDA OFF(ADC Jitter = 20 fs rms). ADC Jitter with SDA = ON is 50 fs rms, and 70 fs rms with SDA = ON and fully tuned. 3. DRR logic programmable with 3WSI interface. Default value is DRR active low.. See Section. on page 3 for control signal settings. 2. Converter Characteristics Unless otherwise specified: Recommended conditions of use (refer to Table 2-2 and Table 2-3 on page 6). Values are specified for Tj 65 C and over specified power supplies range. Typical values are given at ambient (Tj ~65 C) with typical power supplies. These conditions apply for all tables from Table 2-5 to Table 2-7. Table 2-5. DC Converter Characteristics Parameter Test Level Symbol Min Typ Max Unit DC Accuracy Resolution N 0 bit DNLrms () DNLrms 0.22 LSB Differential non-linearity () DNL LSB Differential non-linearity ()) DNL LSB Integral non-linearity () INL- 3.0 LSB Integral non-linearity () INL+ 2.3 LSB Gain center value (2) G Gain error drift G(T) 50 ppm/ C Input offset voltage (3) OFFSET mv Notes:. Histogram testing at Fs = 2.6 Gsps Fin = 00 MHz satured. DNLrms is the deviation from ideal ADC rms quantification noise. For reference, a DNL of 0.22 LSB rms has the same order of magnitude as the 0 Bit rms quantification noise : LSB/ SQRT(2) = LSB / 3.6 = LSB rms. 9

10 2. ADC gain with programmed default value. This ADC Gain can be fine tuned to by monitoring of the gain adjust function through the 3WSI serial interface. 3. ADC offset with programmed default values. The ADC Offset can be compensated through the 3WSI up to ± 20 mv by an 8 Bit embedded control DAC: Resolution: 0 mv/256 = 56 µv (See 3WSI table in Section.5.3 3WSI Register Description on page 5). Table 2-6. Parameter Dynamic Converter Characteristics Test Level Symbol Min Typ Max Unit AC Characteristics Full Power Input Bandwidth ( 3 db) FPBW 5 GHz Gain Flatness (0 MHz-.7 GHz) Systematic roll-off AC gain variation Gain Flatness (.7 GHz-2.9 GHz) Systematic roll-off AC gain variation Gain Flatness (2.9 GHz-. GHz) Systematic roll-off AC gain variation GF 0.5 ± ±0.2.0 ±0.3 db Input Voltage Standing Wave Ratio (DC 3 GHz) (3 GHz 5 GHz) VSWR.25:.50: Table 2-7. Parameter Dynamic Converter Characteristics Test Level Symbol Min Typ Max Unit AC Performance with differential analog input Ain = dbfs, + dbm differential clock ( Vpp in 00Ω), 50% external duty cycle, binary output mode Signal to Noise and Distortion Ratio Fs = 2.6 Gsps Fin = 95 MHz Fs = 2.6 Gsps Fin = 295 MHz Fs = 2.6 Gsps Fin = 595 MHz Fs = 2.6 Gsps Fin = 2295 MHz Fs = 2.6 Gsps Fin = 2595 MHz SINAD dbfs Effective Number of Bits Fs = 2.6 Gsps Fin = 95 MHz Fs = 2.6 Gsps Fin = 295 MHz Fs = 2.6 Gsps Fin = 595 MHz Fs = 2.6 Gsps Fin = 2295 MHz Fs = 2.6 Gsps Fin = 2595 MHz ENOB Bits 0

11 Table 2-7. Parameter Dynamic Converter Characteristics (Continued) Test Level Symbol Min Typ Max Unit Signal to Noise Ratio Fs = 2.6 Gsps Fin = 95 MHz Fs = 2.6 Gsps Fin = 295 MHz Fs = 2.6 Gsps Fin = 595 MHz Fs = 2.6 Gsps Fin = 2295 MHz Fs = 2.6 Gsps Fin = 2595 MHz SNR dbfs Total Harmonic Distortion (0 harmonics) Fs = 2.6 Gsps Fin = 95 MHz Fs = 2.6 Gsps Fin = 295 MHz Fs = 2.6 Gsps Fin = 595 MHz Fs = 2.6 Gsps Fin = 2295 MHz Fs = 2.6 Gsps Fin = 2595 MHz THD dbfs Spurious Free Dynamic Range Fs = 2.6 Gsps Fin = 95 MHz Fs = 2.6 Gsps Fin = 295 MHz Fs = 2.6 Gsps Fin = 595 MHz Fs = 2.6 Gsps Fin = 2295 MHz Fs = 2.6 Gsps Fin = 2595 MHz SFDR dbfs Two-Tone 3 rd order Intermodulation distortion IMD3 ( ): (2f-f2, 2f2-f) at 7 dbfs each tone, Fs = 2.6 Gsps Fin = 790 MHz, Fin2 = 800 MHz Fin = 550 MHz, Fin2 = 560 MHz Fin = 260 MHz, Fin2 = 2650 MHz IMD3( ) dbc Signal independent Spurious level (Fclk/ with : DMUX Ratio) ( dbfs Analog Input) Differential driven analog input (00Ω) (ADC full scale input power: 5 dbm) (0.5Vpp in 00Ω Differential analog input) Fclk/ dbfs dbm Ain = 3 dbfs, + dbm differential clock ( Vpp in 00Ω), 50% external duty cycle, binary output mode Signal to Noise and Distortion Ratio Fs = 2.6 Gsps Fin = 95 MHz Fs = 2.6 Gsps Fin = 295 MHz Fs = 2.6 Gsps Fin = 595 MHz Fs = 2.6 Gsps Fin = 2295 MHz Fs = 2.6 Gsps Fin = 2595 MHz SINAD dbfs Effective Number of Bits Fs = 2.6 Gsps Fin = 95 MHz Fs = 2.6 Gsps Fin = 295 MHz Fs = 2.6 Gsps Fin = 595 MHz Fs = 2.6 Gsps Fin = 2295 MHz Fs = 2.6 Gsps Fin = 2595 MHz ENOB Bits

12 Table 2-7. Parameter Dynamic Converter Characteristics (Continued) Test Level Symbol Min Typ Max Unit Signal to Noise Ratio Fs = 2.6 Gsps Fin = 95 MHz Fs = 2.6 Gsps Fin = 295 MHz Fs = 2.6 Gsps Fin = 595 MHz Fs = 2.6 Gsps Fin = 2295 MHz Fs = 2.6 Gsps Fin = 2595 MHz SNR dbfs Total Harmonic Distortion (0 harmonics) Fs = 2.6 Gsps Fin = 95 MHz Fs = 2.6 Gsps Fin = 295 MHz Fs = 2.6 Gsps Fin = 595 MHz Fs = 2.6 Gsps Fin = 2295 MHz Fs = 2.6 Gsps Fin = 2595 MHz THD dbfs Spurious Free Dynamic Range Fs = 2.6 Gsps Fin = 95 MHz Fs = 2.6 Gsps Fin = 295 MHz Fs = 2.6 Gsps Fin = 595 MHz Fs = 2.6 Gsps Fin = 2295 MHz Fs = 2.6 Gsps Fin = 2595 MHz SFDR dbfs Ain = 3 dbfs, + dbm differential clock ( Vpp in 00Ω), 50% external duty cycle, binary output mode Signal to Noise and Distortion Ratio Fs = 2.6 Gsps Fin = 95 MHz Fs = 2.6 Gsps Fin = 295 MHz Fs = 2.6 Gsps Fin = 595 MHz Fs = 2.6 Gsps Fin = 2295 MHz Fs = 2.6 Gsps Fin = 2595 MHz SINAD dbfs Effective Number of Bits Fs = 2.6 Gsps Fin = 95 MHz Fs = 2.6 Gsps Fin = 295 MHz Fs = 2.6 Gsps Fin = 595 MHz Fs = 2.6 Gsps Fin = 2295 MHz Fs = 2.6 Gsps Fin = 2595 MHz ENOB Bits 2

13 Table 2-7. Parameter Dynamic Converter Characteristics (Continued) Test Level Symbol Min Typ Max Unit Signal to Noise Ratio Fs = 2.6 Gsps Fin = 95 MHz Fs = 2.6 Gsps Fin = 295 MHz Fs = 2.6 Gsps Fin = 595 MHz Fs = 2.6 Gsps Fin = 2295 MHz Fs = 2.6 Gsps Fin = 2595 MHz SNR dbfs Total Harmonic Distortion (0 harmonics) Fs = 2.6 Gsps Fin = 95 MHz Fs = 2.6 Gsps Fin = 295 MHz Fs = 2.6 Gsps Fin = 595 MHz Fs = 2.6 Gsps Fin = 2295 MHz Fs = 2.6 Gsps Fin = 2595 MHz THD dbfs Spurious Free Dynamic Range Fs = 2.6 Gsps Fin = 95 MHz Fs = 2.6 Gsps Fin = 295 MHz Fs = 2.6 Gsps Fin = 595 MHz Fs = 2.6 Gsps Fin = 2295 MHz Fs = 2.6 Gsps Fin = 2595 MHz SFDR dbfs Note: Dynamic performances near full scale may vary by up to typically #0.6 bit ENOB (compared to performances specified in Table 2-7) around Fclk 0.85 Gsps,.6 Gsps,.8 Gsps, 2. Gsps & 2.35 Gsps as illustrated in Figure 2-3. For best performances, use the device in the recommended conditions settings described in Table 2-2 and Table 2-3. Figure 2-3. ENOB performance versus Fclock ENOB versus Fclk & Gain - Fin=2595 Recommended conditions of use and typical supplies - Tj = 65 C Min Gain Typ gain Max Gain ENOB (Bit_FS) Fclock (Gsps) 3

14 When a single tone sinewave at level of around -6 dbfs is applied, a SNR reduction may be observed by typically #3-5 db resulting in ENOB decrease (#-0.8 bit). (No impact on THD/SFDR). In time domain the "glitches" that may be observed in this condition are 32 LSB maximum. Their potential occurrence is reduced with minimum gain and minimum VCCA5 and higher temperature. Low Fin (st Nyquist) and/or low Fclk Frequencies are also more favourable cases. 2.. ADC Converter Characteristics with Single Ended Analog Input For optimum dynamic performances, it is strongly recommended to use a differential Analog input. In single ended input at low levels, dynamic performances are similar to those specified in Table 2-7. However, for high input levels, THD & SFDR are reduced by around db compared to Table Sensitivity of Dynamic Performances to Power Supplies The three figures below illustrate the impact of and VCCA5 power supplies on dynamic performances near full scale depending on Nyquist zone (st or 2nd). Measurements conditions are the recommended conditions of use defined in Table 2-2 & Table 2-3 at ambient temperature (Tj ~ 65 C). Figure 2-. ENOB versus VCCA5 & versus Vcca5 & Vcca3 Recommended conditions of use - Tj = 70 C 7.95 ENOB (bit_fs) Vcca3 typ, Fin=2.595 Vcca3 min, Fin=2.595 Vcca3 max, Fin=2.595 Vcca3 typ, Fin=.295 Vcca3 min, Fin=.295 Vcca3 max, Fin=.295 Vcca5 (V)

15 Figure 2-5. SNR versus VCCA5 & versus Vcca5 & Vcca3 Recommended conditions of use - Tj = 70 C 52.5 SNR (dbfs) Vcca5 (V) Vcca3 typ, Fin=2.595 Vcca3 min, Fin=2.595 Vcca3 max, Fin=2.595 Vcca3 typ, Fin=.295 Vcca3 min, Fin=.295 Vcca3 max, Fin=.295 Figure 2-6. THD versus VCCA5 & versus Vcca5 & Vcca3 Recommended conditions of use - Tj = 70 C -56 Vcca3 typ, Fin=2.595 THD (dbfs) Vcca5 (V) Vcca3 min, Fin=2.595 Vcca3 max, Fin=2.595 Vcca3 typ, Fin=.295 Vcca3 min, Fin=.295 Vcca3 max, Fin=.295 5

16 2..3 Sensitivity of dynamic performances to temperature The three following figures illustrate the impact of junction temperature on dynamic performances in st & 2nd Nyquist zone and versus Analog input level. Measurements conditions are the recommended conditions of use defined in Table 2-2 & Table 2-3. Figure 2-7. ENOB versus junction temperature in st & 2nd Nyquist 9.0 Fin =.295 GHz 9.0 Fin = GHz ENOB (bit_fs) 8.5 ENOB (bit_fs) Tj ( C) Tj ( C) Figure 2-8. SNR versus junction temperature in st & 2nd Nyquist SNR (dbfs) Fin =.295 GHz Tj SNR (dbfs) Fin = GHz Tj ( C) Figure 2-9. SFDR versus junction temperature in st & 2nd Nyquist Fin =.295 GHz Fin = GHz SFDR SFDR (dbfs) Tj ( C) Tj ( C) 6

17 Figure 2-0. THD versus junction temperature in st & 2nd Nyquist Fin =.295 GHz Fin = GHz THD THD (dbfs) Tj ( C) Tj ( C) 2.. Examples of FFT Spectrum Following spectrums (32 Kpts FFT) are given for the following conditions: Unless otherwise specified: Recommended conditions of use (refer to Table 2-2 and Table 2-3 on page 6). Typical supplies Ambient temperature with heatspreader (Tj ~65 C) Figure 2-. FFT 2.6 Gsps Fin = 295 dbfs 2.6Gsps Fin =.295 GHz -dbfs Amplitude (db) F (MHz) 7

18 Figure 2-2. FFT 2.6 Gsps Fin = 295 dbfs 2.6 Gsps Fin =.295 GHz -3dBFs Amplitude (db) F (MHz) Figure 2-3. FFT 2.6 Gsps Fin = 295 dbfs 0 2.6Gsps Fin =.295 GHz -7dBFs Amplitude (db) F (MHz) 8

19 Figure 2-. FFT 2.6 Gsps Fin = dbfs 2.6Gsps Fin =.295GHz -3dBFs Amplitude (db) F (MHz) Figure 2-5. FFT 2.6 Gsps Fin = 2595 dbfs (Carrier at end of the 2nd Nyquist Zone is folded back to baseband) 2.6Gsps Fin = GHz -3dBFs Amplitude (db) F (MHz) 9

20 Figure 2-6. FFT 2.6 Gsps Fin = dbfs (Carrier at end of the 2nd Nyquist Zone is folded back to baseband) 2.6Gsps Fin = GHz -3dBFs Amplitude (db) F (MHz) Figure 2-7. FFT 2.6 Gsps Fin = dbfs (Carrier at end of the 2nd Nyquist Zone is folded back to baseband) 2.6Gsps Fin = 2.595GHz -7dBFs Amplitude (db) F (MHz) 20

21 Figure 2-8. FFT 2.6 Gsps Fin = dbfs (Carrier at end of the 2nd Nyquist Zone is folded back to baseband) 2.6Gsps Fin = GHz -3dBFs Amplitude (db) F (MHz) 2.5 Transient and Switching Characteristics Unless otherwise specified: Recommended conditions of use (refer to Table 2-2 and Table 2-3 on page 6). Values are specified for Tj 65 C and over specified power supplies range. Typical values are given at ambient (Tj ~65 C) with typical power supplies. These conditions apply for all tables from Table 2-8 to Table 2-9. Table 2-8. Transient Characteristics Parameter Test Level Symbol Min Typ Max Unit TRANSIENT PERFORMANCE Bit Error Rate () BER 0 2 Error/sample ADC settling time (± 2%) TS 350 ps Overvoltage recovery time ORT 00 ps ADC step response Rise/Fall Time (0 90%) ps Note:. Measured with SDA OFF ADC Bit Error Rate is related to internal regeneration latches indecision (for analog inputs very close to latches threshold), which may produce large amplitude output errors. The probability of error is measured at 2.6 Gsps maximum operating frequency. 2

22 Table 2-9. Switching Characteristics Parameter Test Level Symbol Min Typ Max Unit Switching Performance and Characteristics Maximum Clock Frequency DRTYPE = DR/2, :2 mode 2.0 DRTYPE = DR, :2 mode Fs MAX 2.0 Gsps DRTYPE = DR/2 : mode 2.6 DRTYPE = DR : mode 2.6 Minimum clock frequency Fs MIN 500 Msps Minimum Clock pulse width (High) TC ns Minimum Clock pulse width (Low) TC ns External clock Duty cycle () DCYC % Aperture Delay (2) TA ps Aperture Jitter added by the ADC (2) Jitter 20 fs rms Output Rise/Fall time for Data (20% 80%) (3)) TR/TF 20/20 80/80 ps Output Rise/Fall time for Output Clock (20% 80%) (3) TR/TF 20/20 80/80 ps Digital Data Output propagation delay TOD 2.5 ns Data Ready Clock Output propagation delay TDR 2.35 ns Differential propagation delay (Output Data vs. Data clock) TOD TDR ps Tskew (0 digital output data) Tskew ± 5 ± 35 ps Output Data Pipeline delay (Latency) Synchronized :2 mode on Port A Synchronized :2 mode on Port B Synchronized : mode on Port A Synchronized : mode on Port B Synchronized : mode on Port C Synchronized : mode on Port D PD Clock Cycles Staggered :2 mode or : mode ASYNCRST minimum pulse width 5 RSTPW 3 ns DRR minimum pulse width 5 DRRPW 3.5 ns Notes:. ADC performance are given for optimum value of 50% external clock duty cycle. 2. ADC Aperture delay and Aperture jitter measured with SDA = OFF. (Default setting at Reset). 3. Rise time and fall time are defined for 00Ω differentially terminated output load with 2nH and 2 pf termination parasitics. 2.6 Timing Diagram 2.6. Aperture Delay The analog input is sampled on the rising edge of the differential clock input (CLK, CLKN) after TA (aperture delay) of +350 ps typical. Aperture delay (TA) is measured at package input balls with the assumption that the external trace length of analog input and clock input are well matched (6.6 ps/mm of mismatch with ε r = )..5 22

23 2.6.2 Latency (Simultaneous Mode and Staggered Mode) In simultaneous output mode with : DMUX Ratio, the digitized digital output data N, N+,N+2, N+3 respectively on port A, B, C and D are aligned (on the latest data available N+3 on port D). The data N on port A is available after 7.5 Clock cycles pipeline delay, plus an additional propagation delay TOD (due to Output Buffers + Package propagation delay). Due to data alignment, the pipeline delay is decreased of one clock cycle for each port from port A to D leading to: 7.5 clock cycles for port A 6.5 clock cycles for port B 5.5 clock cycles for port C.5 clock cycles for port D In simultaneous output mode with :2 DMUX ratio, the latency becomes respectively 5.5 and.5 Clock cycles on port A and port B, with same TOD propagation delay. In staggered output mode, the latency of the Digital output ports A,B,C,D is the same, since data are presented on output port as soon as available. In staggered mode for : DMUX ratio and :2 DMUX ratio latency is only.5 Clock cycles for port A, B, C and D (see Timing Diagram). The output propagation delays TOD, TOD2, TOD3, and TOD of the outputs ports in staggered mode can be considered as identical to TOD Data Ready Positioning Versus Output Data (DR/2 Mode and DR Mode) The Data Ready output clock signal (DR, DRN) is synchronized with ADC (CLK, CLKN) differential clock falling edges to be synchronous with Digital output data (since digital data are output on falling edge of sampling Clock after a latency of 7.5 Clock cycles). In : DMUX Ratio, the (DR, DRN) signal is shifted by 2 clock cycles in order to be located at center of data pulse. In :2 DMUX Ratio, the (DR, DRN) signal is shifted by clock cycle to be located at center of data pulse. Furthermore, the output propagation delay (TDR) of the Data Ready signal and the output propagation delay of the digital data (TOD) are matching very closely, and track each other over full operating temperature range. Therefore the Data signals and Data clock signals are synchronized at Package output, with the differential Data Ready output clock pulse rising edge being centered within Data pulse, in either dual Data rate mode (DR/2) or DR mode. In dual data rate (DR/2 mode), the Data clock switches at the same rate as the digital data, and therefore both the rising and falling edges of (DR, DRN) data clock are located at the center of the data pulse over temperature (with max TOD-TDR = 200 ps). In DR mode, the Data clock switches at twice the rate of the digital data, with the differential Data Ready pulse rising edge being centered within Data pulse and differential falling edges being synchronous with Data transitions. 23

24 2.6. Differential Timing Values TOD-TDR Versus Absolute Timing Values TOD and TDR The absolute values for TOD and TDR are given for information only, and are corresponding to the digital output data propagation delay and to the Data Ready output propagation delay, related to ADC output buffers throughput delay and package propagation times. TOD and TDR are measured at Package I/Os level, (Input/Outputs Balls), taking out the board extra propagation delays of the 50Ω/00Ω controlled impedance lines. Assuming the application board trace lengths are matched for digital data and data ready lines (within skew limit), one has only to consider the time difference between differential digital data outputs and differential Data clock signals TOD-TDR in simultaneous mode. In staggered mode, the differential delays are (TOD-TDR), (TOD2-TDR2), (TOD3-TDR3), (TOD- TDR). See Figure 2-20 on page 27. Therefore the absolute delay values TOD and TDR are not actually of interest: only the time difference TOD-TDR has to be actually considered. The measurement of the relative time difference is easy with matches probes, whereas absolute timings are very difficult to measure. If the propagation time delays (trace lengths for digital data outputs and Data Ready outputs are well matched, together with ideal TOD = TDR, we shall measure ideally TOD-TDR = 0 at application board outputs (FPGA or DSP incoming signals) Alignment Between Data Ready and Data Including Skew Management Real TOD-TDR excluding skew between different data is 50 ps typical, and 200 ps max. In simultaneous mode, one common Data Ready pulse (DR, DRN) is output for all differential Output Ports A,B,C,D. Therefore the skews of the differential data ports have to be as low as possible: the skews of the differential output ports due to ADC Package and internal ADC Buffers is less than ± 35 ps max (measured at Package output Balls). The external skews due to track length differences of the external 00Ω controlled impedance lines), shall be kept as low as possible. For example, (considering 3.3 ps/mm propagation time in vacuum), the signal propagation time in a different medium of dielectric constant ε r = (at 0 GHz), is yielding to SQRT(ε r ) 3.3 ps/mm = 6.6 ps/mm: a 3 mm skew in length between the 0 differential data will result in a 3 mm 6.6 ps/mm = ~ 20 ps skew, to be added to the ±35 ps skew due to the ADC (Package outputs). The total skew (ADC + board) will be in this case 70 ps + 20 ps = 90 ps = ± 5 ps in actual skew at FPGA incomings. Since TOD-TDR is 50 ps typical, and 200 ps max, TOD-TDR shall be added to the total data skew, (ADC and board), leading to: (TOD-TDR) + Tskew(total) = (200 ps) + (± 5 ps) = 25 ps maximum uncertainty on positioning of differential Data Ready signal rising edge (DR, DRN), pulse within Data pulse. In staggered mode, the (four) out-of-range bit function for the (four) Ports A,B,C,D are respectively re-allocated to the Data Ready function, available for each output Port, since latency is different, namely: Port A (AOR, AORN); Port B (BOR, BORN); Port C (COR, CORN); Port D (DOR, DORN) is respectively replaced by: (DRA, DRAN), (DRB, DRBN), (DRC, DRCN), (DRD, DRDN). The output propagation delays of the Data Ready pulses (TDR, TDR2, TDR3, TDR) are identical to the TDR output propagation delay in simultaneous mode, and are matching the Digital Data propagation delays of the Output Ports over temperature. 2

25 The relative differential timing values (TOD-TDR), (TOD2-TDR2), (TOD3-TDR3), (TOD-TDR) are identical to the TOD - TDR differential timing of the simultaneous mode. Skew for port A, B, C, D are considered for 0 bit data in staggered instead of bit of data in simultaneous. Skew between 0 data is slightly better in staggered mode. To simplify calculation skew values of previous section shall be applied Minimum Available Time Width Between Data and Data Ready (TD, TD2) At 2.6 GHz sampling rate, the time difference between zero crossing point of change of differential data and differential Data Ready output clock rising edge (centered within data pulse) is defined by TD. The time difference between differential data clock rising edge and next point of change of the differential data output is defined by TD2. The order of magnitude of time difference TD-TD2 is identical to TOD-TDR: TOD-TDR is frequency independent, whereas TD and TD2 are sampling frequency dependent: For example at : DMUX ratio, the data pulse width at maximum operating frequency of 2.6 GHz is 38.6 ps =.538 ns. Assuming TOD = TDR, the rising edge of differential data clock is ideally located at center of data pulse, with TD = TD2 = 770 ps. With a maximum difference of TOD-TDR of 200 ps over temperature, and a total of ±5 ps output Data skew (ADC + Board) and 20 ps for rise and fall times, this is yielding to a minimum available time width for TD or TD2 pulses of: 770 ps 200 ps 5 ps 20 ps = 25 ps (with 50/50 duty cycle). 25

26 2.6.7 Timing Diagram in Simultaneous and Staggered Mode Figure 2-9. Timing Diagram Simultaneous mode, : DMUX Ratio VIN ADC CLK N TA = +350 ps ADC Pipeline Delay: clock cycles ADC+: DMUX Pipeline Delay: 7.5 clock cycles on Port A clock cycles: ADC Pipeline Delay ADC (internal) Digital Outputs ( internal ) ADC Data Clock ( internal Fclock/2) DMUX Even Latches N- N-3 N-2 N- N N+ N+2 N+3 N+ N+5 N clock cycles : DMUX Pipeline Delay on Port A -2 N 2 6 DMUX Odd Latches Port Select A Port Select B Port Select C Port Select D N- N N+ N-2 N+ N+5 N-3 N+2 N+6 N- N+3 N+7 DMUX (internal) (A0, A0N)...(A9, A9N) Digital outputs : Port A N - N N+ (B0, B0N)...(B9, B9N) Digital outputs : Port B (C0, C0N)...(C9, C9N) Digital outputs : Port C N - 3 N + N - 2 N + 2 N + 5 N + 6 (D0, D0N)...(D9, D9N) Digital outputs : Port D Clock/ synchronised on falling edges of Clock Clock/8 synchronized with output Data on falling edges of Clock 2 Tclock Clock/8 shifted + 2 clock cycles Digital Outputs Port A, Port B, Port C, Port D (DR, DRN) Data Ready (in DR/2 mode) ADC : cycles N - N clock cycles (ADC+DMUX) N -8 N -7 N -6 N -5 DMUX : 3.5 cycles 2 Tclock TOD N - N -3 N -2 N - Tskew TD N + 7 TD2 Port A : N, Port B : N+ Port C : N+2 Port D : N+3 TDR Tskew 26

27 Figure Timing Diagram Staggered mode, : DMUX Ratio TA = +350ps Pipeline Delay Port A, B,C,D :.5 clock cycles VIN ADC CLK N N+ N+2 N+3 A B C D ADC Pipeline Delay: clock cycles ADC (internal) ADC Digital Outputs ADC Data Clock (Fclock / 2) N- N-3 N-2 N- N N+ N+2 N+3 N+ N+5 N+6 DMUX Even Latches -2 N 2 6 DMUX Odd Latches ADC Fclock / DMUX (internal) Port Select A N- N N+ Port Select B N-2 N+ N+5 Port Select C N-3 N+2 N+6 Port Select D N- N+3 N+7 Port A B C D DMUX Latency : 0.5 clock (A0, A0N)...(A9, A9N) Latches Port A N - N N+ (B0, B0N)...(B9, B9N) Latches Port B N - 3 N + N + 5 (C0, C0N)...(C9, C9N) Latches : Port C N - 2 N + 2 N + 6 (D0, D0N)...(D9, D9N) Port A (N) :.5 Clock Cycles (DRA, DRAN) in DR/2 mode Latches : Port D.5 ADC+DMUX Data for N N - TOD TDR N + 3 N N + 7 Tskew TD TD2 N+ Tskew Port B (N+) :.5 Clock Cycles (DRB, DRBN) in DR/2 mode N+.5 ADC+DMUX TOD2 Data for N+ TDR2 N+ N+5 Port C (N+2 ) :.5 Clock Cycles (DRC, DRCN) in DR/2 mode N+2.5 ADC+DMUX TOD3 Data for N+2 TDR3 Port D (N+3 ):.5 Clock Cycles.5 ADC+DMUX TOD (DRD, DRDN) in DR/2 mode N+3 Data for N+3 N+3 Digital Outputs & Data Ready Signals for Port A, Port B, Port C, Port D: Digital Data: after TOD, TOD2, TOD3, TOD ; Data Ready Signals: after TDR, TDR2, TDR3, TDR N+2 N+6 Tskew TD TD2 N+7 27

28 2.7 Digital Output Data Coding Table 2-0. Digital Output Data Coding Table Digital output Differential analog input Voltage level Natural Binary (2) MSB.LSB OR Binary 2 s Complement (2) MSB...LSB OR Gray Coding (2) MSB..LSB OR > mv >Top end of full scale + ½ LSB mv Top end of full scale + ½ LSB mv Top end of full scale ½ LSB mv 3 / full scale + ½ LSB mv 3 / full scale ½ LSB mv Mid scale + ½ LSB mv Mid scale ½ LSB mv / full scale + ½ LSB mv / full scale ½ LSB mv Bottom end of full scale + ½ LSB mv Bottom end of full scale ½ LSB < mv < Bottom end of full scale ½ LSB 0 A9 = B9 = C9 = D9 = MSB A0 = B0 = C0 = D0 = LSB Note:. Be aware that code 0x000 is obtained for positive full scale analog input and code 0x3FF for negative full scale. 2. Refer to Table -9 on page 5 for selection between natural binary, binary two s complement or Gray coding. 2.8 Explanation of Test Levels Table 2-. Test Levels 00% production tested at +25 C () (for C temperature range (2) ) 2 00% production tested at +25 C (), and sample tested at specified temperatures for V temperature ranges (2). 3 Sample tested only at specified temperature Parameter is guaranteed by design and characterization testing (thermal steady-state conditions at specified temperature) 5 Parameter is a typical value only guaranteed by design only Only MIN and MAX values are guaranteed (typical values are issuing from characterization results). Notes:. Unless otherwise specified. 2. Refer to Section 7. Ordering Information on page

29 2.9 Definition of Terms Table 2-2. (Fs max) (Fs min) (BER) (FPBW) (SSBW) (SINAD) (SNR) (THD) (SFDR) Definition of Terms Maximum Sampling Frequency Minimum Sampling frequency Bit Error Rate Full power input bandwidth Small Signal Input bandwidth Signal to noise and distortion ratio Signal to noise ratio Total harmonic distortion Spurious free dynamic range Performances are guaranteed up to Fs max Performances are guaranteed for clock frequency higher than Fs min Probability to exceed a specified error threshold for a sample at maximum specified sampling rate. An error code is a code that differs by more than ± 32 LSB from the correct code. Analog input frequency at which the fundamental component in the digitally reconstructed output waveform has fallen by 3 db with respect to its low frequency value (determined by FFT analysis) for input at Full Scale db ( dbfs). Analog input frequency at which the fundamental component in the digitally reconstructed output waveform has fallen by 3 db with respect to its low frequency value (determined by FFT analysis) for input at Full Scale 0 db ( 0 dbfs). Ratio expressed in db of the RMS signal amplitude, set to db below Full Scale ( dbfs), to the RMS sum of all other spectral components, including the harmonics except DC. Ratio expressed in db of the RMS signal amplitude, set to db below Full Scale, to the RMS sum of all other spectral components excluding the ten first harmonics. Ratio expressed in db of the RMS sum of the first ten harmonic components, to the RMS input signal amplitude. It may be reported in dbfs (i.e, related to converter Full Scale), or in dbc (i.e, related to input signal level). Ratio expressed in db of the RMS signal amplitude to the RMS value of the highest spectral component (peak spurious spectral component). The peak spurious component may or may not be a harmonic. It may be reported in dbfs (i.e., related to converter Full Scale), or in dbc (i.e, related to input signal level). (ENOB) Effective Number Of Bits ENOB SINAD log (A / FS/2) = Where A is the actual input amplitude and FS is the full scale range of the ADC under test (DNL) (INL) (TA) (JITTER) (TS) (ORT) (TOD) (TDR) (TD) Differential non linearity Integral non linearity Aperture delay Aperture uncertainty Settling time Overvoltage recovery time Digital data Output delay Data ready output delay Time delay from Data transition to Data Ready The Differential Non Linearity for an output code i is the difference between the measured step size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum value of all DNL (i). DNL error specification of less than LSB guarantees that there are no missing output codes and that the transfer function is monotonic. The Integral Non Linearity for an output code i is the difference between the measured input voltage at which the transition occurs and the ideal value of this transition. INL (i) is expressed in LSBs, and is the maximum value of all INL (i). Delay between the rising edge of the differential clock inputs (CLK, CLKN) (zero crossing point), and the time at which (V IN, V INN ) is sampled. Sample to sample variation in aperture delay. The voltage error due to jitter depends on the slew rate of the signal at the sampling point. Time delay to achieve 0.2% accuracy at the converter output when a 80% Full Scale step function is applied to the differential analog input. Time to recover 0.2% accuracy at the output, after a 50% full scale step applied on the input is reduced to midscale. Delay from the rising edge of the differential clock inputs (CLK, CLKN) (zero crossing point) to the next point of change in the differential output data (zero crossing) with specified load. Delay from the falling edge of the differential clock inputs (CLK, CLKN) (zero crossing point) to the next point of change in the differential output data (zero crossing) with specified load. Time delay between Data transition to output clock (Data Ready). If output clock is in the middle of the Data, TD = Tdata/2 29

30 Table 2-2. Definition of Terms (Continued) (TD2) TD-TD2 (TC) (TPD) Time delay from Data Ready to Data Encoding clock period Pipeline Delay Time delay between output clock (Data Ready) to Data transition. If output clock is in the middle of the Data, TD2 = Tdata/2. The difference TD-TD2 gives an information if the output clock is centered on the output data. If output clock is in the middle of the data TD = TD2 = Tdata/2. TC = Minimum clock pulse width (high) TC = TC + TC2 TC2 = Minimum clock pulse width (low) Number of clock cycles between the sampling edge of an input data and the associated output data being made available, (not taking in account the TOD). (TR) Rise time Time delay for the output DATA signals to rise from 20% to 80% of delta between low level and high level. (TF) Fall time Time delay for the output DATA signals to fall from 20% to 80% of delta between low level and high level. (PSRR) (IMD) (NPR) (VSWR) Power supply rejection ratio Intermodulation Distortion Noise Power Ratio Voltage Standing Wave Ratio Ratio of input offset variation to a change in power supply voltage. The two tones intermodulation distortion (IMD) rejection is the ratio of either input tone to the worst third order intermodulation products. The NPR is measured to characterize the ADC performance in response to broad bandwidth signals. When applying a notch-filtered broadband white-noise signal as the input to the ADC under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the average in-notch power spectral density magnitudes for the FFT spectrum of the ADC output sample test. The VSWR corresponds to the ADC input insertion loss due to input power reflection. For example a VSWR of.2 corresponds to a 20 db return loss (that is, 99% power transmitted and % reflected). 30

31 3. Pin Description 3. Pinout View Figure 3-. EBGA 37 Pinout Table (View from Bottom of the Package) NC AORN DGDN DGDN SLEEP STAGG A0N AN A2N A3N AN A5N SLEEP A6N A7N A8N A9N B0N BN B2N B3N A0N AN A2N A3N AN A6N A7N A8N A9N DRA B0N BN B2N B3N Sldn Sclk Sdata VCCA5 VCCA5 V CCA5 BN B0 B B2 B3 ASYNCRST AO A A2 A3 A A5 A6 A7 A8 A9 DNC VCCA5 VCCA5 VCCA5 VCCD VCCD VCCD VCCD B B5N DGND DGND VCCA5 VCCA5 VCCA5 B6N B5 VCCD VCCD VCCD VCCD VCCD SUB SUB VCCD DGND DGND VCCA5 VCCA5 VCCA5 B6 B7N VCCD VCCD / / / VCCA5 V CCA5 DGND VCCA5 VCCA5 / VCCA5 VCCA5 DGND Reset DGND / / / VIN VCCA5 VCCA5 VCCA5 VINN VCCA5 VCCA5 VCCA5 VCCA5 VCCA5 Sldn NC DNC CLK Sdata Sclk VCCA5 VCCA5 VCCA5 ADC DGND NC NC NC NC DNC DGND DGND DGND DGND CLKDACTRL NC STAGG ASYNCRST AO A A2 A3 A A5 A6 A7 A8 A9 DGND DGND VCCD SUB VCCD BIST NC NC VCCD VCCD DGND DGND DOR / DRDN DORN DRD / SUB D9 D9N SUB D8 VCCD D8N D7N VCCD VCCD VCCD D7 D6 A5N D5 D6N D5N D D3 DN D3N D2 D D2N DN AORN DRA / / AOR D0 D0N B0 B B2 B3 VCCD VCCD VCCD VCCD DGND DGND VCCD DGND DGND VCCD B5 BN B6N B7 B8N B9 RS C0N DGND DGND DGND DGND C9 C9N C8 C8N C7N C2 C3N C C5N C5 C7 NC DGND DRAN DGND DGND / COR DRCN / CORN DRC / BOR DRBN / BORN DRB C6N C6 NC DGND DGND A B C D E F G H J K L M N P R T U V W AOR DGDN DRAN VCCD VCCD VCCD VCCD B B5N VCCA5 VCCA5 B6 B7N VCCA5 VCCA5 Reset B7 B8N DGND DGND VCCA5 B8 B9N B8 B9N VCCD VCCD BORN B9 DGND DGND VIN DRB DR BOR DR DRBN VINN VCCD DRN DRTYPE VCCD VCCD DRN DRTYPE RS C0N VCCA5 VCCA5 VCCA5 VCCA5 C0 CN C0 CN DGND DGND VCCA5 C C2N C C2N Dam and Fill (not an exposed pad) Dam and Fill (not an exposed pad) C2 C3N DGND DGND DRR NC DRR NC C3 CN C3 CN VCCD SUB DGND VCCA5 C C5N VCCD VCCD VCCD VCCD VCCD VCCD VCCD VCCD VCCD VCCD VCCD VCCD VCCD VCCD DGND VCCA5 VCCD VCCD VCCD VCCD C6N C5 VCCD VCCD VCCD VCCD DGND DGND CLKDACTRL DGND DGND DGND DGND VCCA5 D D5 D6 D7 D8 D9 DOR C6 C7 C8 C9 COR D0 D D2 D3 BIST NC NC NC NC DNC DRCN DRDN NC C8N C7N C9N CORN DRC D0N D2N DN DN D3N D6N D5N D8N D7N D9N DORN / NC NC NC NC DIODE DIODE CLK CLKN DRD CLKN ADC Note: Area in dashed line corresponds to dam & fill (not an exposed pad) 3

32 3.2 Pin Description Table Table 3-. Pin Description Table Signal Name Pin Number Description Dir. Equivalent Simplified Schematics POWER SUPPLIES V CCA5 V CCA3 V PLUSD V CCD SUB DGND A2, A26, A27, B2, B26, B27, C2, C26, C27, D2, D26, D27, E2, E26, F25, L25, L26, M27, R2, T2, U2 A25, B22, B25, C20, C22, C25, D20, D22, D25, E20; E22, E25, F20, F22, F2, K25, K26, L27, M25, M26, N26, N27, R20, T20 C, C5, C6, C7, C9, C, C3, C, C5, C6, C9, D5, D6, D7, D9, D, D3, D9, E3, E9, F9, J3, J, L3, L, N3, N, R3, R, R9, T6, T7, T9, T, T3, T, T5, T9, U, U5, U6, U7, U9, U, U3, U, U5 C3, C8, C0, C2, D3, D, D8, D0, D2, D6, E, E7, G3, G, K3, K, R6, T3, T, T5, T8, T0, T2, T6, T7, U3, U8, U0, U2 D, D5, R7 A9, A20, B9, B20, C7, C8, D7, D8, E8, F3, F, F8, H3, H, M3, M, P3, P, R8, T8, U6, U7, U9, U20 Analog.9V Power Supply (ADC) Analog 3.25V Power Supply (ADC) Output 2.5V Power Supply (ADC and DMUX) Digital 3.3V Power Supply (DMUX) Substrate connect to Board Ground Plane (DGND) Digital Ground, connect to Board Ground Plane 32