LTC Bit 2-/4-Channel ΔS ADC with Easy Drive Input Current Cancellation. Features. Description. Applications. Typical Application

Transcription

1 Features n Up to Differential or 4 Single-Ended Inputs n Easy Drive Technology Enables Rail-to-Rail Inputs with Zero Differential Input Current n Directly Digitizes High Impedance Sensors with Full Accuracy n 6nV RMS Noise n Integrated High Accuracy Temperature Sensor n GND to V CC Input/Reference Common Mode Range n Programmable 5Hz, 6Hz, or Simultaneous 5Hz/6Hz Rejection Mode n ppm INL, No Missing Codes n ppm Offset and 5ppm Full-Scale Error n x Speed Mode/Reduced Power Mode (5Hz Using Internal Oscillator and 8µA at 7.5Hz Output) n No Latency: Digital Filter Settles in a Single Cycle, Even After a New Channel is Selected n Single Supply.7V to 5.5V Operation (.8mW) n Internal Oscillator n Tiny DFN 4mm 3mm Package Applications n Direct Sensor Digitizer n Direct Temperature Measurement n Instrumentation n Industrial Process Control Description LTC49 4-Bit -/4-Channel ΔS ADC with Easy Drive Input Current Cancellation The LTC 49 is a 4-channel (-channel differential), 4 bit, No Latency ADC with Easy Drive technology. The patented sampling scheme eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. This allows large external source impedances and rail-torail input signals to be directly digitized while maintaining exceptional DC accuracy. The LTC49 includes a high accuracy temperature sensor and an integrated oscillator. This device can be configured to measure an external signal (from combinations of 4 analog input channels operating in single-ended or differential modes) or its internal temperature sensor. It can be programmed to reject line frequencies of 5Hz, 6Hz, or simultaneous 5Hz/6Hz and configured to double its output rate. The integrated temperature sensor offers /3th C resolution and C absolute accuracy. The LTC49 allows a wide common mode input range (V to V CC ), independent of the reference voltage. Any combination of single-ended or differential inputs can be selected and the first conversion after a new channel selection is valid. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Easy Drive and No Latency Σ are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application Data Acquisition System with Temperature Compensation CH CH CH CH3 COM 4-CHANNEL MUX TEMPERATURE SENSOR.7V TO 5.5V V CC REF + IN + 4-BIT ADC WITH EASY-DRIVE IN REF OSC SDI CS f O 49 TAa µf.µf 4-WIRE SPI INTERFACE ABSOLUTE ERROR ( C) Absolute Temperature Error TEMPERATURE ( C) 49 TAb

2 LTC49 Absolute Maximum Ratings (Notes, ) Supply Voltage (V CC )....3V to 6V Analog Input Voltage (CH to CH3, COM)....3V to (V CC +.3V) REF +, REF....3V to (V CC +.3V) Digital Input Voltage....3V to (V CC +.3V) Digital Output Voltage....3V to (V CC +.3V) Operating Temperature Range LTC49C... C to 7 C LTC49I... 4 C to 85 C Storage Temperature Range C to 5 C Pin Configuration f O SDI CS GND COM REF 3 REF + V CC CH3 CH 9 CH 8 CH DE PACKAGE 4-LEAD (4mm 3mm) PLASTIC DFN T JMAX = 5 C, θ JA = 37 C/W EXPOSED PAD (PIN 5) IS GND, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC49CDE#PBF LTC49CDE#TRPBF 49 4-Lead (4mm 3mm) Plastic DFN C to 7 C LTC49IDE#PBF LTC49IDE#TRPBF 49 4-Lead (4mm 3mm) Plastic DFN 4 C to 85 C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: For more information on tape and reel specifications, go to: Electrical Characteristics (Normal Speed) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at. (Notes 3, 4) PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes).V V REF V CC, FS V IN +FS (Note 5) 4 Bits Integral Nonlinearity 5V V CC 5.5V,, V IN(CM) =.5V (Note 6).7V V CC 5.5V, V REF =.5V, V IN(CM) =.5V (Note 6) l ppm of V REF ppm of V REF Offset Error.5V V REF V CC, GND IN + = IN V CC (Note 4) l.5.5 µv Offset Error Drift.5V V REF V CC, GND IN + = IN V CC nv/ C Positive Full-Scale Error.5V V REF V CC, IN + =.75V REF, IN =.5V REF l 5 ppm of V REF Positive Full-Scale Error Drift.5V V REF V CC, IN + =.75V REF, IN =.5V REF. ppm of V REF / C Negative Full-Scale Error.5V V REF V CC, IN + =.5V REF, IN =.75V REF l 5 ppm of V REF Negative Full-Scale Error Drift.5V V REF V CC, IN + =.5V REF, IN =.75V REF. ppm of V REF / C Total Unadjusted Error 5V V CC 5.5V, V REF =.5V, V IN(CM) =.5V 5V V CC 5.5V,, V IN(CM) =.5V.7V V CC 5.5V, V REF =.5V, V IN(CM) =.5V Output Noise 5.5V < V CC <.7V,.5V V REF V CC, GND IN + = IN V CC (Note 3) ppm of V REF ppm of V REF ppm of V REF.6 µv RMS Internal PTAT Signal T A = 7 C (Note 4) mv Internal PTAT Temperature Coefficient 93.5 µv/ C

3 LTC49 Electrical Characteristics (x Speed) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at. (Notes 3, 4) PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes).V V REF V CC, FS V IN +FS (Note 5) 4 Bits Integral Nonlinearity 5V V CC 5.5V,, V IN(CM) =.5V (Note 6).7V V CC 5.5V, V REF =.5V, V IN(CM) =.V (Note 6) l l ppm of V REF ppm of V REF Offset Error.5V V REF V CC, GND IN + = IN V CC (Note 4) l. mv Offset Error Drift.5V V REF V CC, GND IN + = IN V CC nv/ C Positive Full-Scale Error.5V V REF V CC, IN + =.75V REF, IN =.5V REF l 5 ppm of V REF Positive Full-Scale Error Drift.5V V REF V CC, IN + =.75V REF, IN =.5V REF. ppm of V REF / C Negative Full-Scale Error.5V V REF V CC, IN + =.5V REF, IN =.75V REF l 5 ppm of V REF Negative Full-Scale Error Drift.5V V REF V CC, IN + =.5V REF, IN =.75V REF. ppm of V REF / C Output Noise 5V V CC.5V,, GND IN + = IN V CC.85 µv RMS Converter Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at. (Note 3) PARAMETER CONDITIONS MIN TYP MAX UNITS Input Common Mode Rejection DC.5V V REF V CC, GND IN + = IN V CC (Note 5) l 4 db Input Common Mode Rejection 5Hz ±%.5V V REF V CC, GND IN + = IN V CC (Note 5) l 4 db Input Common Mode Rejection 6Hz ±%.5V V REF V CC, GND IN + = IN V CC (Note 5) l 4 db Input Normal Mode Rejection 5Hz ±%.5V V REF V CC, GND IN + = IN V CC (Notes 5, 7) l db Input Normal Mode Rejection 6Hz ±%.5V V REF V CC, GND IN + = IN V CC (Notes 5, 8) l db Input Normal Mode Rejection 5Hz/6Hz ±%.5V V REF V CC, GND IN + = IN V CC (Notes 5, 9) l 87 db Reference Common Mode Rejection DC.5V V REF V CC, GND IN + = IN V CC (Note 5) l 4 db Power Supply Rejection DC V REF =.5V, IN + = IN = GND db Power Supply Rejection, 5Hz ±% V REF =.5V, IN + = IN = GND (Notes 7, 9) db Power Supply Rejection, 6Hz ±% V REF =.5V, IN + = IN = GND (Notes 8, 9) db Analog Input and Reference The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IN + Absolute/Common Mode IN + Voltage GND.3V V CC +.3V V (IN + Corresponds to the Selected Positive Input Channel) IN Absolute/Common Mode IN Voltage (IN Corresponds to the Selected Negative Input Channel or COM) GND.3V V CC +.3V V V IN Input Voltage Range (IN + IN ) Differential/Single-Ended l FS +FS V FS Full Scale of the Input (IN + IN ) Differential/Single-Ended l.5v REF V LSB Least Significant Bit of the Output Code l FS/ 4 REF + Absolute/Common Mode REF + Voltage l. V CC V REF Absolute/Common Mode REF Voltage l GND REF +.V V V REF Reference Voltage Range (REF + REF ) l. V CC V CS(IN + ) IN + Sampling Capacitance pf CS(IN ) IN Sampling Capacitance pf 3

4 LTC49 Analog Input and Reference The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CS(V REF ) V REF Sampling Capacitance pf I + DC_LEAK(IN ) IN + DC Leakage Current Sleep Mode, IN + = GND l na I DC_LEAK(IN ) IN DC Leakage Current Sleep Mode, IN = GND l na I + DC_LEAK(REF ) REF + DC Leakage Current Sleep Mode, REF + = V CC l na I DC_LEAK(REF ) REF DC Leakage Current Sleep Mode, REF = GND l na t OPEN MUX Break-Before-Make 5 ns QIRR MUX Off Isolation V IN = V P-P DC to.8mhz db Digital Inputs and Digital Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IH High Level Input Voltage (CS, f O, SDI).7V V CC 5.5V (Note 8) l V CC.5 V V IL Low Level Input Voltage (CS, f O, SDI).7V V CC 5.5V l.5 V V IH High Level Input Voltage ().7V V CC 5.5V (Notes, 5) l V CC.5 V V IL Low Level Input Voltage ().7V V CC 5.5V (Notes, 5) l.5 V I IN Digital Input Current (CS, f O, SDI) V V IN V CC l µa I IN Digital Input Current () V V IN V CC (Notes, 5) l µa C IN Digital Input Capacitance (CS, f O, SDI) pf C IN Digital Input Capacitance () (Notes, 5) pf V OH High Level Output Voltage () I O = 8µA l V CC.5 V V OL Low Level Output Voltage () I O =.6mA l.4 V V OH High Level Output Voltage () I O = 8µA (Notes, 7) l V CC.5 V V OL Low Level Output Voltage () I O =.6mA (Notes, 7) l.4 V I OZ Hi-Z Output Leakage () l µa Power Requirements The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V CC Supply Voltage l V I CC Supply Current Conversion Current (Note ) Temperature Measurement (Note ) Sleep Mode (Note ) l l l µa µa µa Digital Inputs and Digital Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f EOSC External Oscillator Frequency Range (Note 6) l khz t HEO External Oscillator High Period l.5 µs t LEO External Oscillator Low Period l.5 µs 4

5 LTC49 Digital Inputs And Digital Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t CONV_ Conversion Time for x Speed Mode 5Hz Mode 6Hz Mode Simultaneous 5/6Hz Mode External Oscillator t CONV_ Conversion Time for x Speed Mode 5Hz Mode 6Hz Mode Simultaneous 5/6Hz Mode External Oscillator f I Internal Frequency Internal Oscillator (Notes, 7) External Oscillator (Notes,, 5) l l l l l l /f EOSC (in khz) /f EOSC (in khz) 38.4 f EOSC /8 D I Internal Duty Cycle (Notes, 7) l % f E External Frequency Range (Notes,, 5) l 4 khz t LE External Low Period (Notes,, 5) l 5 ns t HE External High Period (Notes,, 5) l 5 ns t DOUT_I Internal 3-Bit Data Output Time Internal Oscillator (Notes, 7) External Oscillator (Notes,, 5) l /f EOSC (in khz) ms ms ms ms ms ms ms ms khz khz.85 ms ms t DOUT_E External 3-Bit Data Output Time (Notes,, 5) 3/f E (in khz) ms t CS to Low l ns t CS to Hi-Z l ns t 3 CS to Internal Mode l ns t 4 CS to External Mode l 5 ns t KQMAX to Valid l ns t KQMIN Hold After (Note 5) l 5 ns t 5 Set Up Before CS l 5 ns t 7 SDI Set Up Before (Note 5) l ns t 8 SDI Hold After (Note 5) l ns Note : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note : All voltage values are with respect to GND. Note 3: Unless otherwise specified: V CC =.7V to 5.5V V REFCM = V REF /, F S =.5V REF V IN = IN + IN, V IN(CM) = (IN + IN )/, where IN + and IN are the selected input channels. Note 4: Use internal conversion clock or external conversion clock source with f EOSC = 37.kHz unless other wise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: 5Hz mode (internal oscillator) or f EOSC = 56kHz ±% (external oscillator). Note 8: 6Hz mode (internal oscillator) or f EOSC = 37.kHz ±% (external oscillator). Note 9: Simultaneous 5Hz/6Hz mode (internal oscillator) or f EOSC = 8kHz ±% (external oscillator). Note : The can be configured in external mode or internal mode. In external mode, the pin is used as a digital input and the driving clock is f E. In the internal mode, the pin is used as a digital output and the output clock signal during the data output is f I. Note : The external oscillator is connected to the f O pin. The external oscillator frequency, f EOSC, is expressed in khz. Note : The converter uses its internal oscillator. Note 3: The output noise includes the contribution of the internal calibration operations. Note 4: Guaranteed by design and test correlation. Note 5: The converter is in external mode of operation such that the pin is used as a digital input. The frequency of the clock signal driving during the data output is f E and is expressed in Hz. Note 6: Refer to Applications Information section for performance vs data rate graphs. Note 7: The converter in internal mode of operation such that the pin is used as a digital output. Note 8: For V CC < 3V, V IH is.5v for pin f O. 5

6 LTC49 Typical Performance Characteristics 3 Integral Nonlinearity (, ) V IN(CM) =.5V 3 Integral Nonlinearity (, V REF =.5V) V REF =.5V V IN(CM) =.5V 3 Integral Nonlinearity (V CC =.7V, V REF =.5V) V CC =.7V V REF =.5V V IN(CM) =.5V INL (ppm OF V REF ) 45 C 85 C 5 C INL (ppm OF V REF ) 45 C, 5 C, 9 C INL (ppm OF V REF ) 45 C, 5 C, 9 C INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V) 49 G G 49 G TUE (ppm OF V REF ) Total Unadjusted Error (, ) V IN(CM) =.5V 85 C 5 C 45 C TUE (ppm OF V REF ) Total Unadjusted Error (, V REF =.5V) V REF =.5V V IN(CM) =.5V 5 C 85 C 45 C TUE (ppm OF V REF ) Total Unadjusted Error (V CC =.7V, V REF =.5V) V CC =.7V V REF =.5V V IN(CM) =.5V 85 C 5 C 45 C INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V).5 49 G4 49 G5 49 G6 NUMBER OF READINGS (%) 4, CONSECUTIVE READINGS RMS =.6µV AVERAGE =.69µV V IN = V Noise Histogram (6.8sps) Noise Histogram (7.5sps) Long-Term ADC Readings OUTPUT READING (µv) NUMBER OF READINGS (%) 4, CONSECUTIVE READINGS V CC =.7V V REF =.5V V IN = V RMS =.59µV AVERAGE =.9µV OUTPUT READING (µv) ADC READING (µv) ,, V IN = V, V IN(CM) =.5V, RMS NOISE =.6µV 3 4 TIME (HOURS) G7 49 G8 49 G9 6

7 Typical Performance Characteristics LTC49 RMS NOISE (µv) RMS Noise vs Input Differential Voltage RMS Noise vs V IN(CM) RMS Noise vs Temperature (T A ) V IN(CM) =.5V RMS NOISE (µv) V IN = V RMS NOISE (µv) V IN = V V IN(CM) = GND INPUT DIFFERENTIAL VOLTAGE (V) V IN(CM) (V) TEMPERATURE ( C) G 49 G 49 G RMS NOISE (µv) RMS Noise vs V CC RMS Noise vs V REF Offset Error vs V IN(CM) V REF =.5V V IN = V V IN(CM) = GND RMS NOISE (µv) V IN = V V IN(CM) = GND OFFSET ERROR (ppm OF V REF ) V IN = V V CC (V) V REF (V) V IN(CM) (V) 49 G3 49 G4 49 G5 OFFSET ERROR (ppm OF V REF ) Offset Error vs Temperature Offset Error vs V CC Offset Error vs V REF V IN = V V IN(CM) = GND F O = GND OFFSET ERROR (ppm OF V REF ) REF + =.5V REF = GND V IN = V V IN(CM) = GND OFFSET ERROR (ppm OF V REF ) REF = GND V IN = V V IN(CM) = GND TEMPERATURE ( C) V CC (V) V REF (V) 5 49 G6 49 G7 49 G8 7

8 LTC49 Typical Performance Characteristics FREQUENCY (khz) On-Chip Oscillator Frequency vs Temperature 34 V CC = 4.V 3 V REF =.5V V IN = V V IN(CM) = GND TEMPERATURE ( C) 49 G9 FREQUENCY (khz) On-Chip Oscillator Frequency vs V CC V CC (V) V REF =.5V V IN = V V IN(CM) = GND G REJECTION (db) PSRR vs Frequency at V CC V CC = 4.V DC V REF =.5V IN + = GND IN = GND k k k M FREQUENCY AT V CC (Hz) 49 G REJECTION (db) PSRR vs Frequency at V CC PSRR vs Frequency at V CC vs Temperature Conversion Current V CC = 4.V DC ±.4V V REF =.5V IN + = GND IN = GND REJECTION (db) V CC = 4.V DC ±.7V V REF =.5V IN + = GND IN = GND CONVERSION CURRENT (µa) CS = GND = NC = NC SDI = GND V CC =.7V FREQUENCY AT V CC (Hz) FREQUENCY AT V CC (Hz) TEMPERATURE ( C) 49 G 49 G3 49 G4 SLEEP MODE CURRENT (µa) Sleep Mode Current vs Temperature CS = V CC = NC = NC SDI = GND V CC =.7V SUPPLY CURRENT (µa) Conversion Current vs Output Data Rate V REF = V CC IN + = GND IN = GND = NC = NC SDI = GND CS GND f O = EXT OSC V CC = 3V INL (ppm OF V REF ) 3 Integral Nonlinearity (x Speed Mode;, ) V IN(CM) =.5V 5 C, 9 C 45 C TEMPERATURE ( C) 3 OUTPUT DATA RATE (READINGS/SEC) INPUT VOLTAGE (V).5 49 G5 49 G6 49 G7 8

9 Typical Performance Characteristics LTC49 INL (ppm OF V REF ) 3 Integral Nonlinearity (x Speed Mode;, V REF =.5V) V REF =.5V V IN(CM) =.5V 9 C 45 C, 5 C INL (ppm OF V REF ) 3 Integral Nonlinearity (x Speed Mode; V CC =.7V, V REF =.5V) V CC =.7V V REF =.5V V IN(CM) =.5V 9 C 45 C, 5 C NUMBER OF READINGS (%) Noise Histogram (x Speed Mode), CONSECUTIVE READINGS V IN = V RMS =.85µV AVERAGE =.84mV INPUT VOLTAGE (V) INPUT VOLTAGE (V) OUTPUT READING (µv) 49 G8 49 G9 49 G3 RMS NOISE (µv) RMS Noise vs V REF (x Speed Mode) V IN = V V IN(CM) = GND V REF (V) OFFSET ERROR (µv) Offset Error vs V IN(CM) (x Speed Mode) V IN = V V IN(CM) (V) OFFSET ERROR (µv) Offset Error vs Temperature (x Speed Mode) V IN = V V IN(CM) = GND TEMPERATURE ( C) 49 G3 49 G3 49 G33 9

10 LTC49 Typical Performance Characteristics OFFSET ERROR (µv) Offset Error vs V CC (x Speed Mode) V REF =.5V V IN = V V IN(CM) = GND OFFSET ERROR (µv) Offset Error vs V REF (x Speed Mode) V IN = V V IN(CM) = GND REJECTION (db) PSRR vs Frequency at V CC (x Speed Mode) V CC = 4.V DC REF + =.5V REF = GND IN + = GND IN = GND V CC (V) V REF (V) 4 k k k M FREQUENCY AT V CC (Hz) 49 G34 49 G35 49 G36 RREJECTION (db) PSRR vs Frequency at V CC (x Speed Mode) V CC = 4.V DC ±.4V REF + =.5V REF = GND IN + = GND IN = GND REJECTION (db) PSRR vs Frequency at V CC (x Speed Mode) V CC = 4.V DC ±.7V REF + =.5V REF = GND IN + = GND IN = GND FREQUENCY AT V CC (Hz) FREQUENCY AT V CC (Hz) 49 G37 49 G38

11 Pin Functions f O (Pin ): Frequency Control Pin. Digital input that controls the internal conversion clock rate. When f O is connected to GND, the converter uses its internal oscillator running at 37.kHz. The conversion clock may also be overridden by driving the f O pin with an external clock in order to change the output rate and the digital filter rejection null. SDI (Pin ): Serial Data Input. This pin is used to select the line frequency rejection mode, or speed mode, temperature sensor, as well as the input channel. The serial data input is applied under control of the serial clock () during the data output/input operation. The first conversion following a new input or mode change is valid. (Pin 3): Bidirectional, Digital I/O, Clock Pin. In Internal Serial Clock Operation mode, is generated internally and is seen as an output on the pin. In External Serial Clock Operation mode, the digital I/O clock is externally applied to the pin. The Serial Clock operation mode is determined by the logic level applied to the pin at power up and during the most recent falling edge of CS. CS (Pin 4): Active LOW Chip Select. A LOW on this pin enables the digital input/output and wakes up the ADC. Following each conversion, the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the data output aborts the data transfer and starts a new conversion. (Pin 5): Three-State Digital Output. During the data output period, this pin is used as the serial data output. When the chip select pin is HIGH, the pin is in a high impedance state. During the conversion and sleep periods, LTC49 this pin is used as the conversion status output. When the conversion is in progress this pin is HIGH; once the conversion is complete goes low. The conversion status is monitored by pulling CS LOW. GND (Pin 6): Ground. Connect this pin to a common ground plane through a low impedance connection. COM (Pin 7): The common negative input (IN ) for all single-ended multiplexer configurations. The voltage on CH to CH3 and COM pins can have any value between GND.3V to V CC +.3V. Within these limits, the two selected inputs (IN + and IN ) provide a bipolar input range (V IN = IN + IN ) from.5 V REF to.5 V REF. Outside this input range, the converter produces unique over-range and under-range output codes. CH to CH3 (Pins 8-): Analog Inputs. May be programmed for single-ended or differential mode. V CC (Pin ): Positive Supply Voltage. Bypass to GND with a µf tantalum capacitor in parallel with a.µf ceramic capacitor as close to the part as possible. REF + (Pin 3), REF (Pin 4): Differential Reference Input. The voltage on these pins can have any value between GND and V CC as long as the reference positive input, REF +, remains more positive than the negative reference input, REF, by at least.v. The differential voltage (V REF = REF + REF ) sets the full-scale range for all input channels. When performing an on-chip temperature measurement, the minimum value of REF = V. Exposed Pad (Pin 5): Ground. This pin is ground and must be soldered to the PCB ground plane. For prototyping purposes, this pin may remain floating.

12 LTC49 Functional Block Diagram V CC TEMP SENSOR INTERNAL OSCILLATOR GND REF + REF AUTOCALIBRATION AND CONTROL f O (INT/EXT) CH CH CH CH3 COM MUX IN + IN + DIFFERENTIAL 3RD ORDER MODULATOR SERIAL INTERFACE SDI CS DECIMATING FIR ADDRESS 49 BD Figure. Functional Block Diagram Test Circuits V CC.69k.69k C LOAD = pf C LOAD = pf Hi-Z TO V OH V OL TO V OH V OH TO Hi-Z 49 TC Hi-Z TO V OL V OH TO V OL V OL TO Hi-Z 49 TC

13 LTC49 Timing Diagrams Timing Diagram Using Internal ( HIGH with CS ) CS t t Hi-Z t 3 t KQMIN t KQMAX Hi-Z t 7 t 8 SDI SLEEP DATA IN/OUT CONVERSION 49 TD Timing Diagram Using External ( LOW with CS ) CS t t Hi-Z t 5 t4 t KQMIN t KQMAX Hi-Z t 7 t 8 SDI SLEEP DATA IN/OUT CONVERSION 49 TD 3

14 LTC49 Applications Information Converter Operation Converter Operation Cycle The LTC49 is a multi-channel, low power, delta-sigma analog-to-digital converter with an easy to use 4-wire interface and automatic differential input current cancellation. Its operation is made up of four states (See Figure ). The converter operating cycle begins with the conversion, followed by the sleep state and ends with the data input/ output cycle. The 4-wire interface consists of serial data output (), serial clock (), chip select (CS) and serial data input (SDI). The interface, timing, operation cycle, and data output format is compatible with Linear s entire family of SPI Δ converters. Initially, at power up, the LTC49 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, if CS is HIGH, power consumption is reduced by two orders of magnitude. The part remains in the sleep state as long as CS is HIGH. The conversion result is held indefinitely in a static shift register while the part is in the sleep state. Once CS is pulled LOW, the device powers up, exits the sleep state, and enters the data input/output state. If CS is brought HIGH before the first rising edge of, the device returns to the sleep state and the power is reduced. If CS is brought HIGH after the first rising edge of, the POWER UP IN + = CH, IN = CH 5/6Hz,x CONVERT SLEEP CS = LOW AND data output cycle is aborted and a new conversion cycle begins. The data output corresponds to the conversion just completed. This result is shifted out on the serial data output pin () under the control of the serial clock pin (). Data is updated on the falling edge of allowing the user to reliably latch data on the rising edge of (See Figure 3). The configuration data for the next conversion is also loaded into the device at this time. Data is loaded from the serial data input pin (SDI) on each rising edge of. The data input/output cycle concludes once 3 bits are read out of the ADC or when CS is brought HIGH. The device automatically initiates a new conversion and the cycle repeats. Through timing control of the CS and pins, the LTC49 offers several flexible modes of operation (internal or external and free-running conversion modes). These various modes do not require programming and do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section. Ease of Use The LTC49 data output has no latency, filter settling delay, or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog inputs is straight forward. Each conversion, immediately following a newly selected input or mode, is valid and accurate to the full specifications of the device. The LTC49 automatically performs offset and full scale calibration every conversion cycle independent of the input channel selected. This calibration is transparent to the user and has no effect with the operation cycle described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage variation, input channel, and temperature drift. 4 CHANNEL SELECT CONFIGURATION SELECT DATA OUTPUT 49 F Figure. LTC49 State Transition Diagram

15 Applications Information Easy Drive Input Current Cancellation The LTC49 combines a high precision delta-sigma ADC with an automatic, differential, input current cancellation front end. A proprietary front-end passive sampling network transparently removes the differential input current. This enables external RC networks and high impedance sensors to directly interface to the LTC49 without external amplifiers. The remaining common mode input current is eliminated by either balancing the differential input impedances or setting the common mode input equal to the common mode reference (see Automatic Differential Input Current Cancellation Section). This unique architecture does not require on-chip buffers, thereby enabling signals to swing beyond ground and V CC. Moreover, the cancellation does not interfere with the transparent offset and full-scale auto-calibration and the absolute accuracy (full scale + offset + linearity + drift) is maintained even with external RC networks. Power-Up Sequence The LTC49 automatically enters an internal reset state when the power supply voltage V CC drops below approximately V. This feature guarantees the integrity of the conversion result, input channel selection and serial clock mode. When V CC rises above this threshold, the converter creates an internal power-on-reset (POR) signal with a duration of approximately 4ms. The POR signal clears all internal registers. The conversion immediately following a POR cycle is performed on the input channel IN + = CH, IN = CH, simultaneous 5Hz/6Hz rejection and output rate. The first conversion following a POR cycle is accurate within the specification of the device if the power supply voltage is restored to (.7V to 5.5V) before the end of the POR interval. A new input channel, rejection mode, speed mode, or temperature selection can be programmed into the device during this first data input/output cycle. Reference Voltage Range This converter accepts a truly differential external reference voltage. The absolute/common mode voltage range for REF + and REF pins covers the entire operating range of LTC49 the device (GND to V CC ). For correct converter operation, V REF must be positive (REF + > REF ). The LTC49 differential reference input range is.v to V CC. For the simplest operation, REF + can be shorted to V CC and REF can be shorted to GND. The converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in nanovolts is nearly constant with reference voltage. A decrease in reference voltage will not significantly improve the converter s effective resolution. On the other hand, a decreased reference will improve the converter s overall INL performance. Input Voltage Range The LTC49 input measurement range is.5 V REF to +.5 V REF in both differential and single-ended configurations as shown in Figure 38. Highest linearity is achieved with Fully Differential drive and a constant common-mode voltage (Figure 38b). Other drive schemes may incur an INL error of approximately 5ppm. This error can be calibrated out using a three point calibration and a second-order curve fit. The analog inputs are truly differential with an absolute, common mode range for the CH to CH3 and COM input pins extending from GND.3V to V CC +.3V. Outside these limits, the ESD protection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits, the LTC49 converts the bipolar differential input signal V IN = IN + IN (where IN + and IN are the selected input channels), from FS =.5 V REF to +FS =.5 V REF where V REF = REF + REF. Outside this range, the converter indicates the overrange or the underrange condition using distinct output codes (see Table ). Signals applied to the input (CH to CH3, COM) may extend 3mV below ground and above V CC. In order to limit any fault current, resistors of up to 5k may be added in series with the input. The effect of series resistance on the converter accuracy can be evaluated from the curves presented in the Input Current/Reference Current sections. In addition, series resistors will introduce a temperature dependent error due to input leakage current. A na input leakage current will develop a ppm offset error on a 5k resistor if. This error has a very strong temperature dependency. 5

16 LTC49 Applications Information Serial Interface Pins The LTC49 transmits the conversion result, reads the input configuration, and receives a start of conversion command through a synchronous 3- or 4-wire interface. During the conversion and sleep states, this interface can be used to access the converter status. During the data output state, it is used to read the conversion result, program the input channel, rejection frequency, speed multiplier, and select the temperature sensor. Serial Clock Input/Output () The serial clock pin () is used to synchronize the data input/output transfer. Each bit is shifted out of the pin on the falling edge of and data is shifted into the SDI pin on the rising edge of. The serial clock pin () can be configured as either a master ( is an output generated internally) or a slave ( is an input and applied externally). Master mode (Internal ) is selected by simply floating the pin. Slave mode (External ) is selected by driving low during power up and each falling edge of CS. Specific details of these modes are described in the Serial Interface Timing Modes section. Serial Data Output () The serial data output pin () provides the result of the last conversion as a serial bit stream (MSB first) during the data output state. In addition, the pin is used as an end of conversion indicator during the conversion and sleep states. When CS is HIGH, the driver is switched to a high impedance state in order to share the data output line with other devices. If CS is brought LOW during the conversion phase, the EOC bit ( pin) will be driven HIGH. Once the conversion is complete, if CS is brought LOW, EOC will be driven LOW indicating the conversion is complete and the result is ready to be shifted out of the device. Chip Select (CS) The active low CS pin is used to test the conversion status, enable I/O data transfer, initiate a new conversion, control the duration of the sleep state, and set the mode. At the conclusion of a conversion cycle, while CS is HIGH, the device remains in a low power sleep state where the supply current is reduced several orders of magnitude. In order to exit the sleep state and enter the data output state, CS must be pulled low. Data is now shifted out the pin under control of the pin as described previously. A new conversion cycle is initiated either at the conclusion of the data output cycle (all 3 data bits read) or by pulling CS HIGH any time between the first and 3nd rising edges of the serial clock (). In this case, the data output is aborted and a new conversion begins. Serial Data Input (SDI) The serial data input (SDI) is used to select the input channel, rejection frequency, speed multiplier and to access the integrated temperature sensor. Data is shifted into the device during the data output/input state on the rising edge of while CS is low. OUTPUT DATA FORMAT The LTC49 serial output stream is 3 bits long. The first bit indicates the conversion status, the second bit is always zero, and the third bit conveys sign information. The next 4 bits are the conversion result, MSB first. The remaining 5 bits are sub LSBs beyond the 4-bit level that may be included in averaging or discarded without loss of resolution. Bit 3 (first output bit) is the end of conversion (EOC) indicator. This bit is available on the pin during the conversion and sleep states whenever CS is LOW. This bit is HIGH during the conversion cycle, goes LOW once the conversion is complete, and is Hi-Z when CS is HIGH. Bit 3 (second output bit) is a dummy bit (DMY) and is always LOW. Bit 9 (third output bit) is the conversion result sign indicator (SIG). If the selected input (V IN = IN + IN ) is greater than V, this bit is HIGH. If V IN <, this bit is LOW. 6

17 LTC49 Applications Information Bit 8 (fourth output bit) is the most significant bit (MSB) of the result. This bit in conjunction with Bit 9 also provides underrange and overrange indication. If both Bit 9 and Bit 8 are HIGH, the differential input voltage is above +FS. If both Bit 9 and Bit 8 are LOW, the differential input voltage is below FS. The function of these bits is summarized in Table. Table. LTC49 Status Bits INPUT RANGE BIT 3 EOC BIT 3 DMY BIT 9 SIG BIT 8 MSB V IN.5 V REF V V IN <.5 V REF /.5 V REF V IN < V V IN <.5 V REF Bits 8 to 5 are the 4-bit conversion result MSB first. Bit 5 is the least significant bit (LSB 4 ). Bits 4 to are sub LSBs below the 4-bit level. Bits 4 to may be included in averaging or discarded without loss of resolution. Data is shifted out of the pin under control of the serial clock () (see Figure 3). Whenever CS is HIGH, remains high impedance and is ignored. In order to shift the conversion result out of the device, CS must first be driven LOW. EOC is seen at the pin of the device once CS is pulled LOW. EOC changes in real time as a function of the internal oscillator or the clock applied to the f O pin from HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for an external microcontroller. Bit 3 (EOC) can be captured on the first rising edge of. Bit 3 is shifted out of the device on the first falling edge of. The final data bit (Bit ) is shifted out on the on the falling edge of the 3st and may be latched on the rising edge of the 3nd pulse. On the falling edge of the 3nd pulse, goes HIGH indicating the initiation of a new conversion cycle. This bit serves as EOC (Bit 3) for the next conversion cycle. Table summarizes the output data format. As long as the voltage on the IN + and IN pins remains between.3v and V CC +.3V (absolute maximum operating range) a conversion result is generated for any differential input voltage V IN from FS =.5 V REF to +FS =.5 V REF. For differential input voltages greater than +FS, the conversion result is clamped to the value corresponding to +FS + LSB. For differential input voltages below FS, the conversion result is clamped to the value FS LSB. Input Data Format The LTC49 serial input word is 3 bits long and contains two distinct sets of data. The first set (SGL, ODD, A, A, A) is used to select the input channel. The second set of data (IM, FA, FB, SPD) is used to select the frequency rejection, speed mode (, ), and temperature measurement. After power up, the device initiates an internal reset cycle which sets the input channel to CH to CH (IN + = CH, IN = CH), the frequency rejection to simultaneous 5Hz/6Hz, and output rate (auto-calibration enabled). The first conversion automatically begins at power up using this CS (EXTERNAL) SDI DON'T CARE EN SGL ODD A A A EN IM FA FB SPD DON'T CARE EOC SIG MSB BIT 3 BIT 3 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT BIT BIT BIT 9 BIT 8 BIT 7 BIT CONVERSION SLEEP DATA INPUT/OUTPUT 49 F3 Figure 3. Channel Selection, Configuration Selection and Data Output Timing 7

18 LTC49 Applications Information Table. Output Data Format DIFFERENTIAL INPUT VOLTAGE V IN * BIT 3 EOC BIT 3 DMY BIT 9 SIG BIT 8 MSB BIT 7 BIT 6 BIT 5 BIT 5 LSB BITS 4 to SUB LSBs V IN *.5 V REF **.5 V REF ** LSB XXXXX.5 V REF ** XXXXX.5 V REF ** LSB XXXXX / XXXXX LSB XXXXX.5 V REF ** XXXXX.5 V REF ** LSB XXXXX.5 V REF ** XXXXX V IN * <.5 V REF ** X XXXXX * The differential input voltage V IN = IN + IN. ** The differential reference voltage V REF = REF + REF. Sub LSBs are below the 4-bit level. They may be included in averaging, or discarded without loss of resolution. The sign bit changes state during the output code when the device is operating in the x speed mode. The underrange output code is XFFFFXXX in x mode. default configuration. Once the conversion is complete, a new word may be written into the device. The first three bits shifted into the device consist of two preamble bits and an enable bit. These bits are used to enable the device configuration and input channel selection. Valid settings for these three bits are, and. Other combinations should be avoided. If the first three bits are or, the following data is ignored (don t care) and the previously selected input channel and configuration remain valid for the next conversion. If the first three bits shifted into the device are, then the next five bits select the input channel for the next conversion cycle (see Table 3). Table 3 Channel Selection MUX ADDRESS CHANNEL SELECTION SGL ODD/ SIGN A A A 3 COM * IN + IN IN + IN IN IN + IN IN + IN + IN IN + IN IN + IN IN + IN *Default at power up The first input bit (SGL) following the sequence determines if the input selection is differential (SGL = ) or single-ended (SGL = ). For SGL =, two adjacent channels can be selected to form a differential input. For SGL =, one of four channels is selected as the positive input. The negative input is COM for all single-ended operations. The remaining four bits (ODD, A, A, A) determine which channel(s) is/are selected and the polarity (for a differential input). The next serial input bit immediately following the input channel selection is the enable bit for the conversion configuration (EN). If this bit is set to, then the next conversion is performed using the previously selected converter configuration. A new configuration can be loaded into the device by setting EN = (see Table 4). The first bit (IM) is used to select the internal temperature sensor. If IM =, the following conversion will be performed on the internal temperature sensor rather than the selected input channel. The next two bits (FA and FB) are used to set the rejection frequency. The final bit (SPD) is used to select either the x output rate if SPD = (auto-calibration is enabled and the offset is continuously calibrated and removed from the final conversion result) or the x output rate if SPD = (offset calibration disabled, multiplexing output rates up to 5Hz with no latency). When IM = (temperature measurement) SPD will be ignored and the device will 8

19 Applications Information LTC49 Table 4. Converter Configuration EN SGL ODD A A A EN IM FA FB SPD CONVERTER CONFIGURATION X X X X X X X X X X Keep Previous X X X X X X X X X Keep Previous X X X X X X X X X X Keep Previous X X X X X External Input (See Table 3) 5Hz/6Hz Rejection, x X X X X X External Input (See Table 3) 5Hz Rejection, x X X X X X External Input (See Table 3) 6Hz Rejection, x X X X X X External Input (See Table 3) 5Hz/6Hz Rejection, x X X X X X External Input (See Table 3) 5Hz Rejection, x X X X X X External Input (See Table 3) 6Hz Rejection, x X X X X X X Measure Temperature 5Hz/6Hz Rejection, x X X X X X X Measure Temperature 5Hz Rejection, x X X X X X X Measure Temperature 6Hz Rejection, x X X X X X X X Reserved, Do Not Use operate in mode. The configuration remains valid until a new input word with EN = (the first three bits are ) and EN = is shifted into the device. Rejection Mode (FA, FB) The LTC49 includes a high accuracy on-chip oscillator with no required external components. Coupled with an integrated 4th order digital lowpass filter, the LTC49 rejects line frequency noise. In the default mode, the LTC49 simultaneously rejects 5Hz and 6Hz by at least 87dB. If more rejection is required, the LTC49 can be configured to reject 5Hz or 6Hz to better than db. Speed Mode (SPD) Every conversion cycle, two conversions are combined to remove the offset (default mode). This result is free from offset and drift. In applications where the offset is not critical, the auto-calibration feature can be disabled with the benefit of twice the output rate. While operating in the x mode (SPD = ), the linearity and full-scale errors are unchanged from the mode performance. In both the and mode there is no latency. This enables input steps or multiplexer changes to settle in a single conversion cycle, easing system overhead and increasing the effective conversion rate. During temperature measurements, the mode is always used independent of the value of SPD. Temperature Sensor The LTC49 includes an integrated temperature sensor. The temperature sensor is selected by setting IM =. The digital output is proportional to the absolute temperature of the device. This feature allows the converter to perform cold junction compensation for external thermocouples or continuously remove the temperature effects of external sensors. The internal temperature sensor output is 8mV at 7 C (3 K), with a slope of 93.5µV/ C independent of V REF (see Figures 4 and 5). Slope calibration is not required if the reference voltage (V REF ) is known. A 5V reference has a slope of 34 LSBs 4 / C. The temperature is calculated 9

20 LTC49 Applications Information from the output code (DATAOUT 4 ) for a 5V reference using the following formula: T K = DATAOUT 4 /34 in Kelvin If a different value of V REF is used, the temperature output is: T K = DATAOUT 4 V REF /57 in Kelvin If the value of V REF is not known, the slope is determined by measuring the temperature sensor at a known temperature T N (in K) and using the following formula: SLOPE = DATAOUT 4 /T N This value of slope can be used to calculate further temperature readings using: T K = DATAOUT 4 /SLOPE All Kelvin temperature readings can be converted to T C ( C) using the fundamental equation: T C = T K 73 Serial Interface Timing Modes The LTC49 s 4-wire interface is SPI and MICROWIRE compatible. This interface offers several flexible modes of operation. These include internal/external serial clock, 3- or 4-wire I/O, single cycle or continuous conversion. The following sections describe each of these timing modes in detail. In all cases, the converter can use the internal oscillator (f O = LOW) or an external oscillator connected to the f O pin. For each mode, the operating cycle, data input format, data output format, and performance remain the same. Refer to Table 5 for a summary. DATAOUT SLOPE = 34 LSB 4 /K ABSOLUTE ERROR ( C) TEMPERATURE (K) TEMPERATURE ( C) F4 49 F5 Figure 4. Internal PTAT Digital Output vs Temperature Figure 5. Absolute Temperature Error Table 5. Serial Interface Timing Modes CONFIGURATION SOURCE CONVERSION CYCLE CONTROL DATA OUTPUT CONTROL CONNECTION AND WAVEFORMS External, Single Cycle External CS and CS and Figures 6, 7 Conversion External, 3-Wire I/O External Figure 8 Internal, Single Cycle Internal CS CS Figures 9, Conversion Internal, 3-Wire I/O, Continuous Conversion Internal Continuous Internal Figure

21 Applications Information External Serial Clock, Single Cycle Operation This timing mode uses an external serial clock to shift out the conversion result and CS to monitor and control the state of the conversion cycle (see Figure 6). The external serial clock mode is selected during the powerup sequence and on each falling edge of CS. In order to enter and remain in the external mode of operation, must be driven LOW both at power up and on each CS falling edge. If is HIGH on the falling edge of CS, the device will switch to the internal mode. The serial data output pin () is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. While CS is LOW, EOC is output to the pin. EOC = while a conversion is in progress and EOC = if the conversion is complete and the device is in the sleep state. Independent of CS, the device automatically enters the sleep state once the conversion is complete; however, in order to reduce the power, CS must be HIGH. LTC49 When the device is in the sleep state, its conversion result is held in an internal static shift register. The device remains in the sleep state until the first rising edge of is seen while CS is LOW. The input data is then shifted in via the SDI pin on each rising edge of (including the first rising edge). The channel selection and converter configuration mode will be used for the following conversion cycle. If the input channel or converter configuration is changed during this I/O cycle, the new settings take effect on the conversion cycle following the data input/ output cycle. The output data is shifted out the pin on each falling edge of. This enables external circuitry to latch the output on the rising edge of. EOC can be latched on the first rising edge of and the last bit of the conversion result can be latched on the 3nd rising edge of. On the 3nd falling edge of, the device begins a new conversion and goes HIGH (EOC = ) indicating a conversion is in progress. At the conclusion of the data cycle, CS may remain LOW and EOC monitored as an end-of-conversion interrupt. µf.7v TO 5.5V V CC f O LTC49 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR.µF REFERENCE VOLTAGE.V TO V CC ANALOG INPUTS REF + REF CH CH CH CH3 COM SDI CS GND WIRE SPI INTERFACE CS (EXTERNAL) SDI DON'T CARE EN SGL ODD A A A EN IM FA FB SPD DON'T CARE EOC SIG MSB Hi-Z BIT 3 BIT 3 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT BIT BIT BIT 9 BIT 8 BIT 7 BIT CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION Figure 6. External Serial Clock, Single Cycle Operation 49 F6

22 LTC49 Applications Information Typically, CS remains LOW during the data output/input state. However, the data output state may be aborted by pulling CS HIGH any time between the st falling edge and the 3nd falling edge of (see Figure 7). On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. In order to program a new input channel, 8 clock pulses are required. If the data output sequence is aborted prior to the 8th falling edge of, the new input data is ignored and the previously selected input channel remains valid. If the rising edge of CS occurs after the 8th falling edge of, the new input channel is loaded and valid for the next conversion cycle. If CS goes high between the 8th falling edge and the 6th falling edge of, the new channel is still loaded, but the converter configuration remains unchanged. In order to program both the input channel and converter configuration, CS must go high after the 6th falling edge of (at this point all data has been shifted into the device). External Serial Clock, 3-Wire I/O This timing mode uses a 3-wire serial I/O interface. The conversion result is shifted out of the device by an externally generated serial clock () signal (see Figure 8). CS is permanently tied to ground, simplifying the user interface or isolation barrier. The external serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle typically concludes 4ms after V CC exceeds V. The level applied to at this time determines if is internally generated or externally applied. In order to enter the external mode, must be driven LOW prior to the end of the POR cycle. Since CS is tied LOW, the end-of-conversion (EOC) can be continuously monitored at the pin during the convert and sleep states. EOC may be used as an interrupt to an external controller. EOC = while the conversion is in progress and EOC = once the conversion is complete. µf.7v TO 5.5V V CC f O LTC49 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR.µF REFERENCE VOLTAGE.V TO V CC ANALOG INPUTS REF + REF CH CH CH CH3 COM SDI 3 CS 4 5 GND 6 4-WIRE SPI INTERFACE CS (EXTERNAL) SDI DON'T CARE EN SGL ODD A A A DON'T CARE EOC SIG MSB Hi-Z BIT 3 BIT 3 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION SLEEP 49 F7 Figure 7. External Serial Clock, Reduced Output Data Length and Valid Channel Selection