2 Basic Ladder Logic Programming

Transcription

1 2 asic Ladder Logic Programming Chapter Topics: asic ladder logic symbols Ladder logic diagram Ladder logic evaluati Start/stop logic OJECTIVES Up completi of this chapter, you will be able to: Understand basic ladder logic symbols Write ladder logic for simple applicatis Scenario: program with a lg scan time may not detect short-durati events. manufacturer of small gasoline engines had an intermittent problem the final assembly line. Sometimes, a defective engine would not be automatically removed from the line for repair at a kick-out stati. If an operator noticed a problem with an engine, he/she inserted a bolt into a certain hole in the engine carrier. proximity sensor before the kick-out stati sensed the presence of the bolt, and the PLC activated a pneumatic cylinder to push the carrier (and engine) the main cveyor and into the repair area. view of this stati is shown in Figure 2.1. Further investigati revealed that the durati of the pulse of the proximity sensor was approximately 3/4 secds. One PLC ctrolled all of the statis the assembly line and its ladder logic program was quite large. s indicated in the PLC status, the time to scan the ladder logic program was slightly less than 1 secd. Hence, it was very likely that a pulse from the proximity sensor could be undetected by the PLC processor. The proximity sensor could be at the start of the ladder scan, generate an pulse from a passing bolt in the carrier, and be at the start of the next ladder scan. Soluti: Logic to examine the proximity sensor is placed in a ladder logic routine that is executed every ½ secd. If the proximity sensor is detected to be, an internal coil is turned for at least 1.5 secds. The main PLC program is changed to examine this internal coil to determine when to activate the pneumatic cylinder and push a carrier the main cveyor. 17

2 18 asic Ladder Logic Programming Engine Carrier olt Repair rea Pneumatic Cylinder Main cveyor belts Note: Main cveyor is moving out of page Proximity sensor Figure 2.1. Kick-out stati. 2.1 INTRODUCTION Now that the PLC has been introduced, let us move to programming the PLC. The first, and still most popular programming language, is ladder logic. Using examples, the language is developed from the electromechanical relay system-wiring diagram. fter describing the basic symbols, they are combined into a ladder diagram. The subsequent secti details the process of scanning a program and accessing the physical inputs and outputs. Programming with the normally closed ctact is given particular attenti because it is often misapplied by novice programmers. To solidify these ccepts, the start/stop of a physical device is csidered. Start/stop is a very comm PLC applicati and occurs in many other ctexts. secti transitial ctacts and coils ccludes the chapter. 2.2 SIMPLE LDDER LOGIC Ladder logic is the primary programming language of programmable logic ctrollers. Since the PLC was developed to replace relay logic ctrol systems, it was ly natural that the initial language closely resembles the diagrams used to document the relay logic. y using this approach, the engineers and technicians using the early PLCs did not need retraining to understand the program. To introduce ladder logic programming simple switch circuits are cverted to relay logic and then to PLC ladder logic. In all of the ladder logic examples used in this chapter, tags (symbols) are used for all inputs, outputs, and internal memory in the examples to avoid having to deal with input/output addressing. This addressing, treated in Chapter 3, is generally different for each PLC manufacturer. Example 2.1. OR Circuit. Two switches labeled and are wired in parallel ctrolling a lamp as shown in Figure 2.2a. Implement this functi as PLC ladder logic where the two switches are separate inputs. Soluti. The switch circuit acti is described as, The lamp is when switch is (closed) or switch is (closed). ll possible combinatis of the two switches and the csequent lamp acti is shown as a truth table in Figure 2.2b. To implement this functi using relays, the switches and are not cnected to the lamp directly, but are cnected to relay coils labeled R and R whose normally-open

3 2.2 SIMPLE LDDER LOGIC 19 Neutral (a) (b) Figure 2.2. Parallel switch circuit: (a) switch circuit; (b) truth table. (NO) ctacts ctrol a relay coil, LR, whose ctacts ctrol the lamp, Figure 2.3a. The switches, and, are the inputs to the circuit. When either switch or is closed, the correspding relay coil R or R is energized, closing a ctact and supplying power to the LR relay coil. The LR coil is energized, closing its ctact and powering the lamp. The output (lamp in this case) is driven by the LR relay to provide voltage isolati from the relays implementing the logic. The switches, and, ctrol relay coils (R and R) to isolate the inputs from the logic. lso, with this arrangement, the e switch cnecti to an input relay can be used multiple times in the logic. typical industrial ctrol relay can have up to 12 poles, or sets of ctacts, per coil. For example, if the R relay has six poles (ly e shown in Figure 2.3a), then the other five poles are available for use in the relay logic without requiring five other cnectis to switch. efore the PLC was developed, engineers had already developed a graphical electrical circuit shorthand notati for the relay circuit of Figure 2.3a. This notati was called a relay ladder logic diagram, shown in Figure 2.3b. The switches are shown as their usual symbol, the circles indicate the relay coils, and the NO relay ctacts are shown as the vertical parallel bars. The PLC ladder logic notati (Figure 2.3c) 1 is shortened from the relay wiring diagram to show ly the third line, the relay ctacts and the coil of the output relay. The PLC ladder logic notati assumes that the inputs (switches in this example) are cnected to discrete input channels (equivalent to the relay coils R and R in Figure 2.3b). lso, the actual output (lamp) is cnected to a discrete output channel (equivalent to the normally open ctacts of LR in Figure 2.3b) ctrolled by the coil. The label shown above a ctact symbol is not the ctact label, but the ctrol for the coil that drives the ctact. lso, the output for the rung occurs the extreme right side of the rung and power is assumed to flow from left to right. The PLC ladder logic rung is interpreted as: When input (switch) is OR input (switch) is then the lamp is, which is the same as the statement describing the switch circuit in Figure 2.2a. Notice that the original descripti of the switch circuit in Figure 2.2a, The lamp is when switch is or switch is. translates into a relay circuit described as 1 The ctact and coil symbols shown in Figure 2.3c are for the CtrolLogix PLC. Other vendors use ctact and coil symbols like those in Figure 2.3b.

4 20 asic Ladder Logic Programming Neutral R R LR (a) 120v R Neutral R R LR R LR W (b) (c) Figure 2.3. Parallel switch relay and ladder logic circuits: (a) equivalent relay circuit; (b) equivalent relay ladder logic circuit; (c) equivalent PLC ladder logic. parallel cnecti of normally-open ctacts, which describes the PLC ladder logic in Figure 2.3c. Example 2.2. ND Circuit. Two switches labeled and are wired in series ctrolling a lamp as shown in Figure 2.4a. Implement this functi as PLC ladder logic where the two switches are separate inputs.

5 2.2 SIMPLE LDDER LOGIC 21 Neutral (a) (b) Figure 2.4. Series switch circuit: (a) switch circuit; (b) truth table. Soluti. The switch circuit acti is described as, The lamp is when switch is (closed) and switch is (closed). ll possible combinatis of the two switches and the csequent lamp acti is shown as a truth table in Figure 2.4b. To implement this functi using relays, the ly change from Example 2.1 is to wire the normally-open ctacts of ctrol relays R and R in series to ctrol the light, Figure 2.5a. The wiring of switches and and the wiring of the lamp do not change. The relay circuit diagram, shown in Figure 2.5b is different from Figure 2.3b ly in the third line. s for example 2.1, the PLC ladder logic notati (Figure 2.5c) is shortened from the relay wiring diagram to show ly the third line, the relay ctacts and the coil of the output relay. The PLC ladder logic rung is interpreted as: When input (switch) is ND input (switch) is then the lamp is. Notice that the original descripti of the switch circuit in Figure 2.4a, The lamp is when switch is and switch is. translates into a relay circuit described as series cnecti of normally-open ctacts, which describes the PLC ladder logic in Figure 2.5c. Example 2.3. s a third example, csider the implementati of a logical NOT functi. Suppose a lamp needs to be turned when switch is (closed) and switch is (open). Implement this functi as PLC ladder logic where the two switches are separate inputs. Soluti. Figure 2.6 shows the truth table, relay implementati and ladder logic for this example. The ly difference between the relay implementati in Figure 2.6b and Figure 2.5a is the wiring of the relay R ctacts. The logical NOT for switch is accomplished with the normally closed (NC) ctact of relay R. The PLC ladder logic rung in Figure 2.6c is different from Figure 2.5c ly in the secd ctact symbol. The PLC ladder logic is interpreted as: When input (switch) is (closed) and input (switch) is (open) then the lamp is. This particular example is impossible to implement with a combinati of ly two normally open switches and no relays. Notice that the original descripti of the Example 2.3, The lamp is when switch is and switch is. translates into a relay circuit described as series cnecti of a normally-open ctact and a normally-closed ctact, which describes the PLC ladder logic in Figure 2.6c. Summarizing these three examples, e should notice that key words in the descripti of the operati translate into certain aspects of the soluti:

6 22 asic Ladder Logic Programming Neutral R R LR (a) 120v R Neutral R R R LR LR W (b) (c) Figure 2.5. Series switch relay and ladder logic circuits: (a) equivalent relay circuit; (b) equivalent relay ladder logic circuit; (c) equivalent PLC ladder logic. and series cnecti of ctacts or parallel cnecti of ctacts normally-open ctact normally-closed ctact These ccepts are key to being able to understand and write ladder logic. To many people these ccepts appear strange and foreign at first. However, they will become more natural as e works problems. Ladder logic is a very visual and graphical language. It is very different from textual languages like C++, Fortran, asic, and Java. In ctrast, e can become proficient at ladder logic much quicker than with textual languages.

7 2.3 SIC LDDER LOGIC SYMOLS 23 (a) Neutral R (b) R LR 120v Neutral (c) Figure 2.6. NOT functi ladder logic circuits; (a) truth table; (b) equivalent relay circuit; (c) equivalent PLC ladder logic. 2.3 SIC LDDER LOGIC SYMOLS t this point, e should start interpreting ladder logic directly and not think of its implementati with relays. s introduced by the examples in the previous secti, the basic ladder logic symbols are Normally open (NO) ctact. Passes power () if is (closed). Normally closed (NC) ctact. Passes power () if is (open). Output or coil. If any left-to-right path of ctacts passes power, the output is energized. If there is no ctinuous left-to-right path of ctacts passing power, is de-energized.

8 24 asic Ladder Logic Programming C Out1 D E F K Out2 G H Figure 2.7. Ladder logic diagram with basic instructis. These symbols are ladder logic instructis that are scanned (executed) by the PLC. In order to avoid cfusi, the ctact symbols should be equated with certain ccepts as follows: = = Closed = True = 1 = = Open = False = 0 This crucial point will be repeated later when the use of the NC ctact is clarified. Figure 2.7 is an example ladder logic diagram with the basic instructis. The first line (also called a rung) that determines output labeled Out1 is interpreted as follows: Out1 is if inputs,, and C are all, or if inputs and C are and input D is. For Out1 to be there must be a ctinuous electrical path through the ctacts. Every PLC manufacturer uses the ctact and coil symbols shown in the previous paragraph, though some vendors show the coil as a circle. There are other ctact and coil symbols, but there is no universal graphic representati for these other symbols amg PLC vendors. The IEC standard (IEC, 1993) has the most ctact and coil symbols and many manufacturers do not implement the full set of symbols. The industry trend is toward using the IEC (formerly IEC ) standard. However, this text emphasizes the llen-radley CtrolLogix implementati of IEC Since IEC is ly a voluntary standard, individual manufacturers have some freedom in the implementati. ecause of their widespread use, the llen-radley MicroLogix and SLC-500 ladder logic languages are also covered. The llen-radley basic ladder logic ctact symbols are Normally open (NO) ctact. Passes power () if is (closed). lso called XIC (examine If Closed). Normally closed (NC) ctact. Passes power () if is (open). lso called XIO (examine If Open).

9 2.3 SIC LDDER LOGIC SYMOLS 25 ONS OSR One-shot ctact. If cditis before this ctact change from to, this ctact passes power for ly e scan (CtrolLogix, PLC-5, and certain MicroLogix ly). It is analogous to the IEC positive transiti sensing ctact except that this ctact follows the ctact(s) whose transiti is being sensed. The is a storage oolean that retains the previous state of the ctact input (left side). One-shot rising ctact. If cditis before this ctact change from to, this ctact passes power for ly e scan (SLC-500 and certain MicroLogix ly). Must immediately precede an output coil. It is analogous to the IEC positive transiti sensing ctact except that this ctact follows the ctact(s) whose transiti is being sensed. The is a storage oolean that retains the previous state of the ctact input (left side). For the llen-radley PLCs, the basic ladder logic coil (output) symbols are Output or coil. If any left-to-right rung path passes power, is energized (). If there is no ctinuous left-to-right rung path passing power, the output is de-energized (). lso called OTE (OuTput Energize). L Latch coil. If any rung path passes power, is energized and remains energized, even when no rung path passes power. lso called OTL (OuTput Latch). U OSR One Shot Rising (O) Storage it <stor> (S) Output it <otag> OSF One Shot Falling (O) Storage it <stor> (S) Output it <otag> Unlatch coil. If any rung path passes power, is de-energized and remains de-energized, even when no rung path passes power. lso called OTU (OuTput Unlatch). One shot rising output. If cditis before this block change from to, the specified output bit is turned for e scan (CtrolLogix and CompactLogix ly). This is more appropriately a functi block because of its appearance. The storage bit retains the previous state of the block input. One shot falling output. If cditis before this block change from to, the specified output bit is turned for e scan (CtrolLogix and CompactLogix ly). This is more appropriately a functi block because of its appearance. The storage bit retains the previous state of the block input.

10 26 asic Ladder Logic Programming lert_5 L lert_5 U latches (turns ) lert_5 unlatches (turns ) lert_5 Figure 2.8. Latch and unlatch coil example. Comments about the basic instructis 1. The transiti sensing ctacts and coils are useful for initializati and detecting input transitis, for example, a push butt press. 2. The latch and unlatch coils are used in cjuncti with each other. Figure 2.8 is a short example using these two coils in cjuncti to ctrol a lamp. 3. Some manufacturers have a negated coil (Ericks, 2011) in which the output is de-energized if any left-to-right rung path passes power. The author discourages use of the negated coil for the following reas. In most systems the safe positi is e in which the output from the PLC is. Generally, ctacts (often called permissives) are placed in series with the coil, indicating multiple cditis must be satisfied before the output is allowed to be energized. With the negated coil the rung cditis must be satisfied to turn the output which is opposite to most safety ccepts. 2.4 LDDER LOGIC DIGRM n example PLC ladder logic diagram appears in Figure 2.9. The vertical lines the left and right are called the power rails. The ctacts are arranged horiztally between the power rails, hence the term rung. The ladder diagram in Figure 2.9 has three rungs. The arrangement is similar to a ladder e uses to climb to a roof. In additi, Figure 2.9 shows an example diagram like e would see if mitoring the running program in the PLC. The thick lines indicate ctinuity and the state (/) of the inputs and outputs is shown next to the tag. Regardless of the ctact symbol, if the ctact is closed (ctinuity through it), it is shown as thick lines. If the ctact is open, it is shown as thin lines. In a relay ladder diagram, power flows from left to right. In PLC ladder logic, there is no real power flow, but there still must be a ctinuous path through closed ctacts in order to energize an output. In Figure 2.9 the output the first rung is because the ctact for C is open, blocking ctinuity through the D and E ctacts. lso notice that the E input is, which means the NC ctact in the first rung is closed and the NO ctact in the secd rung is open. Figure 2.9 also introduces the ccept of functi block instructis. ny instructi that is not a ctact or a coil is called a functi block instructi because of its appearance in the ladder diagram. The most comm functi block instructis are timer, counter, comparis, and computati operatis. More advanced functi block instructis include sequencer, shift register, and first-in first-out operatis.

11 2.4 LDDER LOGIC DIGRM 27 Input (cditi) Instructis Output Instructis C Out1 D E F E K Out2 H E EN H DN Functi lock Instructi Functi lock Instructi Ctinuous path for logic ctinuity Power flows Figure 2.9. Sample ladder logic diagram. llen-radley groups the instructis into two classes: input instructis and output instructis. This distincti is made because in relay ladder logic, outputs were never cnected in series and always occurred the extreme right hand side of the rung. Ctacts always appeared the left side of coils and never the right side. To turn multiple outputs simultaneously, coils are cnected in parallel. This restricti was relaxed in CtroLogix and CompactLogix processors and outputs for these processors may be cnected in series. lso, ctacts can occur the right side of a coil as lg as a coil is the last element in the rung. This text avoids using a series cnecti of coils for two reass: 1. not all PLCs allow it, and 2. it is counterintuitive to maintenance persnel who often interpret ladder logic in the ctext of an electrical diagram. lso, in CtrolLogix and CompactLogix PLCs, all functi block instructis are input instructis because the ly output instructis are the coils. The llen-radley MicroLogix and SLC-500 have functi block output instructis (e.g., timer, counter, and

12 28 asic Ladder Logic Programming SS2 P4 LS3 PL2 Figure Soluti to Example 2.4. computati) which must be remembered when cstructing ladder logic programs for these PLCs. Example 2.4. Draw a ladder diagram that will cause the output, pilot light PL2, to be when selector switch SS2 is closed, push-butt P4 is closed and limit switch LS3 is open. (Note: no I/O addresses yet.) Soluti. The first questi to answer is What is the output? The output is PL2, so the coil labeled as PL2 is put the right side of the rung. Secdly, csider the type of cnecti of ctacts to use. Since all three switches must be in a certain positi to turn the pilot light, a series cnecti is needed. Thirdly, the type of ctact is determined by the switch positi to turn the pilot light: SS2 closed P4 closed LS3 open Putting all the pieces together, ly e rung of ladder logic is needed, as shown in Figure Design Tip The ccept of placing the output the rung first and then looking back to determine the input cditis is very important. ecause of the way the diagram is cfigured, e has a tendency to csider the input cditis first and then positi the output coil as the last step. s will be shown later, the ordinary coil referring to a particular output must ly occur ce in a ladder program. Csidering the output coil first and the cditis for which it is active () will avoid repeating output coils. Example 2.5. Draw a ladder diagram that is equivalent to the digital logic diagram in Figure 2.11, which is the same as the following descriptis. In words: Yis when ( is andis andcis) ordis oreis. oolean logic equati: Y C D E

13 2.4 LDDER LOGIC DIGRM 29 C D E Y Figure Digital logic for Example 2.5. Soluti. First, answer, What is the output? The output is Y, so the coil labeled as Y is put the right side of the rung. Secdly, csider the type of cnecti of ctacts to use. For this problem, there is more than e type of cnecti. The three inputs within the parentheses (the ND gate in Figure 2.11) are cnected with and, so a series cnecti is required for these three ctacts. The other two inputs (D and E) are cnected with the three series ctacts by or (the OR gate inputs), so a parallel cnecti is required. Thirdly, the type of ctact is determined by the input state that turns the output, Y: D E C Putting all the parts together, ly e rung of ladder logic is needed, as shown in Figure Suppose e changes the D ctact in Figure 2.12 to refer to Y, the output (shown as Figure 2.13). Is this legitimate? Yes, it is legitimate, though probably not something e would want to do for this example. Even in relay ladder logic, it is legal and there is no wiring short because the coil for relay Y and its NO ctact are not cnected. This ccept is called sealing or latching an output without using the set (or latch) coil instructi. In this example, it is not a good idea because ce Y is sealed, there is no provisi to turn it. Why? C Y D E Figure Soluti to Example 2.5.

14 30 asic Ladder Logic Programming C Y Y E Figure Output that appears as an input. There are some precautis to observe when programming in ladder logic: 1. DO NOT repeat normal output coils or latch/unlatch coils that refer to the same tag. To illustrate what happens when this is de, csider the ladder logic diagram in Figure This is the ladder of Figure 2.9, modified for this illustrati. Note that the coils for both the first and secd rung refer to Out1. When the first rung of the ladder is scanned, Out1 is turned. However, when the secd rung is scanned, Out1 is turned, overriding the logic in the first rung. If all of these cditis are needed to turn Out1, then they all should be placed in parallel, as in Figure In this illustrati, it was obvious there is a problem. Normally, when this problem occurs, the rungs are not adjacent, and it is not so obvious. Compounding the problem, not all PLC programming software checks for this situati. Therefore, the best way to prevent this problem is to csider the output coil first and then csider all of the cditis that drive that output. 2. Use the latch coil and unlatch coils together. If a latch coil refers to an output, there should also be an unlatch coil for that output. lso, for the same reas that C Out1 D E F E K Out1 H E EN H DN Figure Ladder with repeated output.

15 2.4 LDDER LOGIC DIGRM 31 C Out1 D E F E K H E EN H DN Figure Repeated output corrected. ordinary output coils should not be repeated, do not mix the latch/unlatch coils with an ordinary output coil that refers to the same output. 3. e careful when using the latch/unlatch coils to reference PLC physical outputs. If the system involves safety and a latch coil is used for a PLC physical output, simply interrupting the cditi the latch coil rung will not turn the physical output. ll of the cditis that prevent the device from being turned must also appear a rung with an unlatch coil output. For this reas, some companies forbid the use of the latch/unlatch coils. 4. Reverse power flow in the ctact matrix is not allowed. When electromechanical relays implement ladder logic, power can flow either way through the ctacts. For example, csider the ladder logic in Figure If implemented with electromechanical relays, power may flow right-to-left through the SS2 ctact. When solid state relays replaced electromechanical relays for ladder logic, power can flow ly e way (left-to-right) through the ctacts. This restricti was carried to PLC ladder logic. If the reverse power flow path is truly needed, then insert it as a separate path, where the power flows from left to right. The reverse power flow path in Figure 2.16 is added as a separate path in Figure ctually, e cannot program llen-radley PLCs with ladder logic shown in Figure One is not permitted to start a branch e row of ctacts and finish it another row of ctacts.

16 32 asic Ladder Logic Programming LS1 SS1 PS1 PL1 SS2 PS2 LS2 Reverse Power Flow Figure Reverse power flow in ladder logic. LS1 SS1 PS1 PL1 SS2 PS2 LS2 SS2 SS1 PS1 LS2 PS2 Figure Reverse power flow in ladder logic corrected. 2.5 PLC PROCCESSOR SCN Previously, the process that the PLC uses to scan the ladder logic has ly been implied. Now it will be discussed in detail. In additi to scanning the ladder logic, the PLC processor must also read the state of its physical inputs and set the state of the physical outputs. Historically, these three major tasks in a PLC processor scan are executed in the following order: Read the physical inputs Scan the ladder logic program Write the physical outputs The processor repeats these tasks as lg as it is running, as shown pictorially in Figure The time required to complete these three tasks is defined as the scan time and is typically millisecds, depending the length of the ladder logic program. For very large ladder logic programs, the scan time can be more than e secd. When this happens, the PLC program may miss transient events, especially if they are shorter than e secd. In this situati, the possible solutis are: 1. reak ladder logic into subroutines that are executed at a slower rate and execute the logic to detect the transient event every scan.

17 2.5 PLC PROCCESSOR SCN 33 Update Outputs Start Read Inputs Program (ladder logic) Executi Figure PLC processor scan. 2. Lengthen the time of the transient event so that it is lger than the maximum scan time. If the event is counted, both the time and time of the event must be lger than the scan time. counter must sense both values to work correctly. 3. Place the logic examining the transient in a ladder logic routine that is executed at a fixed time interval, smaller than the length of the transient event. 4. Partiti lg calculatis. For example, if calculating the soluti to an optimizati, do e iterati per scan cycle rather than execute the entire algorithm every scan. Depending the PLC processor, e or more of these solutis may be unavailable. Note that in the CtrolLogix processor, the reading of the physical inputs and writing of the physical outputs is not coordinated with the scanning of the ladder logic. The MicroLogix and SLC-500 processors follow the traditial scan method and that is described first. Examples 2.7 and 2.8 illustrate the differences between these two scan methods. Traditially, during the ladder logic program scan, changes in physical inputs cannot be sensed, nor can physical outputs be changed at the output module terminals. However, most llen-radley processors have an instructi that can read the current state of a physical input and another instructi that can immediately set the current state of a physical output, as shown in Figure However, using the immediate input/output instructi incurs a severe time penalty the program scan. For example, to scan e ctact in the ladder logic typically requires less than e microsecd. The time to execute an immediate input/output instructi typically requires 200 to 300 microsecds. Csequently, these instructis are used sparingly. nother way to view the processor scan is shown in Figure In this figure the state of the actual physical inputs is copied to a porti of the PLC memory, commly called the input image table. When the ladder logic is scanned, it examines the input image table to read the state of a physical input. When the ladder logic determines the state of a physical output, it writes to a porti of the PLC memory commly called the output image table. The output image may also be examined during the ladder logic scan. To update the physical outputs, the output image table ctents are copied to the physical outputs after the ladder logic is scanned.

18 34 asic Ladder Logic Programming Update Outputs Start Read Inputs Immediate Input (Read) Program (ladder logic) Executi Immediate Output (Update) Figure PLC processor scan with immediate input/output. Other Memory State of ctual Input Device Input Image (PLC Memory) Ladder Logic Program Runs Output Image (PLC Memory) State of ctual Output Device Figure lternate view of PLC processor scan. n actual PLC processor executes other tasks than the three listed above. t a minimum, it communicates with other devices and checks its own hardware for faults. These other tasks occur in the background and have some influence the scan time but are generally not csidered part of the scan time. Most PLC processors have a watchdog timer that mitors the scan time. If the processor scan time exceeds the watchdog timer time-out value, the processor halts ladder program executi and signals a fault. This type of fault usually indicates the presence of an infinite loop in the ladder program or too many interrupts to the ladder scan. The overall executi of the PLC processor scan is ctrolled by the processor mode. When the PLC processor is in the run mode, the physical inputs, physical outputs, and ladder logic are scanned as described previously. When the processor is in program mode (sometimes called stopped), the ladder logic is not scanned. Depending the particular PLC processor the physical inputs may be copied into the input image, but the physical outputs are disabled. Some processors have a test mode, where the physical inputs and ladder logic are scanned. The output image table is updated, but the physical outputs remain disabled. The ladder logic program can be evaluated in e of two ways. Most PLC processors scan in rung order, also called top-to-bottom scan or scan from the top. Some PLC