Reconfiguration Challenges & Design Techniques in Software Defined Radio

Transcription

1 Recfigurati Challenges & Design Techniques in Software Defined Radio M. S. Karpe 1, A. M. Lalge 2, S. U. Bhandari 3 Abstract The term Software Radio was coined by Joseph Mitola III to signal the shift from HW design dominated radio systems to systems where the major part of the functiality is defined in software. It creates a necessity of generic programmable hardware base that would allow software to enable various features. The ccept of Recfigurable computing allows the accelerati of computatial processes by using variable cfiguratis of specialized hardware. The FPGAs are opening a new door in digital processing envirments by providing Recfigurability at different granularity levels. Further, the recfigurati models reduce overheads present in traditial systems. Finally, the combinati of both digital signal processing devices such as DSP/GPPs and FPGAs can take advantage of their respective features. These platforms provide ways to propose architectures for optimized SDR executi platform, which may reduce the SDR device size, power csumpti and cost significantly while maintaining a high degree of design and functi switching flexibility. Keywords Software Defined Radio (SDR), FPGA, Dynamic partial recfigurati, Software Communicati Architecture (SCA). 1. Introducti Software Defined Radio (SDR) is the radio in which some or the entire physical layer functis are Software Defined [1]. The objective of developing SDR technology is to realize plural system standards a single hardware platform that is implemented mainly with high speed programmable devices. In SDR the hardware module is recfigured by the software module, which means that a given hardware platform is cverted into specific system standard or M. S. Karpe, Department of Electrics & telecommunicati, Pimpri Chinchwad College of engineering, Pune, India. A. M. Lalge, Department of Electrics & telecommunicati, Pimpri Chinchwad College of engineering, Pune, India. S. U. Bhandari, Department of Electrics & telecommunicati, Pimpri Chinchwad College of engineering, Pune, India. special communicati system depending up the changes in the software module. [2 As wireless communicati becomes more and more diverse, the need of software radio is getting strger. The reas that wireless devices are so inflexible is that they are generally implemented is Hardware. Csequently, frequent redesign is expensive and incvenient to the end users. So, the recfigurable SDR can be obtained with either a single device capable of delivering various services or with a radio that can communicate with devices providing complementary services. [3]. 2. Background & relevance In the late 1950s Gerald Estrin came up with the ccept of Recfigurable computing which allows the accelerati of computatial processes by using variable cfiguratis of specialized hardware modules in additi to a sequential processing unit. Since 80 s the Field Programmable Gate Array (FPGA) market growing rapidly with varied of applicati in different industries. The FPGA has great advantage of flexibility that comes from its programmable nature as compared to systems with applicati specific integrated circuits (ASICs).The prototyping of e or several applicatis can be de in different ways using a single FPGA as it incorporates memories, DSP in its architecture. Recfigurable computing is e of the techniques that fill the gap between hardware and software; it offers potentially much higher performance than software, with ability to maintain a higher level of flexibility than hardware [5]. This type of computing is based up Field Programmable Gate Arrays (FPGAs). It ctains an array of computatial elements whose functiality is determined through multiple SRAM cfigurati bits. Like software, the mapped circuit is flexible and can be changed over the lifetime of the system or even the lifetime of the applicati. These elements, also known as logic blocks, are cnected using a set of routing resources that are also programmable. [5]. 3. Literature review Recfigurability challenges a number of areas ranging from users, business and regulatory aspects 127

2 to radio resource/spectrum management and system level interactis. The technological challenges are not ly the enabling technologies necessary for the development of recfigurable terminals and base statis but also network and equipment architectures supporting Recfigurati, recfigurati management etc. [4]. Also, Recfigurati through the software download over the air (OTA) is the most ccerned issue to many researchers since its attractive ccept of dynamic recfigurati of SDR terminal can, not ly be user friendly in subscribers point of view but also effective for network providers [3]. The case studies reviewed here, have proposed the different architectures in order to improve various parameters such as size of the software download OTA, memory overhead, recfigurati time. The authors in [6] have proposed the architecture for GSM to EDGE recfigurati using FPGA-DSP platform. The paper proves the feasibility of dynamic partial recfigurati. The FPGA provides network switching by dynamically recfiguring ly from QPSK mapped Nyquist filter with to 8PSK mapped Nyquist filter. The case study presented by authors [7] utilized TV white space which were made unlicensed in November 2008 by FCC. The paper ccentrates DFE (Digital Frt End) module of SDR. The proposed SDR transmitter architecture is based single FPGA and it is ctrolled by GPP. It uses DRP with PR FPGA to support TV standards like 3GPP LTE, 3GPP WCDMA, IEEE e; IEEE n.While DRP with PR offers the functial recfigurati alg with programmable clock. Alg with recfigurati, its management is e of the crucial factors. The authors in [8] proposed global architecture called Flexible Radio Kernel. The architecture has PL (Protocol Layer) and R-HAL (Radio-Hardware Abstracti Layer). Former manages the recfigurati of MAC layer and later manages Platform recfigurati. The authors in [9] focused the structure of recfigurati facilitated by SCA standard. The paper includes simple AM/FM receiver that identify and receives either type of modulati. The modular applicatis of SCA are dynamically installed and uninstalled using CORBA middleware. This article addresses large-scale recfigurati through Domain Management (facilitated by SCA), specifically, waveform applicati management''. In this level of recfigurati, the waveform 128 applicatis being run as SCA applicatis in the domain are dynamically installed and uninstalled based the radio requirements. This approach reduces the hardware requirements of the radio (e.g. memory) but introduces latency. 4. Platform based design techniques The design techniques involve hybrid platforms with different types of recfiguratis required as per applicati. The techniques highlight the advantages of dynamic as well as partial recfigurati. Using FPGA and DSP DSP s and FPGA s provide the flexibility and the computatial power required to realize a Digital Frt End (DFE) of SDR [6]. FPGAs enable to take advantage of parallelism to achieve high performance with moderate power csumpti. Furthermore FPGAs can be recfigured in order to provide multi standard/service terminals. Figure 1: DSP/FPGA Sundance Platform As shown in figure 1 the DSP and FPGA are cnected through two Com- Ports, e dedicated to data transfers and the other dedicated to bit stream transfers i.e. for partial recfigurati. In order to manage partial recfigurati a CPLD is used to implement a cfigurati ctroller between the DSP and the FPGA. In partial dynamic recfigurati, ly from a Nyquist filter with QPSK mapping to Nyquist filter with 8PSK is de. The hardware/software partitiing of the modulati chains (Figure 2) that have been csidered for this study (QPSK to 8PSK) leads to the following decompositi. Software compents, which correspd to source coding simulati, data transfers and cfigurati transfers, are mapped to the DSP. The hardware compents, which are bits-to-symbol coding (mapping),

3 oversampling, filtering and IF transpositi, are implemented in the FPGA. Figure 2: Partial dynamic recfigurati a DSP/FPGA platform The bits-to-symbol coding compent needs to undergo partial dynamic recfigurati while other compents are comm to both modulati chains. The Virtex FPGA supports Colum based partial recfigurati. Table 1 presents the main characteristics of three scenarios. The first e does not implement recfigurati; both chains are implemented in the FPGA. The secd e uses dynamic recfigurati but does not take benefit of partial recfigurati (i.e., ly full recfigurati is performed). Finally, the last e uses dynamic with partial Recfigurati. For each soluti, the DSP memory overhead, the FPGA utilizati and the recfigurati time overhead are highlighted. Table 1: QPSK/8PSK implementati scenarios leads to nearly 50% reducti in the DSP memory overhead. In the case of partial recfigurati the DSP memory overhead is composed of e full bit stream and both partial bit streams (bits-to-symbol coding for the QPSK and the 8PSK modulatis respectively) to be compared with two full bit streams in the case of full recfigurati. Csidering recfigurati time overhead, partial recfigurati leads to 90% reducti of the cfigurati time, which is very important in order to guarantee services ctinuity. Hence for an executi using dynamic partial recfigurati of QPSK and then 8PSK modulatis the benefit is almost 50% in terms of recfigurati time. This benefit increases gradually when each time there is a new switching between both modulati chains. Using FPGA and GPP Partial Recfigurati (PR) is a method for Field Programmable Gate Array (FPGA) designs which allows multiple applicatis to time-share a porti of an FPGA while the rest of the device ctinues to operate unaffected. The paper [7] presents a technique named Dynamic Recfigurable Port (DRP), with PR based a single FPGA in order to dynamically change both functiality and also the clock frequency. Implemented Architecture More recently new wireless opportunities such as TV White Spaces, opens a new area where SDR can be applied effectively. DSP/FPGA modulati chains implementati DSP memory overhead with bit stream FPGA Utilizati Recfig urati time overhea d Without Recfigurati No 3180 Slices No With full Recfigurati With Partial Recfigurati 1600 Kbytes 960 Kbytes 1590 Slices 1590 Slices 130 ms 11 ms Between these solutis there is 50% reducti of the slice utilizati. This is normal in our case since with recfigurati a single chain is implemented at any time the FPGA. The memory overhead in DSP occurring due to bit streams is an important issue for embedded systems. The use of partial recfigurati 129 Figure 3: Implementati of SDR architecture to support three standards FPGA The secdary use of TV spectrum is unlikely to be driven by ly e standard and therefore there exists the opportunity to support multi-standards at (low power) community base statis and use e FPGA hardware platform to potentially support multiple standards from TV White Space standards (IEEE af, IEEE , 3GPP LTE-TDD).

4 Example architecture shown in figure 3 has been developed to support 3GPP LTE, 3GPP WCDMA, IEEE e and IEEE n standards. Two DCMs with DRP are employed: e is used to ctrol and cfigure the mapper RP, and the other is for the DUC RP. The mapper DCM uses the input clock of a 100 MHz crystal oscillator for the generati of three clock frequencies: 200 MHz for 400 MHz for 16-QAM and 600 MHz to serve 64-QAM modules. The data output by the mapper RP can then be fed to the transform RP operating at a clock frequency of 100 MHz for the WCDMA implementati, the spreader modules ctain the OVSF code generator with SFs from 4 to 512. Two simple dual port Block RAMs are used to bridge the clock domain boundary between the modulati processing compents and the DUC RP. The 256 MHz from the clock oscillator is chosen as the input clock for the DUC DCM compent so that by setting different integer multiplier and divisor values, the output frequencies of MHz, MHz and 240 MHz may be derived from this frequency correctly. Table 2: Hardware utilizati in terms of Slices Mapper Standards Utilizati without PR ( Slices ) 3GPP LTE 5 MHz Utilizati with PR ( Slices) switching and design flexibility. It uses fewer clock oscillator inputs are required compared to traditial, fixed functi FPGA design. Therefore, the proposed method could reduce the SDR device size, power csumpti and cost significantly, while maintaining a high degree of design and functi switching flexibility Using flexible radio kernel The aim of a flexible radio device is to offer recfigurable radio operati flexible radio is a very wide ccept. it encompasses any soluti for radio operati that can be modified without changing the physical system. [8] Proposed Global architecture: Figure 4 shows global FRK architecture. The Protocol Layer (PL) acts as a networking standard scheduler in FRK.. It stores all implemented MAC layers, and ctrols activati or inactivati of each MAC layers. The Radio Hardware Abstracti Layer (R-HAL) acts as an inter-face between the operati implementati and the upper layers, managing the recfigurati and the ctrol of the physical layer resources allocati. FRK is based the definiti of targets in the platform. A target is a type of processing units for which the cfigurati method is similar. Each platform is made of a collecti of targets, for which the R-HAL implements a Target Management Element (TaME), designed to manage cfigurati and executi the target. QPSK 3GPPWCDMA IEEE e 3.5 MHz IEEE e 5 MHz IEEE n 20 MHz Modulati OFDM Spreader In the paper all of the designs are implemented the Virtex -5 series LX110T device with Xilinx ISE 12.4 software suite versi. Table 2 gives the hardware resources utilizati of each of the modules without and with PR in terms of slices. There is approximately 20% reducti in slice utilizati using PR. As a result, this PR/DRP architecture could be viewed as providing a high degree of functi 130 Figure 4: FRK global architecture The off-line part is integrated in the R-HAL. It is designed to translate a generic applicati called a waveform into a platform executable called a Cfigurati Instance (CI). The R-HAL is designed to manage recfigurability in a flexible radio

5 platform. It offers to the PL and other possible layers an abstracted interface for applicati management. It manages the instantiati of multiple applicatis and the repartiti the different targets according to the platform capabilities. The aim of R-HAL is to manage the cfigurati of the platform following requests from the PL. Thus, the envirment allows easy integrati of heterogeneous processing units. Using SCA Architecture The software defined radio (SDR) has opened the doors for levels of radio recfigurati not possible through the use of more traditial radio design approaches. While most radios allow variati of parameters such as carrier frequency, an SDR enables large-scale recfigurati (e.g., changing to a different protocol type or MAC). This research explores automated, dynamic large-scale radio recfigurati through the implementati and characterizati of three alternative recfigurable radio designs. The SCA is a widely used SDR standard developed by the US Department of Defense. The paper [9] includes simple AM/FM receiver that identify and receives either type of modulati. The modular applicatis of SCA are dynamically installed and uninstalled using CORBA middleware. Two methods for system recfigurati are csidered. In the first method, the installati of SCA applicatis is variable during runtime. A hybrid method combining these approaches can be csidered, in which the radio anticipates the most immediately useful subset of available SCA applicatis. Design Approach: Reference design accepts a baseband signal that can be either FM or AM using large scale recfigurati. These receivers are capable of determining the modulati type of the signal and demodulating the signal appropriately. Case 1: Modular multi-mode receiver with dynamic Recfigurati (steady state): As shown in Figure 5, specifically the signal classifier compent is able to install/uninstall as well as cnect to/discnect from the AM and FM receiver compents during runtime. With these abilities, the signal classifier is able to manage the state of the AM and FM receiver applicatis so that ly the required receiver is installed at any given time. Figure 5: Modular multi-mode receiver In this method, whenever the cfigurati of the radio changes, any existing SCA applicati that is no lger needed can be uninstalled and discnected, and a new SCA applicati installed in its place. Using this method, ly SCA applicatis that are actively processing data are installed. This approach exhibits minimal Memory usage when ly e SCA applicati is installed at a time. The worstcase latency performance occurs for the extreme case in which the required SCA applicati must be installed and uninstalled every time a packet is sent or received. Case 2: Modular multi-mode receiver with dynamic Recfigurati (during recfigurati): Applicatis csidered likely to be used are kept installed until supplanted by other applicatis as measured using a likelihood-of-use metric. In this extended dynamic approach, waveforms are installed and uninstalled less frequently provided that more than e waveform can be installed at a time and data are routed to the appropriate installed waveform. In this design, ly e receiver SCA applicati is installed at any given time. When the radio switches operating modes, the existing receiver SCA applicati is uninstalled and the new receiver SCA applicati is installed in its place. Signal classificati is accomplished by calculating the variance of the magnitude of the baseband signal. Since the FM signal theoretically has a cstant envelope in the absence of noise and fading, if the variance is low, the signal is determined to be FM. Alternatively, the signal is determined to be AM. 5. Discussi As per discussed case studies, we can summaries that different platforms use different recfigurati techniques enlisted in Table III. The platforms provide recfigurati of modulati chain, applicati switching, and multi service and recfigurati management. 131

6 Sr. No. Published Year Table 3: Discussed Parameters Platform Used FPGA and DSP 2010 SCA 2011 FPGA and GPP FRK Applicati QPSK to 8PSK AM/FM switching 3GPP LTE, IEEE802.16e,,3GPP WCDMA, IEEE802.11n Recfigurati Management 6. Cclusis and Future Work As per the discussi, the platform comprising of FPGA and DSP offer two advantages. As DSP works as hardware accelerator for FPGA, increases the speed of recfigurable functiality. Also, FPGA due its partial recfigurati ability reduces size of software to be downloaded locally or over the Air (OTA) which in turn ctributes to solve the challenge mentied in[2]. In platform csist of FPGA and GPP, the FPGA supports the multiple TV white space standards. As the standards require different frequencies to operate, the authors presented an architecture which uses DRP with PR to recfigure clock alg with functiality. The GPP handles the user requirement and decides which partiti is to be recfigured. The Flexible Radio Kernel provides an envirment for easy recfigurati management. This platform can be employed where there is necessity for management of recfigurati. The SCA architecture facilitates different modular applicati to build single platform and to run it independently. The case study discusses an receiver architecture that receives either AM or FM depending variance using dynamic recfigurati.thus, Dynamic and Partial recfigurati is an interesting soluti to cquer the challenges in SDR recfigurati. References Recfigura ti Used Dynamic partial recfigurati Dynamic recfigurati DRP with Partial recfigurati Level Dependent [1] SDR forum SDRF Cognitive Radio Definitis Working Document SDRF-06-R-0011-V [2] V Jeyalakhmi and K Sankaranarayanan Challenges in Technology and Recfigurati of SDR A survey IETE Technical review, Vol. 25, No.1, Jan Feb 08. [3] Alok Shah Vanu, Inc. An Introducti to Software Radio White paper [4] Klaus Moessnera, Didier Bourseb, Dieter Greifendorfc, Joerg Stammenc Software radio and recfigurati management Computer Communicatis 26 (2003) [5] K. Compt, S. Hauck, Cfigurable Computing A Survey of System and Software, Northwestern University USA Technical Report, [6] J. P. Delahaye, G. Gogniat, C. Roland, P. Bomel software radio and dynamic Recfigurati a dsp/fpga platform IETR/Supelec - Campus de Rennes, Av. de la Boulais, BP [7] Ke He & Louise Crockett & Robert Stewart Dynamic Recfigurati Technologies Based FPGA in Software Defined Radio System J Sign Process Syst DOI /s [8] P.-H. Horrein et al. An envirment for (re)cfigurati and executi management of heterogeneous flexible radio platforms, Microprocess. Microsyst.(2012), [9] Andrew R. Cormier a, Carl B. Dietrich b,, Jeremy Price a, Jeffrey H. Reedb, Dynamic recfigurati of software defined radios using standard architectures, Physical Communicati 3 (2010) Mayuri Karpe received her B.E degree from Pune University in She is currently pursuing ME in VLSI and Embedded systems from P.C.C.O.E Pune University. She is currently working in LSI India Pvt. Ltd as Intern in DFT (Design For Testability) area. Archana Lalge received her B.E. degree from University of Pune in She is currently pursuing M.E in VLSI and Embedded Systems from P.C.C.O.E, Pune University. She has 7 years of teaching experience. Sheetal Bhandari is an assistant professor of electrics and telecommunicati engineering at Pimpri Chinchwad College of Engineering, University of Pune, India. She received her B.E. and M.E. degree from University of Pune in 1998 and 2006 respectively She has completed her PhD in the area of Recfigurable Computing in She is been teaching for about 8 years and has entrepreneurial stint of 4 years. Her academic focus is Microelectrics and VLSI Design. Her research interests include Partial Recfigurati and HW-SW Co-Design. 132