PI2EQX4432D 2.5 Gbps x2 Lane PCI Express Repeater/Equalizer with Signal Detect and Flow-Through Pinout

Transcription

1 Features Two High Speed PC Express lanes Supports PC Express data rates (2.5 Gbps) on each lane Adjustable Receiver Equalization nput Signal Level Detect & Output Squelch on all Channels Output De-emphasis = -3.5dB 00 Ohm Differential CML /O s Low Power (00mW per Channel) Standby Mode Power Down State V DD Operating Range:.8V +/-0.V Packaging (Pb-free & Green): 48-contact TQFN P2EQX4432D 2.5 Gbps x2 Lane PC Express Repeater/Equalizer with Signal Detect and Flow-Through Pinout Description Pericom Semiconductor s P2EQX4432D is a low power, PC Express compliant signal Re-Driver. The device provides programmable equalization, to optimize performance by reducing nter-symbol nterference (S). P2EQX4432D supports two 00 Ohm Differential CML data /O s between the Protocol ASC to a switch fabric, across a backplane, or extends the signals across other distant data pathways on the user s platform. The integrated equalization circuitry provides flexibility with signal integrity of the PC Express signal before the Re-Driver. Whereas the integrated de-emphasis circuitry provides flexibility with signal integrity of the PC Express signal after the Re- Driver. A low-level input signal detection and output squelch function is provided for all four channels. Each channel operates fully independantly. When a channel is enabled (EN_x=) and operating, that channels input signal level (on xl+/-) determines whether the output is enabled. f the input level of the channel falls below the active threshold level (Vth-) then the output driver switches off, and the pin is pulled to via a high impedance resistor. n addition to providing serial re-conditioning, Pericom's PEQX4432D also provides a power management Stand-by mode operated by the enable pins. Block Diagram Pin Description (Top View) Signal Detect CML xo+ SEL EQ_A SEL EQ_B SEL OL_A SEL OL_B SEL DE_A SEL DE_B EN_A EN_B EN_C EN_D xl+ xl SEL EQ_x EN_X Equalizer Limiting Amp Repeat 4 Times Power Management SEL OL_x SEL DE_x xo A+ A BO+ BO C+ C DO+ DO GND AO+ AO B+ B CO+ CO D+ D GND CLK+ CLK Clock Buffer CLKO+ CLKO EN_CLK CLK+ CLK SEL EQ_C SEL EQ_D SEL OL_C SEL OL_D SEL DE_C SEL DE_D CLKO+ CLKO REF EN_CLK REF

2 Pin Description Pin # Pin Name /O Description A+ 2 A- 36 AO+ O 35 AO- O 33 B+ 32 B- 4 BO+ O 5 BO- O 7 C+ 8 C- 30 CO+ O 29 CO- O 27 D+ 26 D- 0 DO+ O DO- O 4, 40, 39, 38 43, 42, 20, 2 47, 46, 6, 7 45, 44, 8, 9 4, 5 22, 23 EN_[A, B, C, D] SEL DE_ [A:D] SEL EQ_ [A:D] SEL OL_ [A:D] CLK+, CLK CLKO, CLKO 3 EN_CLK O P2EQX4432D Positive CML nput Channel A with internal 50 Ohm pull down during normal operation (EN_A = ). When EN_A = 0, this pin is a high-impedance. Negative CML nput Channel A with internal 50 Ohm pull down during normal operation (EN_A = ). When EN_A =0, this pin is a high-impedance. Positive CML Output Channel A internal 50 Ohm pull up during normal operation and 2KΩ pull up otherwise. Negative CML Output Channel A with internal 50 Ohm pull up during normal operation and 2K-ohm pull up otherwise. Posite CML nput Channel B with internal 50 Ohm pull down during normal operation (EN_B = ). When EN_B = 0, this pin is a high-impedance. Negative CML nput Channel B with internal 50 Ohm pull down during normal operation (EN_B = ). When EN_B = 0, this pin is a high-impedance. Positive CML Output Channel B with internal 50 Ohm pull up during normal operation Negative CMLOutput Channel B with internal 50 Ohm pull up during normal operation Positive CML nput Channel C with internal 50 Ohm pull down during normal operation (EN_C = ). When EN_C = 0, this pin is a high-impedance. Negative CML nput Channel C with internal 50 Ohm pull down during normal operation (EN_C = ). When EN_C = 0, this pin is a high-impedance. Positive CMLOutput Channel C with internal 50 Ohm pull up during normal operation and 2K-ohm pull up otherwise. Negative CMLOutput Channel C with internal 50 Ohm pull up during normal operation Positive CML nput Channel D with internal 50 Ohm pull down during normal operation (EN_D = ). When EN_D = 0, this pin is a high-impedance. Negative CML nput Channel D with internal 50 Ohm pull down during normal operation (EN_D = ). When EN_D = 0, this pin is a high-impedance. Positive CML Output Channel D with internal 50 Ohm pull up during normal operation Negative CML Output Channel D with internal 50Ω pull up during normal operation EN_[A:D] is a channel enable pin with internal 50k Ohm pull-up resistor. ALVCMOS high provides normal operation. ALVCMOS low selects a low power down mode. Output De Emphasis configuration input for channels A, B, C and D, with internal 50k Ohm pull up.refer to table for modes. Equalizer configuration input for channels A, B, C and D, with internal 50k Ohm pull-up. Refer to table for modes. Output Level configuration input for channels A, B, C, and D, with internal 50k Ohm pull up. Refer to table for modes. Differential input reference clock, typically 00MHz Differential reference clock output Enable Clock input with 50K Ohm pull-up. When EN_CLK is LVCMOS high level, the clock output operates normally. When EN_CLK = low, the clock outputs are turned off for power savings. A clock is not required bt the data channels for operation. 2

3 P2EQX4432D 24 REF Connect to 475-Ohm resistor to ground when the reference clock is used. Otherwise do not connect. 3, 6, 9, 2, 28, 3, 34, 37, 48 PWR.8V Supply Voltage 25, Center Pad GND PWR Supply Ground, Center pad must be connected Output Swing Control SEL OL_[A:D] Output Swing 0 x.2x Output De-emphasis Adjustment SEL DE_[A:D] De-emphasis 0 0dB 3.5dB Equalizer Selection SEL EQ_[A:D] Compliance Channel 0 GHz GHz Maximum Ratings (Above which useful life may be impaired. For user guide lines, not tested.) Storage Temperature C to +50 C Supply Voltage to Ground Potential V to +2.5V DC SG Voltage V to V DD +0.5V Current Output...-25mA to +25mA Power Dissipation Continous mW Operating Temperature... 0 to +70 C Note: Stresses greater than those listed under MAX MUM RAT- NGS may cause permanent damage to the de vice. This is a stress rating only and func tion al op er a tion of the device at these or any other conditions above those indicated in the operational sections of this spec i fi ca tion is not implied. Exposure to absolute max i mum rating con di tions for extended periods may affect re liability. AC/DC Electrical Characteristics (V DD =.8 ±0.V) Ps Symbol Parameter Conditions Min. Typ. Max. Units Supply Power All Enables = LVCMOS High 0. All Enables = LVCMOS Low 0.6 Latency From input to output 2.0 ns CML Receiver nput RL RX Return Loss 50 MHz to.25 GHz 2 db V RX-DFFP-P Differential nput Peak-topeak Voltage V V RX-CM-ACP AC Peak Common Mode nput Voltage 50 mv V TH - Signal Detect Threshold EN_x = High mv Z RX-DFF-DC DC Differential nput mpedance Ω Z RX-DC DC nput mpedance Equalization J RS Residual Jitter (,2) Total Jitter 0.3 Deterministic jitter 0.2 Ulp-p J RM Random Jitter (,2).5 psrms Notes. K28.7 pattern is applied differentially at point A as shown in Figure. 2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (4. RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter. Signal source is a K28.5 ± pattern ( ) for the deterministic jitter test and K28.7 (00000) or equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure or its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. Jitter is measured at 0V at point C of Figure. W 3

4 P2EQX4432D FR4 Signal Source A B Pericom Re Driver C SmA Connector 30N SmA Connector n Out Figure. Test Condition Referenced in the Electrical Characteristic Table AC/DC Electrical Characteristics (TA = 0 to 70 C) Symbol Parameter Conditions Min. Typ. Max. Units CML Transmitter Output (00Ω differential) V DFFP Output Voltage Swing Differential Swing V TX-D+ - V TX-D mvp-p V TX-C Common-Mode Voltage V TX-D+ + V TX-D- / 2 V DD t F, t R Transition Time 20% to 80% () 50 ps Z OUT Output resistance Single ended Ω Z TX-DFF-DC DC Differential TX mpedance Ω C TX AC Coupling Capacitor nf V TX-DFFP-P Differential Peak-to-peak Ouput Voltage V TX-DFFP-P = 2 * V TX-D+ - V TX-D V LVCMOS Control Pins V H nput High Voltage 0.65 V DD V DD V L nput Low Voltage 0.35 V DD V H nput High Current 250 L nput Low Current 500 μa 4

5 P2EQX4432D AC Switching Characteristics for Clock Buffer (V DD =.8 ±0.V, AV DD =.8 ±0.V) (3) Symbol Parameters Min Max. Units Notes T rise / T fall Rise and Fall Time (measured between 0.75V to 0.525V) () ΔT rise / ps Rise and Fall Time Variation 75 ΔT fall V HGH Voltage High including overshoot V LOW Voltage Low including undershoot -200 mv V CROSS Absolute crossing point voltages ΔV CROSS Total Variation of Vcross over all edges 250 T DC Duty Cycle (input duty cycle = 50%) (2) % 2 Notes:. Measurement taken from Single Ended waveform. 2. Measurement taken from Differential waveform. 3. Test configuration is R S = 33.2Ω, Rp = 49.9Ω, and 2pF. Configuration Test Load Board Termination Figure 2. Configuration test load board termination Note: TLA and TLB are 3 transmission lines. 5

6 P2EQX4432D Packaging Mechanical: 48-contact TQFN (ZD48) DATE: 03/0/06 DESCRPTON: 48-Contact, Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZD (ZD48) DOCUMENT CONTROL #: PD-2045 REVSON: A Ordering nformation Ordering Number Package Code Package Description P2EQX4432DZDE ZD Pb-free & Green 48-contact TQFN Notes: Thermal characteristics can be found on the company web site at E = Pb-free & Green X suffix = Tape/Reel Pericom Semiconductor Corporation