Impact of Advanced Electronics for DoD Today

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1 Impact of Advanced Electronics for DoD Today Dr. Jay Lewis, Deputy Director DARPA Microsystems Technology Office (MTO) Electronics Resurgence Initiative Workshop Day 2 July 19, 2017 Reference herein to any specific commercial product, process, or service by trade name, trademark or other trade name, manufacturer or otherwise, does not necessarily constitute or imply endorsement by DARPA, the Defense Department or the U.S. government, and shall not be used for advertising or product endorsement purposes.

2 Leading-edge ASICs under development in MTO programs could deliver revolutionary capabilities to the warfighter Example ASIC* ACT** CLASIC CLASS DAHI ReImagine RF-FPGA SHIELD SPADE UPSIDE Capability Capture unprecedented volumes of RF data at 64Gs/sec for next-gen arrays Distinguish and classify RF signals for 180 hours on a cellphone battery Disguise and dynamically vary signals for inexpensive LPI/LPD comms 10x higher dynamic range arbitrary waveform generator for RF applications Collect different data in a single camera frame with a reconfigurable ROIC A software-defined front end that works for 20GHz or below Verify the authenticity of components at every point in the supply chain Build trusted circuits through split integration Enable real-time machine learning for object recognition on UAVs **Program acronyms are later slide *ASICs from MTO programs ASIC application specific integrated circuit RF radio frequency ROIC readout IC LPI/LPD low probability of intercept/detection DISTRIBUTION A. Approved for public release: distribution unlimited.

3 Leading-edge ASICs under development in MTO programs could deliver revolutionary capabilities to the warfighter Example ASIC* ACT** CLASIC CLASS DAHI ReImagine RF-FPGA SHIELD SPADE UPSIDE Capability Capture unprecedented volumes of RF data at 64Gs/sec for next-gen arrays Distinguish and classify RF signals for 180 hours on a cellphone battery Disguise and dynamically vary signals for inexpensive LPI/LPD comms 10x higher dynamic range arbitrary waveform generator for RF applications Collect different data in a single camera frame with a reconfigurable ROIC A software-defined front end that works for 20GHz or below Verify the authenticity of components at every point in the supply chain Build trusted circuits through split integration Enable real-time machine learning for object recognition on UAVs **Program acronyms on later slide *ASICs from MTO programs ASIC application specific integrated circuit RF radio frequency ROIC readout IC LPI/LPD low probability of intercept/detection DISTRIBUTION A. Approved for public release: distribution unlimited.

Leading-edge ASICs under development in MTO programs could deliver revolutionary capabilities to the warfighter Example ASIC* ACT CLASIC CLASS DAHI Capability ACT Capture unprecedented volumes of RF

vary signals for volumes inexpensive of RF LPI/LPD data at comms 64Gs/sec for next-gen 10x higher dynamic range arbitrary waveform arraysgenerator for RF applications ReImagine RF-FPGA SHIELD SPADE

SOI vs. 14nm FinFet Verify the authenticity of components at every point in the supply chain Build trusted circuits through split integration Area: 44.2mm 2 6.

4 Leading-edge ASICs under development in MTO programs could deliver revolutionary capabilities to the warfighter Example ASIC* ACT CLASIC CLASS DAHI Capability ACT Capture unprecedented volumes of RF data at 64Gs/sec for next-gen arrays Enable digital re-use for phased arrays Distinguish and classify RF signals for 180 hours on a cellphone battery Capture unprecedented Disguise and dynamically vary signals for volumes inexpensive of RF LPI/LPD data at comms 64Gs/sec for next-gen 10x higher dynamic range arbitrary waveform arraysgenerator for RF applications ReImagine RF-FPGA SHIELD SPADE UPSIDE Collect different data in a single camera frame Leverage with the a reconfigurable world s ROIC best digital beamforming system A software-defined front end that works for 20GHz or below 32nm SOI vs. 14nm FinFet Verify the authenticity of components at every point in the supply chain Build trusted circuits through split integration Area: 44.2mm 2 6.8mm 32nm Enable real-time machine learning for object recognition on UAVs 6.5mm 5mm 14nm 4mm 50% Less Area: 20mm 2 40% Less Power ASIC application specific integrated circuit *ASICs from MTO programs RF radio frequency DISTRIBUTION A. Approved for public release: distribution unlimited. ROIC readout IC LPI/LPD low probability of intercept/detection

cellphone battery electronic components Disguise and dynamically vary signals for Tag inexpensive electronics LPI/LPD at low comms cost with an encrypted 10x higher dynamic range arbitrary waveform

5 Leading-edge ASICs under development in MTO programs could deliver revolutionary capabilities to the warfighter Example ASIC* ACT CLASIC CLASS DAHI ReImagine RF-FPGA SHIELD SPADE UPSIDE Capability Capture Microscopic unprecedented volumes of RF data at 64Gs/sec for next-gen arrays SHIELD dielet Ensure the authenticity of genuine military Distinguish and classify RF signals for 180 hours on a cellphone battery electronic components Disguise and dynamically vary signals for Tag inexpensive electronics LPI/LPD at low comms cost with an encrypted 10x higher dynamic range arbitrary waveform 100µm generator x 100µm for ASIC RF applications Collect different data in a single camera frame Personalization with a reconfigurable of ROIC millions of die at waferscale A software-defined front end that works for 20GHz or below 14nm FinFet Verify the authenticity of components at every point in the supply chain Build trusted circuits through split integration 100 µm Full AES encryption ~30 µm x 30 µm Enable real-time machine learning for object recognition on UAVs 100 µm ASIC application specific integrated circuit *ASICs from MTO programs RF radio frequency SHIELD ROIC readout IC LPI/LPD low probability of intercept/detection DISTRIBUTION A. Approved for public release: distribution unlimited.

reconfigurable ROIC Disguise and dynamically vary signals for Simultaneously inexpensive LPI/LPD collect comms diverse data types from 10x higher dynamic range arbitrary waveform multiple generator

for 20GHz or below 14nm CMOS Verify the authenticity of components at every point in the supply chain SOA digital ROIC pixel layout using 65 nm CMOS Build trusted circuits through split integration

6 Leading-edge ASICs under development in MTO programs could deliver revolutionary capabilities to the warfighter Example ASIC* ACT CLASIC CLASS DAHI ReImagine RF-FPGA SHIELD SPADE UPSIDE Capability Capture unprecedented volumes of RF data at 64Gs/sec for next-gen arrays Achieve full battlespace awareness with a single Distinguish and classify RF signals for 180 hours on a cellphone battery reconfigurable ROIC Disguise and dynamically vary signals for Simultaneously inexpensive LPI/LPD collect comms diverse data types from 10x higher dynamic range arbitrary waveform multiple generator regions for of RF applications interest Collect different data in a single camera frame with a reconfigurable ROIC ADC with signal processing in every pixel A software-defined front end that works for 20GHz or below 14nm CMOS Verify the authenticity of components at every point in the supply chain SOA digital ROIC pixel layout using 65 nm CMOS Build trusted circuits through split integration Enable real-time machine learning for object recognition on UAVs 25 µm ~6 µm ~10 µm ReImagine 14 nm CMOS pixel with computation ASIC application specific integrated circuit *ASICs from MTO programs Images courtesy: MIT Lincoln Laboratory ROIC readout IC RF radio frequency LPI/LPD low probability of intercept/detection DISTRIBUTION A. Approved for public release: distribution unlimited.

7 Program Names ACT CLASIC CLASS DAHI ReImagine RF-FPGA SHIELD UPSIDE Arrays at Commercial Timescales Cognitive radio Low-energy signal Analysis Sensor Integrated Circuits Computational Leverage Against Surveillance Systems Dense Accessible Heterogeneous Integration Reconfigurable Imaging Radio Frequency Field Programmable Gate Array Supply Chain Hardware Integrity for Electronics Defense Unconventional Processing of Signals for Intelligent Data Exploitation DISTRIBUTION A. Approved for public release: distribution unlimited.

9 Ongoing FY18 Programs in Advanced Computing and Design Dr. William Chappell, Director DARPA Microsystems Technology Office (MTO) Electronics Resurgence Initiative Workshop Day 2 July 19, 2017 Reference herein to any specific commercial product, process, or service by trade name, trademark or other trade name, manufacturer or otherwise, does not necessarily constitute or imply endorsement by DARPA, the Defense Department or the U.S. government, and shall not be used for advertising or product endorsement purposes.

10 NATIONAL ELECTRONICS CAPABILITY $216 MILLION TOTAL (FY18) materials architectures designs $75 million Of New Funding (FY18) JUMP + Traditional Programs $141 million in Current Efforts (FY18)

11 Traditional Programs Currently Funded materials architectures designs JUMP Joint University Microelectronics Program CHIPS Common Heterogeneous Integration and IP Reuse Strategies HIVE Hierarchical Identify Verify Exploit JUMP + Traditional Programs L2M Lifelong Learning Machines N-ZERO - Near-Zero Power Radio Frequency Receivers CRAFT Circuit Realization at Faster Time Scales SSITH System Security Integrated Through Hardware and firmware

12 MTO Electronics Timeline /2015 N-ZERO Kickoff 4/2016 CRAFT Kickoff 6/2016 CHIPS Approved 8/22/2016 JUMP Approved 1/2017 L2M Approved 4/2017 HIVE Kickoff Today 4/2017 SSITH BAA Released Ultra Low Power Design Reduced Design Time Pseudolithic Design Broad University Support In Field Machine Learning Graph Processing Built in Security

13 Joint University Microelectronics Program (JUMP) Industry 40% 60% Predecessor Program STARnet 646 Graduate students 184 Faculty researchers 46 Universities Joint University Microelectronics Program (JUMP) 6,118 Research publications RF to THz Distributed Computing Cognitive Computing Intelligent Memory/Storage Advanced IC Architectures Devices/ Materials

Circuit Realization at Faster Time Scales (CRAFT) Chip Design and Fabrication Time (weeks) DoD (Today) CRAFT (Future) Driving a design methodology that can be used to quickly design flexible, high

14 Circuit Realization at Faster Time Scales (CRAFT) Chip Design and Fabrication Time (weeks) DoD (Today) CRAFT (Future) Driving a design methodology that can be used to quickly design flexible, high performance custom integrated circuits using leading-edge CMOS technology while driving DoD to use the best commercial fabrication and design practices Sharply reduce barriers to DoD use of leading-edge custom integrated circuits (ICs) for orders-of-magnitude higher performance at low power for DoD systems.

15 N-ZERO passive sensor wake-up Continuous operation and near-zero power processing Persistent sensing with greatly extended lifetime and reduced cost Multiple sensing modalities with sensor fusion Lifetime (Days) Unattended Ground Sensors Battery leakage, active processing and N-ZERO wake-up Battery drainage by active wakeup circuitry 10 yrs. 1 yr. 1 mo Event Activity (% of Time) Devices are off (zero power consumption) yet continually alert.

16 Acoustic Sensor Wake-up Acoustic Signal Identify Sound of Interest + Noise Wake-up to generator and truck at > 5m with 12 nw of power consumption S. Jeong, et al. "21.6 A 12nW always-on acoustic sensing and object recognition microsystem using frequency-domain feature extraction and SVM classification." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017.

Hierarchical identify Verify Exploit (HIVE) Enabling the DoD to perform graph analytics at the edge of the battlefield and not rely on datacenters back in the United States; providing greater

17 Hierarchical identify Verify Exploit (HIVE) Enabling the DoD to perform graph analytics at the edge of the battlefield and not rely on datacenters back in the United States; providing greater situational awareness in addition to the ability to do real time sensor fusion and exploitation at the lowest echelons Next-generation server processor designed to find patterns in streaming data sets by using graph analytics

HIVE: An example of blending commercial and DoD interests TA 3:

Cyber security TA 2: Graph analytics toolkits (ref: Tensorflow, CUDA)

Accelerators Memory Scaling TA 1: Graph analytics accelerator (ref:

Identify/Develop hardware accelerators for each building block Create

Develop bus architectures to avoid congestion in data movement

18 HIVE: An example of blending commercial and DoD interests TA 3: Evaluator (evaluation framework x improvement) Northrop Grumman Cyber security TA 2: Graph analytics toolkits (ref: Tensorflow, CUDA) Georgia Tech Pacific Northwest Graph Software What should be accelerated? Define graph primitives Create data format model Define data flow model Accelerators Memory Scaling TA 1: Graph analytics accelerator (ref: TPU, GPU) Intel Qualcomm Graph Hardware How should it be accelerated? Identify/Develop hardware accelerators for each building block Create memory controller which optimizes data movement based on sparse mapping Develop bus architectures to avoid congestion in data movement DISTRIBUTION A. Approved for public release: distribution unlimited. CUDA compute unified device architecture TPU tensor processing unit GPU graphics processing unit

Lifelong Learning Machines (L2M) Continual Learning

during execution in the field Fundamentally new

19 Lifelong Learning Machines (L2M) Continual Learning Mechanisms Pursuing approaches for biologicallyinspired artificial intelligence utilizing flexible models to continue adapting during execution in the field Fundamentally new machine learning mechanisms for machines that learn continuously as they operate

Cortical Processor results Learn Architecture

recurrence Results Found optimal result 278x

accuracy than the hand designed (Neverova et.al.

architecture via hyper-parameters and finds

learning picture elements and relationships

20 Cortical Processor results Learn Architecture Dense Captioning Determine Optimal Fusion Architecture 21 classes, 3 modalities (ChaLearn, gesture) Requires localization and recurrence Results Found optimal result 278x faster than grid search method* Slightly higher accuracy than the hand designed (Neverova et.al. 2015) *12 iterations vs ~3300 System modifies architecture via hyper-parameters and finds best fusion processing paradigm Context: learning picture elements and relationships instead of whole image captioning SRI (Chai) Adaptive Architectures DISTRIBUTION A. Approved for public release: distribution unlimited. Stanford (Li) Context Sensitivity

Cortical Processor results Collaborative

Classification error: Set 1 Pedestrians and

Predicted Location Each network sees some of

world Stanford-UTK (Savarese) Collaborative

Approved for public release: distribution

21 Cortical Processor results Collaborative Machine Intelligence Predict Motion using Social LSTM Mitigating Catastrophic Forgetting Algorithmic Solutions Classification error: Set 1 Pedestrians and bikers Set 2 Skateboarders and cars Multiple Interacting Neural Networks Modeled Predictions Average Error vs. Predicted Location Each network sees some of others: interacts intelligently with dynamic world Stanford-UTK (Savarese) Collaborative Machine Intelligence DISTRIBUTION A. Approved for public release: distribution unlimited. First steps toward solving catastrophic forgetting Stanford-UTK (Savarese) Lifelong Learning

Common Heterogeneous Integration and IP Reuse Strategies

design tools and integration standards required to

leverage the best of the DoD and commercial designs and

22 Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) Market IP Proprietary IP 6 12 Weeks Developing the design tools and integration standards required to demonstrate modular integrated circuit (IC) designs that leverage the best of the DoD and commercial designs and technology Integrate CHIPS enables rapid integration of modular circuits at the die level

-10-20 -30-40 -50-60 -70-80 -90 0 FCLK_15 GHz, FCW_771_clk_ttune_128_dem_en_0 0 1 2 3 4 5 6 7

(Dec 2015): Si (45nm), InP (TF5 HBT), GaN (GaN20 HEMT) HBT Array - Beta at 1mA 80 60 40 Beta_812_@1mA

Beta_872_@1mA Beta_873_@1mA Beta_874_@1mA Beta_875_@1mA High foundry integration yields; test

94% HIC yield 98% HBT post-integration R2C3M0 R3C4M0 R4C3M0 R5C4M0 R2C3M0 R3C4M0 R4C3M0 R5C4M0 R2C3M0

R5C4M0 AR_2 AR_2A AR_1 AR_1A AR_1B HIC Redundancy: None HIC Redundancy: 2x Relative Amplitude (db)

23 FCLK_15 GHz, FCW_771_clk_ttune_128_dem_en_ Frequency (Hz) 10 9 Predecessor is DAHI 300mm diameter Si CMOS wafer (45nm node) DAHI integration (Dec 2015): Si (45nm), InP (TF5 HBT), GaN (GaN20 HEMT) HBT Array - Beta at 1mA Beta_812_@1mA Beta_813_@1mA Beta_814_@1mA Beta_815_@1mA Beta_862_@1mA Beta_863_@1mA Beta_864_@1mA Beta_865_@1mA Beta_872_@1mA Beta_873_@1mA Beta_874_@1mA Beta_875_@1mA High foundry integration yields; test vehicles fully functional DAC with very low digital noise (-70dBc) % HIC yield 98% HBT post-integration R2C3M0 R3C4M0 R4C3M0 R5C4M0 R2C3M0 R3C4M0 R4C3M0 R5C4M0 R2C3M0 R3C4M0 R4C3M0 R5C4M0 R2C3M1 R3C4M1 R4C3M1 R5C4M1 R2C3M0 R3C4M0 R4C3M0 R5C4M0 R2C3M0 R3C4M0 R4C3M0 R5C4M0 AR_2 AR_2A AR_1 AR_1A AR_1B HIC Redundancy: None HIC Redundancy: 2x Relative Amplitude (db) Successful testing identified optimal S/H circuit for ADC (>65dB 2GHz) DAHI Diverse Accessible Heterogeneous Integration Sources: DARPA, Northrop Grumman

Interface standards: Too many? Not enough? How to compare? MonoLithic PCB 1.00E+11 1.

24 Interface standards: Too many? Not enough? How to compare? MonoLithic PCB 1.00E E+10 What standards will allow CHIPS to bridge the gap? 1.00E+09 GGGGGGGG/mmmm EEEEeerrggyy/bbbbbb BWD/EPB 1.00E E E E+05 WideIO HBM 32nm_SerDes Proprietary 65nm_SerDes Si Photonic Too many solutions can hinder wider adoption 28nm_SerDes 28nm_SerDes 1.00E+04 LVDS PCIe 1.00E E E E E E E+00 Interconnect Length (m) CHIPS challenge: make a usable interface standard Source: DARPA

25 Interface standards: Too many? Not enough? How to compare? 1.00E+11 MonoLithic PCB 1.00E E+09 CHIPS Convergence to a minimal set of standards is necessary GGGGGGGG/mmmm EEEEeerrggyy/bbbbbb BWD/EPB 1.00E E E E+05 WideIO HBM 32nm_SerDes Proprietary 65nm_SerDes Si Photonic 28nm_SerDes 28nm_SerDes 1.00E+04 LVDS PCIe 1.00E E E E E E E+00 Interconnect Length (m) CHIPS challenge: make a usable interface standard Source: DARPA

26 MTO Electronics Timeline /2015 N-ZERO Kickoff 4/2016 CRAFT Kickoff 6/2016 CHIPS Approved 8/22/2016 JUMP Approved 1/2017 L2M Approved 4/2017 HIVE Kickoff Today 4/2017 SSITH BAA Released Traditional Programs JUMP University Driven Page 3 Investments Industry Driven N-ZERO CRAFT HIVE L2M CHIPS SSITH

27 Workshop Summary: Linton Salmon Materials and Integration materials architectures designs JUMP + Traditional Programs

28 Workshop Summary: Tom Rondeau Wade Shen Architectures materials architectures designs JUMP + Traditional Programs

29 Workshop Summary: Andreas Olofsson Designs materials architectures designs JUMP + Traditional Programs

30 MTO Electronics Resurgence Initiative Timeline Launch, Learn, & Organize Summer of Listening Open Competition Complete Contracting 6/21: Industry Discussion 7/11: Defense Base Summit 7/18: 2-day workshop on Materials, Architectures, Designs 9/12: Proposals Requested (Expected) 4/20: Start Work Completed Happening Now Fall 2017 Spring months May Jun Jul Aug Sep Oct Nov Dec Jan Apr V V Defense Base Summit 2-day Workshop Proposals Requested Proposals Submitted Partners Selected Funding Released

31 Teaming Session Defense and National Needs (HIVE) (CRAFT) (Possible)

32 Advantest Cadence IBM Microsemi Qualcomm ST Research Allvia, Inc. Cold Logic Intel Microsoft Alphacore Esperanto Technologies Commercial Attendees Quantum Semiconductor Teledyne Intermolecular MonolithIC 3D QuickLogic Teradeep Analog Devices Ethaphase Intrinsix Moon RF2BITS Texas Instruments Applied Materials Fault Tolerant Technology Jariet Nanoshift Sage Design Automation TSMC ARM Ferric, Inc. Kryptos Solutions Novati Siemens Vista Ventures Astrileux Flex Innovation Kyndi Nuvotronics Avalanche Technology Silicon Storage Technologies Google MaXentric NVIDIA Silvaco Xilinx Bell Labs HP Mentor Graphics PARC SRI International BroadPak HRL Micron Photia Synopsys

33 University/Research Attendees AFRL Georgia Tech Portland State Arizona State Harvard Purdue ARL Berkeley National Lab MIT Naval Research Lab Sandia National Lab Stanford BRIDG NC State UC Berkeley Columbia University Northwestern UC Davis Cyclotron Road Notre Dame UC San Diego DRAPER Oak Ridge National Lab UC Santa Cruz University of Arkansas University of Illinois at Chicago University of Massachusetts University of Michigan University of Minnesota University of New Mexico University of Pennsylvania University of Texas at Dallas University of Texas at Dallas University of Washington USC Virginia Tech

34 Defense Industry Attendees BAE Boeing Leidos Lockheed Martin Northrop Grumman Raytheon Rockwell Collins

36 Teaming Session #1 11:00 am 12:30 pm Defense and National Needs (HIVE) (CRAFT) (Possible) Followed by: Lunch (12:30PM, Imperial Ballroom) Teaming Session #2 (2:00PM, Club Regent) Workshop Close (4:00PM)

37 Teaming Session #2 2:00 pm 4:00 pm Defense and National Needs (HIVE) (CRAFT) (Possible) The workshop will adjourn informally at 4:00pm. Thank you for attending.

A TECHNOLOGY-ENABLED NEW TRUST APPROACH

A TECHNOLOGY-ENABLED NEW TRUST APPROACH Dr. William Chappell Director, DARPA Microsystems Technology Office (MTO) The U.S. semiconductor landscape The U.S. military must have access to microelectronics