Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST

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1 JOURNAL OF ELECTRONIC TESTING: Theory and Applications 17, , 2001 c 2001 Kluwer Academic Publishers. Manufactured in The Netherlands. Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST F. AZAÏS, S. BERNARD, Y. BERTRAND AND M. RENOVELL Laboratoire d Informatique Robotique Microélectronique de Montpellier (LIRMM), Université de Montpellier II: Sciences et Techniques du Languedoc, 161, rue Ada Montpellier Cedex 5, France azais@lirmm.fr bernard@lirmm.fr bertrand@lirmm.fr renovell@lirmm.fr Received August 1, 2000; Revised October 1, 2000 Editor: J. Figueras Abstract. The histogram method is a very classical test technique for Analog to Digital Converters (ADCs), but only used for external testing because of the large amount of required hardware resources. This paper discusses the viability of a BIST implementation for this technique. An original approach is developed that permits to extract the ADC parameters with a reduced area overhead. This approach involves (i) the calculation of the parameters using approximations and (ii) the decomposition of the global test in a code-after-code test procedure. These two features allow a significant reduction of the required operative resources and memory dedicated to the storage of experimental data. In addition, the use of a piece-wise approximation for computing the ideal histogram also permits to minimize the memory dedicated to the storage of reference data. Keywords: analog and mixed-signal testing, ADC test, Built-In Self-Test (BIST) 1. Introduction The price of an increasing number of mixed-signal devices is presently being dominated by the cost of performing production testing. One important factor affecting this cost is the direct cost of the test equipment, although another factor is the indirect cost incurred when test development time becomes the critical step in the manufacture of new devices. The cost of mixed-signal testers is exceedingly high on account of their requirements for both digital and analog test equipment with very high-performance capabilities. This trend tends to augment with the advances in the area of mixed-signal Integrated Circuits (ICs). Faster and more complex mixed-signal testers with high performance on speed, precision, memory and noise are actually needed to meet ever more demanding test specifications. An attractive alternative to simplify the test equipment is to move some or all the tester functions onto the chip itself. The use of Built-In Self-Test (BIST) for high volume production of mixedsignal ICs is desirable to reduce the cost per chip during production testing by the manufacturers. In addition, it helps performing diagnosis in the field. For mixed signal ICs including both an ADC and a DAC, many of the proposed BIST techniques use an all-digital approach [2, 8, 9]. These approaches assume that a reconfiguration is performed in test mode such that the circuit appears all digital by connecting the analog output of the DAC to the input of the ADC, possibly via some analog block under test. It is clear that the viability of these techniques depend on a number of prerequisites such that the presence in the original circuit of both an ADC and a DAC. Another all-digital BIST approach [14 16] exploits the digital signal processing (DSP) capabilities to determine characteristic

2 256 Azaïs etal. parameters of the converters. Here again, it is clear that the technique is limited to ICs already containing a DSP on-chip. Finally, another interesting approach has been proposed more recently, which is based on a polynomial-fitting algorithm to implement DAC and ADC BIST [13]. Focusing now on mixed signal ICs including solely an ADC, only a limited number of BIST techniques have been proposed. An original approach is detailed in [1], which relies on a reconfiguration in test mode that creates oscillations in the circuit. Measurements on these oscillations guarantee some tests. Note that in this case, no generation of input stimulus is required. A more classical ADC BIST scheme implies the generation of an analog test stimulus and the digital processing of the ADC outputs. Solutions for on-chip analog test signal generation are given in [10]. Concerning the processing of ADC outputs, classical digital modules such as signature analyzers, simple adders or modulo 2 n adders may be used. However, these classical digital compression techniques have been found inadequate due to the possible misinterpretation of the ADC responses. In addition, it is to note that ADCs are preferably tested using a specification-oriented approach with the objective to determine parameters of interest such as offset, gain, non-linearity, signal-tonoise ratio. Classical digital compression techniques do not provide any information on these parameters. A BIST structure is proposed in [3] that partially overcomes this drawback since it permits to evaluate the converter linearity. Only the LSB is used for the determination of the linearity, the global functionality of the converter being tested with the comparison between the remaining bits and a counter clocked by the LSB. A very classical ADC test technique used to determine the offset, gain error and non-linearity is the histogram method [4, 7], and an interesting test approach has recently been reported [5]. The histogram method involves the application of a given analog signal to the ADC input and the record of the number of time each code appears on the ADC outputs. To achieve statistically satisfactory results, this technique requires a lot of samples even if deterministic sampling is used [6], e.g. for a 8-bit ADC, 67 K random or 4 K deterministic samples are usually needed. These recorded samples are then used with theoretical samples in a complex computation to determine offset, gain and non-linearity. The histogram technique is widely used for the external testing of ADCs but a histogram-based BIST technique with complete on-chip determination of the ADC parameters is generally not considered as a viable solution because of the huge amount of required additional circuitry. The authors have already proposed a BIST scheme for implementing the linear histogram technique [11, 12]. The proposed scheme takes advantage of the intrinsic properties of a linear input signal to reduce the circuitry of the ADC output analyzer. Obviously, the proposed scheme does not work with a sine-wave signal. However, it may be interesting to use a sine-wave signal in order to obtain dynamic specifications. Indeed, because a single linear ramp changes so slowly, ramp tests are considered to be static tests, even when the ADC is clocked at rated speed. This drawback can be overcome using a multi-cycle approach which consists in applying a triangle-wave with several cycles within the test interval. At very high frequencies, however, pure sinusoids are much easier to generate than pure linear triangles, so this multi-cycle approach is usually restricted to sinusoidal waves. The counterpart is of course that the analysis is more complicated than in the linear case. It is therefore the objective of this paper to investigate the viability of a histogrambased BIST approach in case of a sine-wave signal used as input test stimulus. Note that only the possibilities of on-chip output data processing are explored in this research, existing solutions for on-chip test signal generation being detailed in [10]. The paper is organized as follows. Section 2 gives some general definitions of the ADC parameters and presents the main features of the histogram test technique. Section 3 defines the general BIST scheme in the context of histogram-based testing. The minimization process of the required hardware resources is then detailed in Section 4. Finally, performances of the BIST scheme are discussed in Section Histogram-based Test of ADCs 2.1. ADC Parameters The specification of an ADC involves the determination of different parameters such as the offset, the gain, the differential and integral non-linearity. Although these are well-known parameters, it may be helpful to redefine here these parameters and relate them graphically to the transfer function of an ideal ADC. Such an ideal transfer function is illustrated in Fig. 1. The analog input voltage is quantized into a finite number of digital output codes over the full scale range (FS) of the converter. In a perfect converter,

3 Optimizing Sinusoidal Histogram Test 257 as a uniform displacement of all points of the transfer function as illustrated in Fig. 2(a). Gain Error is the deviation of the actual input voltage from the design input voltage for a full scale output code. Gain error may be expressed either in fractional LSB or in percentage of the full scale range. Such a gain error basically corresponds to a modification of the slope of the straight line symbolizing the transfer function as illustrated in Fig. 2(b). Fig. 1. Transfer function of an ideal ADC. each step has an equal size corresponding to one least significant bit (LSB), and the transfer function can be simply symbolized by a straight line joining every code transition. Offset Error is the deviation of the actual mean value from the design mean value of the required analog input voltage to set zero code out. Offset error may be expressed either in fractional LSB or in percentage of the full scale range. Such an offset error may be viewed Non-Linearity Errors correspond to the deviation of the actual transfer function from the ideal one. As illustrated in Fig. 2(c), a linearity error allows for one or more steps being greater or less than the ideal shown. Two parameters are actually defined to characterize the linearity of the converter. The Differential Non- Linearity (DNL) error corresponds to the deviation of the actual code width from the ideal one for each step. Such DNL errors can accumulate over a series of codes and cause a global deviation from the ideal linear transfer curve. These accumulated DNL errors form the Integral Non-Linearity (INL) error. DNL and INL errors are usually expressed in fractional LSB. Fig. 2. Transfer function of an ADC with (a) offset error, (b) gain error and (c) non-linearity errors.

4 258 Azaïs etal. Fig. 3. Sinusoidal histogram for an ideal ADC Histogram Test Technique The histogram (or code density) method is one of the most popular techniques in the industrial context for ADC testing. Given an analog input signal, the histogram shows how many times each different digital code word appears on the ADC outputs [7]. The analog input signal can be any wave whose amplitude distribution is known. Fig. 3 illustrates the histogram obtained with an ideal ADC using a sine wave as input signal. The code count is not uniform reflecting the variable slope of the sinusoidal input signal. In the context of ADC testing, the histogram is only an intermediate step to catch the ADC parameters. Processing the measured histogram of an ADC under test actually permits to obtain characterization data. Indeed, ADC errors modify the output code count and so impact the shape of the histogram. As a result, comparing the measured histogram to the ideal one and performing some calculations permit to evaluate the following parameters: offset, gain, DNL and INL. Details on the computations performed to extract these parameters from the histogram data will be given in Section Histogram-based BIST of ADCs From a general point of view, a complete BIST scheme for ADCs requires the definition of an analog sinewave generator and a digital output response analyzer. Solutions can be found in the literature for on-chip generation of a sine-wave signal [10]. Consequently, we focus here on the problem of defining the digital analyzer able to implement the histogram test technique. The straightforward implementation of the histogram test technique requires a number of hardware resources, both in terms of memory and operative resources. Indeed, the determination of the ADC parameters is based on a comparison between the experimental and reference histograms together with subsequent calculations. It is therefore necessary to store both the experimental and reference histograms, implying two memories of 2 n words for an n-bit converter. Then, complex computations have to be performed on these data to extract the parameters, implying the use of a DSP or a microprocessor. Finally, the complete process is managed by a control unit. Fig. 4 summarizes these different on-chip resources. 4. BIST Resource Optimization This section details the optimization process we propose for the different blocks of the digital analyzer in order to reduce the required hardware BIST circuitry. Indeed, it is clear that unless memory and DSP capabilities are already available on-chip, the direct implementation of the histogram test technique as described in the previous section is not viable because of the huge amount of additional circuitry Operative Unit In order to integrate the histogram test technique with a reasonable silicon area, the first point we consider concerns the calculations required to evaluate the ADC parameters, i.e. offset, gain, DNL and INL. Classically, these parameters are calculated using a DSP that permits computation of trigonometric functions. We want to investigate how it is possible to approximate the

5 Optimizing Sinusoidal Histogram Test 259 Fig. 4. General BIST scheme. original complex expressions by simpler ones, which contain only elementary operations such as addition, subtraction, multiplication or division. We detail in the following the new expressions we derive for the ADC characteristic parameters. Offset Calculation. We assume an input waveform slightly larger than the full scale range of the converter in order to ensure that all valid codes are exercised. For such clipped sinusoids, a common trigonometric procedure permits to evaluate the offset to useful accuracy using the counts for the two extreme codes H exp (1) and H exp (2 n ) of the experimental histogram. The original expression of the offset as defined in [7] is given by the following equation: Offset = FS 2 cos πhexp (1) cos πhexp (2 n ) cos πhexp (1) + cos πhexp (2 n ) where FS is to the full scale amplitude of the ADC and is the total number of samples. Manipulating this equation, we can re-express the offset as follows: Offset = FS 2 sin π(hexp (1) + Hexp (2n )) 2 sin π(hexp (1) H exp (2 n )) cos π(hexp (1) + H exp (2 n )) 2 cos π(hexp (1) H exp (2 n )) 2 Then it becomes: Offset = FS 2 tan π(hexp (1) + H exp (2 n )) 2 tan π(hexp (1) H exp (2 n )) 2 A first observation concerns the sum of the counts for the two extreme codes H exp (1) + H exp (2 n ). We can consider that this sum is almost a constant value even in case of an offset error. Indeed, a positive offset error causes a decrease of H exp (1) and an increase of H exp (2 n ), and conversely. These two variations nearly compensate each other when adding the counts for the two extreme codes. Consequently, our first approximation is to replace this experimental sum by a constant value derived from the reference histogram H exp (1) + H exp (2 n ) 2H ref (1), where H ref (1) is a known-value for a given number of bits n, number of samples and input amplitude A in. The offset can then be estimated by: Offset FS 2 tan πhref (1) tan π(hexp (1) H exp (2 n )) 2 To validate this approximation, we build up the histogram of an 8-bit converter using 8191 samples, an input sine-wave of different peak-to-peak amplitude values and we estimate the offset using the new expression. We then compare the resulting value to the one obtained using the original expression, for different offset values. Table 1 shows the error (in LSB) induced by the approximation in the various cases. It clearly appears that the larger the offset value to be measured, the larger the error. However, it also appears that the error depends on the amplitude of the input sine-wave. Hence, large offset values can be estimated with good accuracy, provided that the amplitude of the input sinewave is large enough. For example, an offset value as high as 3 LSB can be estimated with an error less than 0.05 LSB using an input sine-wave of 272 LSB peakto-peak amplitude. A second observation is that the difference between the counts for the two extreme codes

6 260 Azaïs etal. Table 1. Error on the offset estimation. Offset value to (Error on the offset estimation in LSB) be measured (in LSB) A in = 262 LSB A in = 266 LSB A in = 272 LSB H exp (1) H exp (2 n ) is very small relative to the total number of samples. Hence, using the common firstorder approximation tan(α) α for small values of α, we obtain: Offset FS 2 tan π Href (1) ( ) π(h exp (1) H exp (2 n )) 2 So finally, an estimate of the offset can be expressed as follows: Offset K (H exp (2 n ) H exp (1)) π tan FS 4 πhref (1) where K = is a constant value that can be pre-determined for a given converter under test. We obtain a simple expression in which the offset is proportional to the difference between the counts of the two extreme codes. Note that in case of an ideal converter, the offset value should be zero. Therefore, the offset error of the converter can be expressed in LSB by: Offset Error = 2n FS Offset Gain Calculation. A common technique to derive the gain is to estimate the amplitude of the input sinusoid as seen through the eyes of the ADC under test; the gain is then the ratio between this amplitude and the actual value of the input amplitude [7]: Gain = FS 2 Offset A in 2 cos πhexp (2 n ) where A in corresponds to the peak-to-peak amplitude of the input sine-wave. This expression implies calculating a cosine function, which is not trivial to realize on-chip. In addition, it depends on the offset value, implying any error on the offset determination will affect the gain determination. We propose an alternative approach to estimate the gain. Our solution stems from the following observation. The histogram obtained with a sine wave as input presents a relatively flat section in the center part. This flat section actually corresponds to the ADC outputs for the almost linear part of the input sinusoid. Hence, we can make an analogy with the histogram obtained using a ramp as input signal. In this case, all ADC output codes have the same probability and all bins are equal; the ADC gain is therefore simply given by the ratio between the reference and experimental counts for any of these codes [12]: Gain = Href (i) H exp (i) In case of a sine wave as input signal, this relation remains valid as long as the code under consideration is in the linear part of the sinusoid, i.e. i close to 2 n /2. So it is possible to obtain an estimate of the ADC gain simply using the experimental count H exp (i) for a given code i in the linear section of the sinusoid and the corresponding reference value H ref (i). However for real measurements, the count may vary from a code to another due to regularity defects in the sample distribution. It is consequently reasonable to average the measure on several codes. Considering N codes around the center code 2 n /2, we obtain the following expression for the ADC gain: Gain 1 N 2 n + N 2 i = 2n N H ref (i) H exp (i) Of course, the greater the number of codes N considered, the more accurate the gain computation, provided that all N codes remain in the flat section of the histogram. For illustration, we build up the histogram of an 8-bit converter using 8191 samples with an input sine-wave of 262 LSB peak-to-peak amplitude. We observe that all bins for codes between 92 and 163 present a constant value of 20 to within one sample. It is then possible to average the gain measurement on up to 70 codes. Note that an ideal converter should exhibit a unity gain. Therefore, the gain error of the converter can be

7 Optimizing Sinusoidal Histogram Test 261 expressed in LSB by: Gain Error = 2 n (Gain 1) DNL & INL Calculation. The differential nonlinearity error of a given code i (expressed in LSB) is defined as the relative difference between the experimental count H exp (i) and the corresponding reference one H ref (i) [7]: DNL (i) = Hexp (i) H ref (i) H ref (i) = Hexp (i) H ref (i) 1 The integral non-linearity error of a given code i (expressed in LSB) is then expressed as the cumulative sum of the DNL of all preceding codes [7]: INL = i DNL( j) j=1 Both these expressions involve only simple operations. There is consequently no need of modifying these expressions to integrate the calculation. Operative Resource Minimization. New expressions have been proposed to determine the ADC characteristic parameters using only simple operators. Let us evaluate more precisely the hardware operative resources required to implement the different calculations. Analyzing the different expressions, it appears that: the offset calculation demands a subtracter (omitting the multiplication by a constant), the gain calculation demands an adder and a divider, the DNL and INL calculation demands an adder, a subtracter and a divider. An evident minimization of the operative resources consists in replacing the concurrent calculation of all parameters by a phase-after-phase approach in which each parameter is determined sequentially. Indeed in this case, the subtracter required for the offset calculation can be reused in the DNL and INL calculation phase. In the same way, the adder and divider required for the gain calculation can be reused in the DNL and INL calculation phase. So finally, decomposing the global ADC test in a 3-phase procedure and using the simplified parameter expressions, the operative unit only consists of an adder, a subtracter and a divider instead of a DSP or a microprocessor in the direct implementation of the technique Experimental Histogram Memory Our objective is now to study how it is possible to minimize the memory required for storing the experimental histogram. The fundamental idea is based on the use of a time decomposition technique. Indeed, the previous section has established that it seems judicious to decompose the global test into different phases, each phase dedicated to the calculation of one ADC parameter. This time decomposition allows to reuse the hardware operative resources in the different test phases. The same approach can be adopted inside each test phase in order to minimize the hardware memory resources. The idea is to sequentially store only the code counts needed to compute the ADC parameter for a given test phase. More precisely, we suggest to decompose each test phase in several steps, each individual step requiring only the storage of one code count. In other words, we propose to store and concurrently process the histogram code after code. Offset Determination. The pseudo-code given below details the offset calculation procedure. Only one input pattern is necessary to collect the samples for the two extreme codes. Indeed, during the pattern application, register R1 (respectively R2) is incremented each time the output code is 1 (respectively 2 n ). By the end of the pattern, H exp (i) is stored in register R1 and H exp (2 n ) in register R2. Consequently, subtracting these registers gives the difference between the counts for the two extreme codes. The offset value is then proportional to R1, with K = π FS 4 tan πhref (i). Algorithm 1. Offset calculation procedure R1 = 0, R2 = 0 for n s =1to if code = 1 then R1 = R1 + 1 if code = 2 n then R2 = R2 + 1 n s = n s + 1 R1 = R1 R2 Offset =K.R1 Gain Determination. The pseudo-code given below details the gain calculation procedure. The gain is computed using the counts for the N center codes. However, computation is done sequentially one code after the other. For a given code i, a complete input pattern is used to collect the samples; N patterns are then necessary to carry out the calculation. So for a given code i, the register R1 is incremented each time the output code

8 262 Azaïs etal. is i. By the end of the frame, H exp (i) is stored in register R1. We assume that the corresponding reference value H ref (i) is available at this time in a dedicated register R ref. We can then divide this register with R1 and store the result in R1. Finally, we progressively compute in register R2 the cumulative sum of H ref (i)/h exp (i) (coming from register R1), for the different codes involved in the calculation. The gain value is therefore available in register R2 by the end of the N input patterns. Algorithm 2. Gain calculation procedure R2 = 0 for i = (2 n N)/2 + 1to(2 n + N)/2 R1 = 0 R ref = H ref (i) for n s = 1 to if code = i then R1 = R1 + 1 n s = n s + 1 R1 = R ref /R1 R2 = R1 + R2 i = i + 1 R2 = R2/N Gain =R2 DNL & INL Determination. The pseudo-code given below details the non-linearity calculation procedure. Both DNL and INL have to be evaluated for each of the 2 n codes. Computation is performed code after code, using a complete input pattern for each code. So for a given code i, H exp (i) is accumulated in register R1 during the corresponding pattern. Dividing R1 by the reference value H ref (i) and subtracting 1 gives the DNL value. The INL value is then obtained by progressively accumulating all the DNL values in register R2. Algorithm 3. Non-linearity calculation procedure R2 = 0 for i = 1 to 2 n R1 = 0 R ref = H ref (i) for n s = 1 to if code=i then R1 = R1 + 1 n s = n s + 1 R1 = R1/R ref R1 = R1 1 DNL(i) =R1 R2 = R1 + R2 INL(i) =R2 i = i + 1 Memory Resource Minimization. Concerning memory resources, it clearly appears on the pseudoalgorithms presented above that besides a dedicated register (R ref ) for the storage of reference data, only 2 registers (R1 and R2) working with experimental data are sufficient to implement each ADC parameter calculation. Note that the same 2 registers can be used in the different phases because of the global test decomposition procedure. So it finally comes out that using the time decomposition concept, the experimental histogram memory unit only consists of 2 registers. In addition, it is to remark that because of the sequential calculation procedure, the adder and the subtracter are never used at the same time. It is consequently possible to go further in the minimization process of the operative unit replacing these two operators by a single adder/subtracter Reference Histogram Memory The last point to investigate now concerns the minimization of the reference histogram memory unit. Indeed, the direct storage of a histogram for a n-bit converter necessitates 2 n memory words, which is an unacceptable solution in terms of silicon area. A first evident minimization consists in storing only half the data due to the symmetrical property of the reference histogram. However, a memory of 2 n /2 words still represents a too large silicon area. Hence, we propose an alternative approach that consists in computing on-chip the reference histogram, only one code bin being computed at a time. This approach is of course only valid with the code-after-code test procedure presented in the previous section. The main difficulty stands in the computation of the reference histogram, which is given by the following equation: H ref (i) = π { [( 2i 2 sin 1 n 2 n sin 1 [( 2i 2 n 2 2 n ) FS A in ] ) FS A in ] } The on-chip computation of such a complex function is obviously not compatible with the constraint of a small area overhead. We actually propose to approximate this function by a simpler one. A classical approach consists in determining a polynomial which best fits the set of data points given by the reference

9 Optimizing Sinusoidal Histogram Test 263 histogram. The on-chip computation of the polynomial then provides an estimate of the reference histogram. However, implementing this classical approach necessitates to add a multiplier in the BIST circuitry to perform the polynomial computation. Since our first concern is the minimization of the hardware BIST resources, we choose a slightly different approach. The idea is to realize the approximation with a function that can be computed with the operative resources already available on-chip, instead of using a polynomial. This is then a pragmatic approach. So, taking into account that the operative unit comprises an adder/subtracter and a divider, we propose to estimate the reference histogram with a curve described by: H est (i) = α i + β where α and β are coefficients to be determined to ensure the best fitting between the reference (H ref ) and estimated (H est ) curves. Obviously, it is not possible using such a function to obtain a good fitting on the complete domain, i.e. for i varying from 1 to 2 n. But as already mentioned, only half the histogram can be considered due to the symmetrical property. Even in this case, the precision on the estimated histogram appears non acceptable. Consequently, we suggest to perform a piece-wise approximation defining several domains in half the histogram (see Fig. 5). For each domain, we can determine the α k and β k coefficients of the best fitting curve. The number of domains to consider directly depends on the desired precision for the estimated histogram. We actually develop a software routine in Labview that permits to define the different domains and the Fig. 5. Piece-wise approximation of the reference histogram. associated coefficients, for a given maximum error between the reference and estimated curves. As an example, we consider the histogram obtained for an 8-bit converter using 8191 samples and an input sinewave of 262 LSB peak-to-peak amplitude. We specify a maximum error between the original and estimated curves of 0.05%, and the routine finds out that 6 domains are sufficient to fulfil this requirement. It is to note that the number of domains required to approximate the reference histogram does not drastically increase with the number of bits of the converter. For instance, considering a 12-bit converter and the same maximum error of 0.05%, only 8 domains permit to approximate the reference histogram. Concerning hardware resources, we have seen that all the required operators are already available in the operative unit. It is therefore just necessary to consider memory resources. The implementation of our solution only necessitates 2 registers per domain for the storage of the α k and β k coefficients, plus an additional register R ref that contains the result of the computation according to the different steps of the test procedure. For illustration, the reference histogram memory then contains 13 registers in case of a 8-bit converter or 17 registers in case of a 12-bit converter. 5. Evaluation To make the histogram method acceptable in the context of BIST, we have proposed different simplifications permitting to minimize as much as possible the additional circuitry. We finally obtain a structure composed of an adder/subtracter and a divider for the operative unit, 2 registers for the experimental histogram memory and 2 k + 1 registers for the reference histogram memory, k being the number of domains for the piece-wise approximation. This structure has to be compared to the original one, which comprises a DSP for the operative unit, 2 n memory words for the experimental histogram memory and 2 n memory words for the reference histogram memory. It is clear that we have a drastic reduction of the required hardware resources, then making viable a BIST solution. In order to validate the structure, we now have to evaluate its performances. We want to compare our implementation of the histogram technique, which comprises a number of simplifications and approximations, to the original implementation with exact formulae. For this purpose, we develop an evaluation program in

10 264 Azaïs etal. Table 2. Error on ADC parameter measurements. Type of Our Original Difference measurements approach approach (in LSB) Offset error # measurements # (in LSB) # # Gain error # measurements # (in LSB) # # Max DNL # measurements # (in LSB) # # Fig. 6. Comparison of measurement results for (a) offset, (b) gain, (c) DNL and (d) INL determination. Max INL # measurements # (in LSB) # # Labview that permits to (i) simulate a converter (with or without errors), (ii) build the associated histogram and (iii) extract the ADC parameters using either our approach or the original one. As an example in this paper, we consider an 8-bit converter, an input sine wave of 262 LSB peak-topeak amplitude and = 8191 samples to build up the histogram. We also specify a maximum error of 0.05% for the piece-wise approximation of the reference histogram and we choose to compute the gain using the 50 center codes. Then, we run the program on various cases of converter error. For each type of error (offset, gain and non-linearity), we compare the measurements obtained using our approach or the original one. Fig. 6 presents some of the results taking into account typical error values. It can be noted that for all the simulated cases, we observe a very good agreement between measurements. In fact, it appears that except for the case #1, we obtain a difference between the measurements of less than 0.05 LSB. All these differences are reported in Table 2. Note that the case #1 corresponds to a relatively large offset error (around 2 LSB) compared to the amplitude of the input sine-wave (262 LSB), which explains the imprecision of our measurement. Indeed as stated in Section 4.1, the approximation that replaces the sum of the code counts for the two extreme codes by a constant introduces an error all the more important as the offset is large. However, more precise estimation of the offset could be obtained using an input sine-wave of larger amplitude. 6. Conclusion The histogram test method for ADC is usually invoked in the context of external testing because of the large amount of hardware resources required for its implementation; two large RAMs and DSP capabilities. In order to reduce as much as possible this additional circuitry, this paper analyzes in detail the histogram technique and proposes several simplifications. The first one concerns the calculation of the ADC parameters, which usually requires complex operations. It has been demonstrated that good estimates of offset, gain, DNL and INL can been obtained using operations as simple as addition, subtraction and division. As a result, only one adder/subtracter and one divider are necessary if the global test procedure is decomposed in several phases, each phase dedicated to the evaluation of a given ADC parameter. Indeed, the same operative resources can then be used in the successive different phases. The second simplification concerns the storage of the experimental histogram. It has been shown that using the time decomposition concept, it is possible to sequentially store only the code counts needed to

11 Optimizing Sinusoidal Histogram Test 265 compute the ADC parameter for a given phase. A code-after-code procedure has been developed that employs only 2 registers for the storage of experimental data. Finally the last simplification addresses the storage of the reference histogram. An original approach based on a piece-wise approximation has been proposed to reduce the amount of required memory. The idea is to perform the computation of the reference histogram using the operators already available on-chip, only one code being computed at a time. It has been shown that the implementation of this solution necessitates 2 registers per domain of approximation for the storage of the coefficients determining the best fitting curve, plus an additional register that contains the result of computation according to the different steps of the test procedure. To summarize, this work shows that it is possible to drastically reduce the amount of additional on-chip circuitry required to implement the histogram test technique. Experiments conducted on various examples of faulty converters have validated the approach since comparable results are obtained using either our BIST structure or the original histogram technique. However, the reduction of the additional circuitry is obtained to the prejudice of the testing time. Indeed, the sequential decomposition of the test procedure implies that a high number of input test patterns are required to complete the test. Further investigations will concentrate on this issue. References 1. K. Arabi and B. Kaminska, Efficient and Accurate Testing of Analog-to-Digital Converters Using Oscillation-Test Method, in Proc. European Design & Test Conference, 1997, pp K. Damm and W. Anheier, HBIST Of Nonlinear Analog Building Blocks In Mixed-Signal Circuits, in Proc. Int l Mixed Signal Testing Workshop, 1995, pp R. de Vries, T. Zwemstra, E. Bruls, and P. Regtien, Built-In Self-Test Methodology for A/D Converters, in Proc. European Design & Test Conference, 1997, pp J. Doernberg, H.S. Lee, and D.A. Hodges, Full Speed Testing of A/D Converters, IEEE J. Solid-State Circuits, Vol. SC 19, No. 6, pp , December A. Frish and T. Almy, HABIST: Histogram-based Analog Built- In Self-Test, in Proc. International Test Conference, 1997, pp V. Liberali, F. Maloberti, and M. Stramesi, ADC Characterization Using the Code Density Test Method With Deterministic Sampling, in Proc. Int l Mixed Signal Testing Workshop, May 1996, pp M. Mahoney, DSP-based Testing of Analog and Mixed-Signal Integrated Circuits, IEEE Computer Society Press, New York, N. Nagi, A. Chatterjee, and J. Abraham, A Signature Analyzer for Analog and Mixed-Signal Circuits, in Proc. ICCD, 1994, pp M.J. Ohletz, Hybrid Built In Self Test (HBIST) for Mixed Analog / Digital Integrated Circuits, in Proc. European Test Conference, 1991, pp G.W. Roberts and A.K. Lu, Analog Signal Generation for Built-In Self-Test of Mixed-Signal Integrated Circuits, Dordrecht Kluwer Academic Publishers, M. Renovell, F. Azaïs, S. Bernard, and Y. Bertrand, Procédé et dispositif de test intégré pour un CAN, CNRS Fr. Patent , filed September 9, M. Renovell, F.Azaïs, S. Bernard, and Y. Bertrand, Hardware Resource Minimization for a Histogram-based ADC BIST, in Proc. VLSI Test Symposium, May 2000, pp S. Sunter and N. Nagi, A Simplified Polynomial Fitting Algorithm for DAC and ADC BIST, in Proc. International Test Conference, 1997, pp E. Teraoca, T. Kengaku, I. Yasui, K. Ishikawa, and T. Matsuo, A Built-In Self-Test for ADC and DAC in a Single-Chip Speech CODEC, in Proc. International Test Conference, 1993, pp M.F. Toner and G.W. Roberts, A BIST Scheme for a SNR, Gain Tracking and Frequency Response Test of a Sigma-Delta ADC, IEEE Trans. Circuits & Systems II, Vol. 42, pp. 1 15, M.F. Toner and G.W. Roberts, A Frequency Response, Harmonic Distortion, and Intermodulation Distortion Test for BIST of a Sigma-Delta ADC, in IEEE Trans. Circuits & Systems II, Vol. 43, No. 8, pp , Florence Azaïs received the MS and PhD degrees in electrical engineering both from the University of Montpellier, France. She is currently working in the Microelectronics Department of the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM) as a Researcher of the National Council of Scientific Research (CNRS). Since 1993, she has been interested in the testing domain. Her main research interests include Analog and Mixed- Signal Circuit Testing and Fault Modeling. Serge Bernard received the MS degree in Electrical Engineering from the University of Paris XI, France. He is currently working in the Microelectronics Department of the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM) where he is doing a PhD. His main research interests include Test, Design- For-Testability and Built-In-Self-Test for mixed-signal circuits. Yves Bertrand is a Professor at the University of Montpellier (France). He works at the Microelectronics Department of the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM). Previously, Yves Bertrand worked in the field of solid-state physics and published several papers, especially on the photoemission of the semiconductors under synchrotron radiation. He joins the LIRMM in His research interests are principally Fault Modeling, Design-For-Test and Built-In Self- Test for digital and mixed-signal Integrated Circuits and Design

12 266 Azaïs etal. & Test of Microsystems. He is author or co-author of more than 100 papers in the the field of solid-state physics and microelectronics. He is presently responsible for the CRTC (Test Resource Center of CNFM). Michel Renovell received his MS and Ph.D. in applied physics both from the University of Montpellier, France. He is a researcher at LIRMM (Lab of Computer Science, Robotics, and Microelectronics of Montpellier) and head of the Microelectronics Department. He is Chair of the Communication Group of the IEEE Computer Society Test Technology Technical Committee (TTTC). His research interests include analog and mixed-signal circuit testing, fault modeling, and reconfigurable-circuit testing. He is an Editor of the Journal of Electronic Testing: Theory and Applications.