RT9173D. Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator. Features. General Description. Applications. Ordering Information

Transcription

1 Pin Configurations Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator General Description The is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_ and SSTL_ or other specific interfaces such as HSTL, SCSI- and SCSI-3 etc. devices requirements. The regulator is capable of actively sinking or sourcing continuous A or up to 3A transient peak current while regulating an output voltage to within mv. The output termination voltage cab be tightly regulated to track /V DDQ by two external voltage divider resistors or the desired output voltage can be pro-grammed by externally forcing the REFEN pin voltage. The also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient. Other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. The are available in the SOP- (Exposed Pad) surface mount packages. Ordering Information Note : Richtek products are : Package Type SP : SOP- (Exposed Pad-Option ) Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-. Suitable for use in SnPb or Pb-free soldering processes. Features Ideal for DDR-I, DDR-II and DDR-III V TT Applications Sink and Source Current A Continuous Current Peak 3A for DDRI and DDRII Peak.5A for DDRIII Integrated Power MOSFETs Generates Termination Voltage for SSTL_, SSTL _, HSTL, SCSI- and SCSI-3 Interfaces High Accuracy Output Voltage at Full-Load Output Adjustment by Two External Resistors Low External Component Count Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output Current Limiting Protection On-Chip Thermal Protection Available in SOP- (Exposed Pad) Packages V IN and V CNTL No Power Sequence Issue RoHS Compliant and % Lead (Pb)-Free Applications Desktop PCs, Notebooks, and Workstations Graphics Card Memory Termination Set Top Boxes, Digital TVs, Printers Embedded Systems Active Termination Buses DDR-I, DDR-II and DDR-III Memory Systems VIN REFEN VOUT (TOP VIEW) SOP- (Exposed Pad) NC NC VCNTL NC DS973D-7 April

2 Typical Application Circuit V CNTL = 3.3V V IN =.5V/.V/.5V R TT N7 R VIN VCNTL REFEN VOUT C IN C CNTL EN R C SS C OUT R = R = kω, R TT = 5Ω / 33Ω / 5Ω C OUT(MIN) = μf (Ceramic) + μf under the worst case testing condition C SS = μf, C IN = 7μF (Low ESR), C CNTL = 7μF Test Circuit.5V/.V/.5V 3.3V VIN VCNTL.5V/.9V/.75V REFEN VOUT V OUT Figure. Test Circuit for Typical Operating Characteristics Curves DS973D-7 April

3 Functional Pin Description VIN (Pin ) Input voltage which supplies current to the output pin. Connect this pin to a well-decoupled supply voltage. To prevent the input rail from dropping during large load transient, a large, low ESR capacitor is recommended to use. The capacitor should be placed as close as possible to the VIN pin. [Pin, Exposed pad (9)] Common Ground (Exposed pad is connected to ). The pad area should be as large as possible and using many vias to conduct the heat into the buried plate of PCB layer. REFEN (Pin 3) Reference voltage input and active low shutdown control pin. Two resistors dividing down the VIN voltage on the pin to create the regulated output voltage. Pulling the pin to ground turns off the device by an open-drain, such as N7, signal N-MOSFET. VOUT (Pin ) Regulator output. VOUT is regulated to REFEN voltage that is used to terminate the bus resistors. It is capable of sinking and sourcing current while regulating the output rail. To maintain adequate large signal transient response, typical value of μf AL electrolytic capacitor with μf ceramic capacitors are recommended to reduce the effects of current transients on VOUT. VCNTL (Pin ) VCNTL supplies the internal control circuitry and provides the drive voltage. The driving capability of output current is proportioned to the VCNTL. Connect this pin to 3.3V bias supply to handle large output current with at least μf capacitor from this pin to. NC (Pin 5, 7, ) No Internal Connect. Function Block Diagram VCNTL VIN Current Limit Thermal Protection REFEN + EA VOUT - DS973D-7 April 3

4 Absolute Maximum Ratings (Note ) Input Voltage, V IN V Control Voltage, V CNTL V Power Dissipation, P T A = 5 C SOP- (Exposed Pad) W Package Thermal Resistance (Note ) SOP- (Exposed Pad), θ JA C/W SOP- (Exposed Pad), θ JC C/W Junction Temperature C Lead Temperature (Soldering, sec.) C Storage Temperature Range C to 5 C ESD Susceptibility (Note 3) HBM (Human Body Mode) kv MM (Machine Mode) V Recommended Operating Conditions (Note ) Input Voltage, V IN V to.5v ± 5% Control Voltage, V CNTL V or 3.3V ± 5% Ambient Temperature Range C to 5 C Junction Temperature Range C to 5 C Electrical Characteristics (V IN =.5V/.V/.5V, V CNTL = 3.3V, V REFEN =.5V/.9V/.75V, C OUT = μf (Ceramic), TA = 5 C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Input V CNTL Operation Current I CNTL I OUT = A --.5 ma Standby Current (Note 5) I STBY V REFEN <.V (Shutdown), R LOAD = Ω μa Output (DDR / DDR II / DDR III) Output Offset Voltage (Note ) V OS I OUT = A -- + mv Load Regulation (Note 7) ΔV LOAD I OUT = +A I OUT = A -- + mv Protection Current limit I LIM V IN =.5V/.V/.5V A Thermal Shutdown Temperature T SD 3.3V V CNTL 5V C Thermal Shutdown Hysteresis ΔT SD 3.3V V CNTL 5V C REFEN Shutdown Shutdown Threshold V IH Enable V IL Shutdown V DS973D-7 April

5 Note. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note. θja is measured in the natural convection at TA = 5 C on a high effective thermal conductivity test board ( Layers, SP) of JEDEC 5-7 thermal measurement standard. The case point of θjc is on the expose pad for SOP- (Exposed Pad) package. Note 3. Devices are ESD sensitive. Handling precaution recommended. Note. The device is not guaranteed to function outside its operating conditions. Note 5. Standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown signal on REFEN pin (VIL <.V). It is measured with VIN = VCNTL = 5V. Note. V OS offset is the voltage measurement defined as V OUT subtracted from V REFEN. Note 7. Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load regulation in the load range from A to A. DS973D-7 April 5

6 Typical Operating Characteristics.77 Output Voltage vs. Temperature VIN =.5V.9 Output Voltage vs. Temperature VIN =.V Output Voltage (V) Output Voltage (V) Output Voltage vs. Temperature VIN =.5V. Shutdown Threshold vs. Temperature Output Voltage (V) Shutdown Threshold (V) VCNTL = 5V, Turn On VCNTL = 5V, Turn Off VCNTL = 3.3V, Turn On VCNTL = 3.3V, Turn Off VIN Current (ma) V IN Current vs. Temperature VIN =.V, VCNTL = 3.3V VIN =.V, VCNTL = 5V VIN =.5V, VCNTL = 3.3V VIN =.5V, VCNTL = 5V VIN =.5V, VCNTL = 5V VIN =.5V, VCNTL = 3.3V Vcntl Current (ma) Vcntl Current vs. Temperature VIN =.V, VCNTL = 3.3V VIN =.V, VCNTL = 5V VIN =.5V, VCNTL = 3.3V VIN =.5V, VCNTL = 5V VIN =.5V, VCNTL = 5V VIN =.5V, VCNTL = 3.3V DS973D-7 April

7 Source Current Limit (A) Source Current Limit vs. Temperature VIN =.V, VCNTL = 5V VIN =.V, VCNTL = 3.3V VIN =.5V, VCNTL = 5V VIN =.5V, VCNTL = 3.3V VIN =.5V, VCNTL = 5V VIN =.5V, VCNTL = 3.3V Sink Current Limit (A) Sink Current Limit vs. Temperature VIN =.V, VCNTL = 3.3V VIN =.5V, VCNTL = 3.3V VIN =.5V, VCNTL = 5V VIN =.V, VCNTL = 5V VIN =.5V, VCNTL = 5V VIN =.5V, VCNTL = 3.3V V A Transient Response.9V A Transient Response Output Voltage Transient (mv) - VIN =.V, VCNTL = 3.3V, VOUT =.9V Sink Output Voltage Transient (mv) - VIN =.V, VCNTL = 3.3V, VOUT =.9V Source Output Current (A) Swing Frequency : khz Output Current (A) Swing Frequency : khz Time (5μs/Div) Time (5μs/Div).75V A Transient Response.75V A Transient Response Output Voltage Transient (mv) - VIN =.5V, VCNTL = 3.3V, VOUT =.75V Sink Output Voltage Transient (mv) - VIN =.5V, VCNTL = 3.3V, VOUT =.75V Source Output Current (A) Swing Frequency : khz Output Current (A) Swing Frequency : khz Time (5μs/Div) Time (5μs/Div) DS973D-7 April 7

8 .5V A Transient Response.5V A Transient Response Output Voltage Transient (mv) - VIN =.5V, VCNTL = 3.3V, VOUT =.5V Sink Output Voltage Transient (mv) - VIN =.5V, VCNTL = 3.3V, VOUT =.5V Source Output Current (A) Swing Frequency : khz Output Current (A) Swing Frequency : khz Time (5μs/Div) Time (5μs/Div) Output Short-Circuit Protection Output Short-Circuit Protection VIN =.5V, VCNTL = 3.3V Sink VIN =.5V, VCNTL = 3.3V Source Output Short Circuit (A) Output Short Circuit (A) Time (ms/div) Time (ms/div) Output Short-Circuit Protection Output Short-Circuit Protection VIN =.V, VCNTL = 3.3V Sink VIN =.V, VCNTL = 3.3V Source Output Short Circuit (A) Output Short Circuit (A) Time (ms/div) Time (ms/div) DS973D-7 April

9 Output Short-Circuit Protection Output Short-Circuit Protection VIN =.5V, VCNTL = 3.3V Sink VIN =.5V, VCNTL = 3.3V Source Output Short Circuit (A) Output Short Circuit (A) Time (ms/div) Time (ms/div) DS973D-7 April 9

10 Application Information Consideration while designs the resistance of voltage divider Make sure the sinking current capability of pull-down NMOS if the lower resistance was chosen so that the voltage on V REFEN is below.v. In addition, the capacitor and voltage divider form the lowpass filter. There are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. How to reduce power dissipation on Notebook PC or the dual channel DDR SDRAM application? In notebook application, using RichTek's Patent Distributed Bus Terminator Topology with choosing RichTek's product is encouraged. Distributed Bus Terminating Topology General Regulator The could also serves as a general linear regulator. The accepts an external reference voltage at REFEN pin and provides output voltage regulated to this reference voltage as shown in Figure 3, where V OUT = V EXT x R/(R+R) As other linear regulator, dropout voltage and thermal issue should be specially considered. Figure and 5 show the R DS(ON) over temperature of in PSOP- (Exposed Pad) package. The minimum dropout voltage could be obtained by the product of R DS(ON) and output current. For thermal consideration, please refer to the relative sections. R DS(ON) vs. Temperature. VCNTL = 3.3V.35 REFEN Terminator Resistor VOUT VOUT R R R R3 R R5 R R7 R R9 R(N) R(N+) BUS() BUS() BUS() BUS(3) BUS() BUS(5) BUS() BUS(7) BUS() BUS(9) BUS(N) BUS(N+) RDS(ON) (Ω) Figure R DS(ON) vs. Temperature VCNTL = 5V V EXT R Figure VCNTL VIN REFEN VOUT V OUT RDS(ON) (Ω) R Figure Figure 5 DS973D-7 April

11 Input Capacitor and Layout Consideration Place the input bypass capacitor as close as possible to the. A low ESR capacitor larger than 7uF is recommended for the input capacitor. Use short and wide traces to minimize parasitic resistance and inductance. Inappropriate layout may result in large parasitic inductance and cause undesired oscillation between and the preceding power converter. Thermal Consideration regulators have internal thermal limiting circuitry designed to protect the device during overload conditions. For continued operation, do not exceed maximum operation junction temperature 5 C. The power dissipation definition in device is: P D = (V IN - V OUT ) x I OUT + V IN x I Q The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula: P D(MAX) = ( T J(MAX) -T A ) /θ JA Where T J(MAX) is the maximum operation junction temperature 5 C, T A is the ambient temperature and the θ JA is the junction to ambient thermal resistance. The junction to ambient thermal resistance (θ JA is layout dependent) for SOP- package (Exposed Pad) is 75 C/W on standard JEDEC 5-7 ( layers, SP) thermal test board. The maximum power dissipation at T A = 5 C can be calculated by following formula: P D(MAX) = (5 C - 5 C) / 75 C/W =.33W Figure show the package sectional drawing of SOP- (Exposed Pad). Every package has several thermal dissipation paths. As show in Figure 7, the thermal resistance equivalent circuit of SOP- (Exposed Pad). The path is the main path due to these materials thermal conductivity. We define the exposed pad is the case point of the path. Junction Ambient Molding Compound Gold Line Die Pad Case (Exposed Pad) Lead Frame Figure. SOP- (Exposed Pad) Package Sectional Drawing R GOLD-LINE path R DIE R DIE-ATTACH R DIE-PAD path R LEAD FRAME R MOLDING-COMPOUND path 3 R PCB R PCB Case (Exposed Pad) Figure 7. Thermal Resistance Equivalent Circuit Ambient The thermal resistance θ JA of SOP- (Exposed Pad) is determined by the package design and the PCB design. However, the package design has been decided. If possible, it's useful to increase thermal performance by the PCB design. The thermal resistance can be decreased by adding copper under the expose pad of SOP- package. About PCB layout, the Figure show the relation between thermal resistance θ JA and copper area on a standard JEDEC 5-7 ( layers, SP) thermal test board at T A = 5 C.We have to consider the copper couldn't stretch infinitely and avoid the tin overflow. We use the dog-bone copper patterns on the top layer as Figure 9. As shown in Figure, the amount of copper area to which the SOP- (Exposed Pad) is mounted affects thermal performance. When mounted to the standard SOP- (Exposed Pad) pad of oz. copper (Figure.a), θ JA is 75 C/W. Adding copper area of pad under the SOP- (Exposed Pad) (Figure.b) reduces the θ JA to C/W. Even further, increasing the copper area of pad to 7mm (Figure.e) reduces the θ JA to 9 C/W. DS973D-7 April

12 θ JA vs. Copper Area 9 θja ( C/W) 7 5 Figure (b). Copper Area = mm, θ JA = C/W Copper Area (mm ) Figure Exposed Pad Figure (c). Copper Area = 3mm, θ JA = 5 C/W W.mm Figure 9.Dog-Bone layout Figure (d). Copper Area = 5mm, θ JA = 5 C/W Figure (a). Minimum Footprint, θ JA = 75 C/W Figure (e). Copper Area = 7mm, θ JA = 9 C/W Figure. Thermal Resistance vs. Different Cooper Area Layout Design DS973D-7 April

13 Outline Information A H M EXPOSED THERMAL PAD (Bottom of Package) J Y X B F I C D Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A B C D F H I..5.. J M Option Option X Y X Y Lead SOP (Exposed Pad) Plastic Package Richtek Technology Corporation Headquarter 5F, No., Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (3)5579 Fax: (3)55 Richtek Technology Corporation Taipei Office (Marketing) 5F, No. 95, Minchiuan Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: ()7399 Fax: () marketing@richtek.com Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS973D-7 April 3