2A Sink/Source Bus Termination Regulator

Transcription

1 2A Sink/Source Bus Termination egulator Product Description The is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DD) memory system to comply with the JEDE SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SSI-2 and SSI-3 etc. devices requirements. The regulator is capable of actively sinking or sourcing up to 2A while regulating an output voltage to within 40mV.The output termination voltage cab be tightly regulated to track 1/2VDDQ by two external voltage divider resistors or the desired output voltage can be pro-grammed by externally forcing the EFEN pin voltage. The also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient. Other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. The are available in the PSOP-8 (Exposed Pad) surface mount packages. Features Ideal for DD-I, DD-II and DD-III V TT Applications Sink and Source 2A ontinuous urrent Integrated Power MOSFETs Generates Termination Voltage for SSTL_2, SSTL_18, HSTL, SSI-2 and SSI-3 Interfaces. High Accuracy Output Voltage at Full-Load Output Adjustment by Two External esistors Low External omponent ount Shutdown for Suspend to AM (ST) Functionality with High-Impedance Output urrent Limiting Protection On-hip Thermal Protection Available in PSOP-8 (Exposed Pad) Packages V IN and V NTL No Power Sequence Issue 100% Lead (Pb)-Free Stable with eramic Output apacitor ohs ompliant, 100%Pb & Halogen Free Applications Desktop Ps, Notebooks, and Workstations Graphics ard Memory Termination Set Top Boxes, Digital TVs, Printers Embedded Systems Active Termination Buses DD-I, DD-II and DD-III Memory Systems Block Diagram 1

2 Packages & Pin Assignments PSF (PSOP- 8) Exposed Thermal Pad PSOP V IN 5 N 2 GND 6 V NTL 3 EFEN 7 N 4 V OUT 8 N Pin Name V IN GND V NTL V OUT EFEN Pin function Power input Ground Gate drive voltage Output voltage eference voltage input and chip enable Ordering Information Marking Information 2

3 Absolute Maximum atings Symbol Parameter Value Unit V IN Input Voltage 6 V V NTL ontrol Voltage 6 V P D Power Dissipation Internally Limited ESD ating 3 KV T S Storage Temperature ange -65 to +150 º T LEAD Lead Temperature(Soldering,5 sec.) 260 º ΘJ Package Thermal esistance 28 º/W Operating ating Symbol Parameter Value Unit V IN Input Voltage 5.5 to 1.5 ±3% V V NTL ontrol Voltage 5.0 to 3.3 ±5% V T A Ambient Temperature -40 to +85 º T J Junction Temperature -40 to +125 º Electrical haracteristics V IN =2.5V/1.8V/1.5V, V NTL =3.3V, V EFEN =1.25V/0.9V/0.75V, OUT =10μF ( eramic ), T A =25, unless otherwise specified Symbol Parameter Test onditions Min Typ Max Unit Input I NTL V NTL Operation urrent I OUT =0A ma I STBY Standby urrent Output (DD / DD II / DD III) V EFEN <0.2V(Shutdown), LOAD =180 Ω µa V OS Output Offset Voltage(3) I OUT = 0A mv ΔV LOAD Load egulation(4) I OUT = +2A mv ΔV LOAD Load egulation(4) I OUT = -2A mv Protection I LIM urrent limit A T SD ΔT SD EFEN Shutdown Thermal Shutdown Temperature Thermal Shutdown Hysteresis 3.3V V NTL 5V º 3.3V V NTL 5V º V IH Shutdown Threshold Enable Shutdown V IL Tss Soft Start interval 1=2=100K, ss=1uf 0.2 ms Note 1: Exceeding the absolute maximum rating may damage the device. Note 2: V OS offset is the voltage measurement defined as V OUT subtracted from V EFEN. Note 3: V OS offset is the voltage measurement defined as V OUT subtracted from V EFEN. Note 4: egulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load regulation in the load range from 0A to 2A. V 3

4 Application Information Input apacitor and Layout onsideration onsideration while designs the resistance of Place the input bypass capacitor as close as possible to voltage divider the. A low ES capacitor larger than 470uF is Make sure the sinking current capability of pull-down recommended for the input capacitor. Use short and NMOS if the lower resistance was chosen so that the wide traces to minimize parasitic resistance and voltage on V EFEN is below 0.2V. In addition, the inductance. Inappropriate layout may result in large capacitor and voltage divider form the low-pass filter. parasitic inductance and cause undesired oscillation There are two reasons doing this design; one is for between and the preceding power converter. output voltage soft-start while another is for noise immunity. EFEN VOUT VOUT (2N) (2N+1) BUS 0 BUS 1 BUS 2 BUS 3 BUS 4 BUS 5 BUS 6 BUS 7 BUS 8 BUS 9 BUS 2N BUS 2N+1 Thermal onsideration regulators have internal thermal limiting circuitry designed to protect the device during overload conditions. For continued operation, do not exceed maximum operation junction temperature 125. The power dissipation definition in device is: P D = (V IN - V OUT ) x I OUT + V IN x I Q The maximum power dissipation depends on the thermal resistance of I package, PB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula: P D(MAX) = ( T J(MAX) -T A ) /Θ JA Where T J(MAX) is the maximum operation junction temperature 125º, T A is the ambient temperature and the Θ JA is the junction to ambient thermal resistance. The junction to ambient thermal resistance (Θ JA is layout dependent) for PSOP-8 package (Exposed Pad) is 75 º/W on standard JEDE 51-7 (4layers, 2S2P) thermal test board. The maximum power dissipation at T A = 25º can be calculated by following formula: P D(MAX) = (125º - 25º) / 75 /W = 1.33W The thermal resistance Θ JA of PSOP-8 (Exposed Pad) is determined by the package design and the PB design. However, the package design has been decided. If possible, it's useful to increase thermal performance by the PB design. The thermal resistance can be decreased by adding copper under the expose pad of PSOP-8 package. We have to consider the copper couldn t stretch infinitely and avoid the tin overflow. Typical Application ircuit V =3.3V V =2.5V/1.8V/1.5V VIN VNTL 2N7002 EN EFEN VOUT GND 1 = 2 =100KΩ, TT =50Ω/33Ω/25Ω OUT, min =10μF(eramic)+1000μF under the worst case testing condition DUMMY =1kΩ as for VOUT discharge when VIN is not present but VNTL is present SS =1μF, IN =470μF(ES), NTL = 1μF 4

5 Typical Operating haracteristics Power On Soft Start (Vin =1.8V) 5

6 Package Dimension PSOP-8 PLASTI PAKAGE Dimensions Millimeters Inches SYMBOL MIN MAX MIN MAX A B D F H I J M X Y

7 NOTIE Information furnished is believed to be accurate and reliable. However Globaltech Semiconductor assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties, which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Globaltech Semiconductor. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information without express written approval of Globaltech Semiconductor. ONTAT US GS Headquarter 4F.,No.43-1,Lane11,Sec.6,Minquan E.d Neihu District Taipei ity 114, Taiwan (.O.) Wu-Xi Branch No.21 hangjiang d., WND, Wuxi, Jiangsu, hina (INFO. &. TEH. Science Park Building A 210 oom) sales@g-tech.com.tw D Division 824 Bolton Drive Milpitas. A sales@g-tech.com.tw Version_1.4 Notice