A Buck Converter for DVS Compatible Processors in Mobile Computing Applications Using Fuzzy Logic Implemented in a RISC based Microcontroller

Transcription

1 A Buck Converter for DVS Compatble Processors n Moble Computng Applcatons Usng Fuzzy Logc Implemented n a RISC based Mcrocontroller Monaf S. Tapou, Hamed S. Al-Raweshdy, Maysam Abbod, Manal J. Al-Knd Abstract The desgn of voltage regulators for moble computng applcatons s complcated by several factors that lead to makng tradeoffs between effcency, voltage rpple and dynamc response. Careful choces must be made n selectng the passve and actve components order to accommodate for the performance fgures requred to acheve compatblty for DVS ready processors. A sutable control scheme must be selected that can suffce the stablty and dynamc response requred. Ths paper descrbes the desgn of Buck converter that has a fuzzy controller mplemented usng Atmel Atmega189 RISC Based mcrocontroller wth a choce of hardware components that wll ensure better effcency whle delverng good stablty and dynamc response. System smulaton was carred out usng MATLAB/SIMULINK. Smulaton results showed that the fuzzy controller has the capablty of provdng response characterstcs that makes t comparable wth PID controllers and more sutable for mplementaton usng mcrocontrollers. Keywords Fuzzy Logc Control, Buck Converter, Mcrocontrollers, PID, RISC, DVS. R I. INTRODUCTION educng power consumpton n moble computng systems has an mportant role n achevng longer runnng tme on a sngle charge of the equpment battery along wth reducng power dsspaton resultng n the possblty of reducng equpment sze. The dynamc voltage and frequency scalng (DVS) s a technque that s beng ncreasngly appled n modern mcroprocessor desgns. It enables talorng processor power n accordance wth the applcaton requrements, and snce dfferent applcaton requred dfferent computatonal power n order to execute a gven task, t becomes possble to reduce processor performance when not needed. Ths s accomplshed by reducng processor clock frequency along wth core voltage. The equaton below shows that dynamc power consumed by processor crcutres whch are mplemented n CMOS technology [1]: P Dynamc α V dd C eff f clk (1) where V dd s supply voltage, Ceff s the total capactance of the nodes weghted wth ts actvty factor, and f clk s the clock frequency. It can be observed that reducng the clock frequency alone would not affect the power consumpton greatly as a gven task wll requre the same number of clock cycles to fnsh but the great power reducton comes from reducng the supply voltage whch comes possble when operatng CMOS crcutry at lower frequency. Ths acton proves to contrbute to a great reducton n power consumed by the processor whch consumes about 58% of the total power needed by any computer system []. The man component n the system that can provde for these reductons n power s the power converter of the system. The DVS compatble processor requres a specal converter desgn that can provde varable output voltages accordng to DVS system requrement. Along wth that the power converter must provde these output changes whle mantanng hgh effcency over the whole operatng range. That makes the power converter a very mportant part n any system that requres voltage scalng. Moble computng devces lke Netbooks, Tablets, and PDAs are suppled wth power packs that consst of several Lthum-on / polymer cells connected n seres wth nomnal voltages of 11.1 Volts or more. Ths voltage s then reduced usng swtch mode regulators n buck topology to provde for the varety of voltages requred to operate the varous crcutres nsde the moble devce. II. RELATED WORKS DVS compatble power supply desgns are always under contnuous development wth varety of deas, systems confguratons and Control algorthms. Zhang et. al. proposed a dgtal PWM/PFM controller wth automatc mode swtchng [15]. Whle the propose desgn comprses good effcency dstrbuton over wde operatng ranges but the hardware complexty and power consumpton makes the desgn successful for hgh powered processors lke those mplemented n laptop computers wth effcency fgure between 86 % and 8%. Dhar et.al. descrbes a swtchng regulator that has the capablty to change supply voltage as requred by applcaton usng a modfed Watkns Johnson converter [16] mplementng a smple Bang Bang controller to obtan fast transent response along wth AVS (Automatc Voltage Scalng ) controller mplemented on a sngle chp usng standard CMOS process. The end system has all components ncludng nductors and capactors mplemented usng CMOS technology whch means the converter wll work at several MHz frequency. The resultng effcency vares between 80% to 90 when operated at 0MHz to 30MHZ. Gupta et.al. proposed a Fuzzy controller for DC-DC converter usng 87C75 mcrocontroller form Intel [17]. They have demonstrated that stable responses can be obtaned from any converter topology (Buck or Boost) wthout any change n control program. III. DESIGNING A DVS COMPATIBLE POWER CONVERTER DVS compatble power converters have specal requrements as they work on a varable load that needs to change ts operatng voltage n accordance wth the requrements of the runnng software. Along wth ths comes addtonal requrements, these nclude the need for faster transton tmes durng load changes [3]. The DVS compatble converter works n two man modes. Regulaton mode where the converter tres to keep the voltage suppled to the load constant. Trackng mode where the regulator starts changng the output voltage as requested by the DVS scheduler. ISBN:

2 To start desgnng the buck converter requred, one must frst choose the target processor, as an example, a processor s selected from Intel XScale famly of DVS compatble processor namely the PXA70. The power requrements for ths processor has been nvestgated [4][5] and t requres fve separate converters one of whch must be DVS compatble n order to utlze the power reducton capabltes of ths processor. Ths converter supples the core of the processor whch works on a voltage rangng from 0.85Volts at low workloads to 1.55 Volts at peak workloads wth maxmum core power fgure of 95mW. Other system parameters are also beng put nto consderaton whle calculatng component values for the Buck converter desgn. Before startng the calculaton, the choce of the mcrocontroller s to be made and that has been done comparng features of mcrocontroller famles from several manufacturers whle keepng n mnd the power consumpton fgure for the mcrocontroller n addton to ntegrated perpherals and nstructon set. DSPs were not ncluded n the search because of ther relatvely hgh power consumpton fgures that render them nadequate for moble applcatons. The PIC16FXX from Mcrochps, and AVR ATmegaxx from Atmel. The choce has fallen on the RISC based Atmega169 for havng very low power consumpton fgure and a host of analogue perpherals and ts nstructon set provdes better flexblty than that of the PIC16FXX famly [6][7]. The pulse wdth modulator frequency that s to be mplemented usng the Atmel mega169 mcrocontroller s selected to be 40 KHz. Ths fgure wll make t possble to mplement the dgtally controlled buck converter whle mantanng low power operaton of the mcrocontroller n use. The careful selecton of desgn components wll ensure hgher effcency, n case of swtchng elements, the MOSFET transstors, these wll be selected accordng to ther fgure of mert (FOM) whch s based on channel ON resstance (R DSon ) and gate charge (Q G ) these two fgures reflects the conducton losses of the devce and ts drve charge requrements. Selectng MOSFETS havng the lowest possble fgures for FOM wth the requred voltage and current ratngs wll result n a better converter desgn. The TI CSD1731Q5 MOSFET for swtch and the TI CSD1631Q5 MOSFET for synchronous rectfer [11] were chosen for havng a very low FOM n addton to a 1.1Volts gate threshold voltage whch smplfes drvng requrements. As the topology chosen for the buck converter s the one that uses synchronous rectfer, the TI UCC7 Gate Drvng IC [1] s selected to smplfy MOSFET gatng and has a predctve gate tmng functon the helps elmnatng cross currents and actvely boost effcency. To calculate the values of the passve components and at the same tme adherng wth common desgn methodologes followed n buck converters for DVS applcatons [3][8] the choce of the components wll be made as follows: After settng nput and output voltages, maxmum load current, and converter frequency, the value of the nductor s calculated from the followng equaton [9]: ( VIN L= V V IN f sw ) V I L () where L s n Henres, I L s the peak nductor current rpple n Amperes and s usually chosen between 0% to 40% from the maxmum load current [8][9]. Ths equaton results n L values rangng from 115.7µH to 31.5µH. Larger values gve lower output voltage rpple but reduce the dynamc response of the system [3][9]. I s the maxmum current flowng through the nductor and s calculated for the followng equaton [9]: I = I,max I + (3) An nductor wth I SAT large than I (0.908A) must be selected to avod saturatng the magnetc core materal whch wll result n poor regulaton and larger nductor losses. As the DVS compatble converter requres fast response, L s selected to be close to the mnmum value. The maxmum allowable overshoot n supply voltage s taken from the data sheet [4] to be 10% of the output voltage. Ths value wll be used to calculate the capactor (C) as follows [9]: C = ( V + V L ( I ), overshoot ) V (4) From the above equaton a capactor value of about 180 µf s found. The choce of capactors must be made whle consderng another factor called the effectve seres resstance of the capactor (ESR). Ths fgure can be calculated from the equaton gven below [9]: ESR= V I, overshoot (5) The calculated ESR value s 170mΩ, the capactor selected should have t ESR fgure below that but f power effcency s of prme mportance the capactor selected must be of low ESR type lke Polymer Cathode Tantalum, Sold Alumnum Polymer Electrolyte or Ceramc thn flm capactors. Fgure 1 shows the block dagram of the proposed buck converter. FUSE 11.1 Volts BATTERY mcro F. Cn CSD173 1Q5 UCC 7 Synchronous Buck Gate Drve PWMand Control ATmel ATmega169 Mcrocontroller CSD163 1Q5 Fg. 1 buck converter proposed desgn for PXA70 core supply The desgned converter losses were calculated [8][13] for the selected components accordng to the operatng condtons gven n the desgn. The desgn yelded a 9.0% effcency fgure sustanable over wde operatng condtons L 11 6 mcro H 18 0 mcro F. Voltage Feed to ADC npu + C PXA 70 Procssor Core ISBN:

3 for the specfc load. Table I shows the power loss and the effcency fgures expected for the desgned buck converter. TABLE I POWER LOSSES AND EFFICIENCY OF THE DESIGNED BUCK CONVERTER V IN=11.1 Volts, V =1.55 Volts, P LOAD=95mWatts, F Converter=40KHz Component MOSFET Swtch CSD1731Q5 MOSFET Sync. RECT. CSD1631q5 Power loss 1.308mWatts.071mWatts Inductor L (ESR=10.0mΩ) 3.35mWatts Capactor C (ESR=30mΩ) Gate Drver UCC7 RISC Mcrocontroller ATmega169 Total Loss.488mWatts 48.84mWatts 15.51mWatts mWatts Effcency 9.63% IV. SELECTING CONTROLLER AND PERFORMING CIRCUIT SIMULATION Whle general purpose DC-DC converters are commonly desgned mplementng a lnear controller of some sort for example lnear proportonal ntegral (PI) or proportonal ntegral dervatve (PID) controllers. In these cases an accurate model for the converter becomes essental to obtan a gven performance standard. Lnear control strateges usually attempt to lnearze the dynamcs behavor for a certan operatng regon dependng on the mathematcal model of the system. The resultng controller wll be useful for lmted operatng range and ths s not the case wth the DC-DC converters desgned to be DVS compatble thus the requrement for a control system that can cope wth these varatons becomes necessary. These nclude non lnear PID controller, Fuzzy controllers and Neural Network controllers along wth other varatons. Wth the excepton of the Fuzzy controller, other controllers mplementaton requres larger software overhead whch renders them n applcable to smple mcrocontrollers, and ther mplementaton requres usng DSP processors or FPGA devces [14 ]. MATLAB/SIMULINK s used to desgn a model for a buck converter []. The model was bult observng the basc Buck Converter Crcut show n fgure. Fg. basc buck converter crcut where S1 s the MOS Swtch and S s the MOS synchronous rectfer, V S s the source voltage, V O s the output voltage, Lm s the converter Man Inductance, Cm s the man capactor and R L d the load resstance. The analyss method of ths converter has followed the lterature of references [18][19][0]. The constructed SIMULINK model ncluded the addtonal detals of crcut components lke the R DSon of the swtch and synchronous rectfer MOS transstors, ECR of the Inductor and Capactor. In addton to that the model has ncluded elements for conductng lne, load regulaton, and transent response analyss where the load resstance was change and the effect on the controller behavor was observed. The Source voltage has been made to change mmckng a battery operatng from a fully charged state untl becomng flat. Fgure 3 shows the SIMULINK model bult for the buck converter along wth the testng block. Fg. 3 the SIMULINK model for the buck converter wth the lne and load testng elements. The Fuzzy controller beng selected for the buck converter desgn due to the fact that ths type of controllers can delver performance fgures and operatonal flexblty requred wth out demandng exact mathematcal models or the need for complex computatonal power to perform[17][1]. Thus, Fuzzy based controller desgn would be very applcable when RISC based mcro-power mcrocontrollers are consdered. Fuzzy logc control provdes a formal methodology for representng, manpulatng and mplementng a human s heurstc knowledge about how to control a system. Bascally t s an artfcal decson-maker that operates n a closed loop system n real tme. It gathers plant output data, compares t to reference nput and then decdes what the plant nput should be to ensure that the performance objectve wll be met. The Desgn of a fuzzy logc controller conssts of four components: Fuzzfcaton, Fuzzy Rule Base, Fuzzy Inference Engne, and Defuzzfcaton [1]. The fuzzfcaton process converts the real nput (usually error and change of error) to fuzzy unverse of dscourse to produce correspondng fuzzy nputs. These nputs are fed nto the fuzzy nference engne, where certan fuzzy rules comng from the fuzzy rule base are trggered accordng to the fuzzy nput varables. These trggered rules produce the output varable whch n turn s defuzzfed by the defuzzfcaton engne to the real world unverse of dscourse and the o/p s used as the plant nput [1]. Fgure 4 shows the desgn components for a fuzzy controller. Fg. 4 the desgn components of a fuzzy controller The mplemented fuzzy logc controller conssts of one fuzzy algorthm n whch the error and change of error are fed to the controller and nterpreted nto lngustc terms usng the fuzzyfre. Throughout the conducted tests, t was notced that usng the Gaussan dstrbuton membershp ISBN:

4 functon resulted n smoother control acton. Ths functon s descrbed by [1]: µ x = exp 1. m x / σ ( ) ( ) (( ) ) (6) where m s the center of the membershp functon (mean), σ s the wdth of the membershp functon (standard devaton) and x s the nput varable. The number of fuzzy sets that were used n the smulaton s seven, as smaller set dd not gve the desred smoothness whle larger fuzzy set requred larger tables and algorthms. They were dstrbuted normally along the unverse of dscourse for error, change of error and the control acton, as shown n fgure 5. where N s the number of the used nterval, µ s the degree of membershp of every output varable correspondng to each error, change of error, and sum of error group. U s the crsp o/p of the controller. Fg. 5 the membershp functon dstrbuton along the unverse of dscourse for the error, change of error and the output (U). Fg. 6 control surface of table II rules From ths fgure, t can be observed that there are seven lngustc fuzzy sets whch are: NB for negatve bg, NM for negatve medum, NS for negatve small, Z for zero, PS for postve small, PM for postve medum and PB for postve bg, CE for change of error and E s the error sgnal= output (measured) - nput (desred). The fuzzy rules were derved by experence and through the observaton of the control acton along wth the transent and steady state response and were checked aganst several desgn cases of Fuzzy controlled buck converters n order to mprove the rule table. Ths rule table s shown n table II. Table II FUZZY RULE SET IMPLEMENTED IN THE CONTROLLER DESIGN Ths table wll gve the control surface shown n fgure 6. For the defuzzfcaton process, the center of gravty method s used and s gven by [1]: U (7) E CE N = 0 = N µ = 0 NB NM NS Z PS PM PB NB NB NB NB NM NM NS Z NM NB NB NM NM NS Z PS NS NB NM NM NS Z PS PM Z NM NM NS Z PS PM PM PS NM NS Z PS PM PM PB PM NS Z PS PM PM PB PB PB Z PS PM PM PB PB PB ( u ). µ ( u ) u The desgned fuzzy controller performance has been tested aganst a tuned PID controlled buck converter to get the load regulaton characterstcs. In both cases the controller was subjected to load change from lght load (CPU core dle I Load =167mA) to Heavy load (CPU core full actvty I Load =597mA). The resultng transent response has been recorded and shown n fgure 7. Output Voltage Samplng Tme 1mSec PID Controller Fuzzy Controller Fg. 7 load change transent response of the buck converter when operated wth a PID controller (sold lne) and a fuzzy controller (dashed lne). The followng dfferences were observed: the PID controller was tuned to have response characterstcs that makes the end response fast wth an overshoot that would be lower than target load lmt set by the manufacturer, Ths PID controller had an overshoot that was about 6.5% form the output and that was wthn the allowable lmts set by the target load electrcal specfcatons, steady state was reached after 4.6mllSeconds and there was no measurable error n the steady state output. The fuzzy controller had a Lower overshoot that was 4.8% of the output and reached steady state after about 4.75 mllseconds and had a steady state error fgure of less than 0.3%. From these results, t can be concluded that: ISBN:

5 The Fuzzy controller had a lttle slower response than the PID controller. The Fuzzy controller had smaller overshoot than the PID controller. The Fuzzy controller had a small steady state error whle the PID controller showed no steady state error. The desgned fuzzy controller provded more flexble operatng performance sutable for a DVS ready system as changng the output voltage of the converter ddn t requre changng the fuzzy set rules whle the PID Controller requred retunng of ts parameters n order to yeld the same response characterstcs. V. CONCLUSION In ths paper a desgn for a buck converter sutable to supply the core of a DVS ready processor (PXA70) was proposed. Careful selecton of components was made n an attempt to boost converter effcency. Low ESR capactor and low leakage nductors n addton to selectng MOS devces wth very low FOM were chosen to mnmze power loss and enhance performance. Further more, the MOS gate drver devce chosen has a unque feature of dynamcally selectng dead zone between gatng the MOS swtch and the MOS synchronous rectfer thus resultng n better cross current preventon yeldng hgher effcency. The proposed mcrocontroller (ATmega169) has a very low operatng power n addton to a powerful RISC desgned nstructon set that permts performng good control functon whch s beng mplemented usng a fuzzy controller. Ths mcrocontroller has been ncorporated wth several seral buses, ths feature can ease the transacton between the man processor and the power management mcrocontroller n mplementng DVS functons. The proposed fuzzy controller performance was compared aganst a tuned PID controller. The results promote usng the fuzzy based controller wth much better flexblty and lower software overhead than the case when controller structure of another type would be suggested. The overall system effcency s expected to be hgher than 9% that can be mantaned over wde operatng condtons by Adaptng varable frequency PWM when operatng at dfferent output voltages and swtchng to PFM for low power loads. REFERENCES [1] Soto A,; Alou,p.; Cobos,J.A.; Uceda,J.; The Future DC-DC Converter as an Enabler of Low Energy Consumpton System wth Dynamc Voltage Scalng. IECON 0, IEEE 00 8 th. [] Perng T.; Burd T.; Brodersen R.; Dynamc Voltage Scalng and the Desgn of a Low Power Mcroprocessor System. ISCA [3] Soto A,; Alou,p.; Cobos,J.A.; Desgn Methodology for Dynamc Voltage Scalng n the Buck Converter. APEC 005, 0 th Annual IEEE. [4] Intel, PXA70 Processor, Electrcal, Mechancal, and Thermal Specfcatons. Data Sheet. [5] Intel, PXA7x Processor Famly Power Requrements. Applcaton Note. [6] ATmel, ATmega169 8-bt AVR mcrocontroller wth 16K Byte nsystem Programmable Flash. Data Sheet. [7] Mcrochp, PIC16F87XA Enhanced Flash Mcrocontroller. 003 Mcrochp Technology Incorporated. Data Sheet. [8] Wu K.C.; Pulse Wdth Modulated DC-DC Converters by Chapman & Hall ISBN [9] Mcrochp, Buck Converter Desgn Example. 006 Mcrochp Technology Incorporated. Applcaton Note. [10] Freescale, Selectng L and C Components n Power Stage of Swtchng Regulators. 010 Freescale Semconductors Incorporated. Applcaton Note. [11] Texas Instruments, NexFET Power MOSFETs Quck Reference Gude. 010 Texas Instruments Incorporated. Data Sheet. [1] Texas Instruments, UCC7 Hgh Effcency Synchronous Buck Gate Drvers. 003 SLUS486b Texas Instruments Incorporated. Data Sheet. [13] Jauregu D.; Wang B.; Chen R.; Power Loss Calculaton wth Common Source Inductance consderaton for Synchronous Buck Converters. SLPA Texas Instruments Applcaton Report. [14] Guo L.; Hung J.Y.; Nelms R.M.; Evaluaton of DSP-Based PID and Fuzzy Controllers for DC_DC Converters. IEEE Transactons on Industral Electroncs Vol. 56 No.6 June 009/ [15] Zahng Z.; Maksmovc D.; Dgtal PWM/PFM Controller wth Input Voltage Feed-Forward for Synchronous Buck Converters. APEC rd Annual IEEE. [16] Dhar S.; Maksmovc D.; Swtchng Regulator Wth Dynamcally Adjustable Supply Voltage for Low Power VLSI. IECON th Annual Conference of the IEEE ndustral Electroncs Socety. [17] Gupta T.; Boudreaux R.R.; Implementaton of a Fuzzy Controller for DC-DC Converter Usng an Inexpensve 8-b Mcrocontroller. IEEE Transactons on Industral Electroncs. Vol. 44, No. 5, October [18] Hart D.W.; Introducton to Power Electroncs, Prentce Hall Inc [19] Mohan N.; Underland T.M.; Robbns W.P.; Power Electroncs: Converters Applcatons and Desgn, John Wley and Sons [0] Su J.H.; Chen J.J.; Learnng Feedback Controller Desgn of Swtchng Converters Va MATLAB/SIMULINK. IEEE Transacton on Educaton Vol.45 No.4 November 00. [1] REZNIK L.; Fuzzy Controllers. Newnes, 1997.ISBN [] Jan S.; Azad M.; Modelng and Smulaton Usng MATLAB- SIMULINK. 011 Wley-Inda ISBN Monaf Sabr Tapou s a Lecturer n the Control and System Engneerng Department Unversty of Technology Baghdad. He was born n He earned hs BSc. degree n Electroncs Engneerng from the Electrcal Engneerng Department Unversty of Technology Baghdad n 1981, M.Sc. degree n Computer Engneerng from the Control and System Engneerng department Unversty of Technology Baghdad n He s currently conductng a PhD. Research n the School of engneerng and Desgn, Brunel Unveersty. Hs research nterest s n nvestgatng n low power technques n modern computer systems. He can be contacted at ths emal: monaf.tapou@brunel.ac.uk. Hamed Al-Raweshdy s a research professor and the head of the Wreless Networks & Communcatons Research Group n the School of Engneerng and Desgn at Brunel Unversty. Hs research nterests nclude network optmzaton, mesh and ad hoc networks, rado over fber, PAN and PN, and IP moblty. He receved hs PhD for work n spread spectrum multplexng for communcaton networks. He holds a number of projects wth EPSRC and EU. He s a senor member of the IEEE, an IEE fellow, and a member of New York Academy of Scences. Contact hm at the Wreless Networks & Communcatons Group, School of Eng. and Desgn, Brunel Unv., Uxbrdge, Mddlesex UB8 3PH, UK; Hamed.Al- Raweshdy@brunel.ac.uk. Maysam Abbod was born n He has fnshed hs BSc degree n electroncs from the Unversty of Technology, Baghdad n 1987 and PhD degree n Control Engneerng for the Unversty of Sheffeld n 199. Hs research work s of a mult-dscplnary nature rangng from bomedcal applcatons to ndustral applcatons. He has been a Research Fellow workng for the Insttute for Mcrostructural and Mechancal Process Engneerng, The Unversty of Sheffeld (IMMPETUS) on modelng of materal propertes usng hybrd modelng technques. Hs research nterests nclude ntellgent systems for modelng and optmzaton. Currently he s a lecturer n Intellgent Systems n the School of Engneerng and Desgn, Brunel Unversty. Dr Abbod s a member of the IET and Chartered Engneer. Hs emal address: maysam.abbod@brunel.ac.uk Dr. ManalJ. AL-Knd s an Asstant Lecturer currently workng at the Department of Electrcal and Electronc Engneerng - Al-Nahran Unversty Baghdad. He had hs BSc. Engneerng from The Electercal Engneerng Department Unversty of Technology Baghdad. He obtaned hs PhD. From Unversty of Strathclyde Glasgow UK. He can be contacted thorugh ths emal address: Manal alknd@yahoo.com ISBN: