COLLEGE OF ENGINEERING ROORKEE (COER)

Transcription

1 COLLEGE OF ENGINEERING ROORKEE (COER) Department of Electronics and Telecommunication Engineering Lab Manual OF Fundamental of Electronics Engg Lab(PEC-101/201)

2 LIST OF EXPERIMENTS FUNDAMENTALS OF ELECTRONICS ENGINEERING LAB (PEC-101/201) BTECH FIRST YEAR (COMMON TO ALL BRANCHES) 1. STUDY OF POWER SUPPLY, CRO, FUNCTION GENERATOR AND MULTIMETER. 2. STUDY OF PN-JUNCTION (SI& GE) DIODES. 3. STUDY OF ZENER DIODE(BREAKDOWN MECHANISMS). 4. STUDY OF HALF WAVE & FULL WAVE RECTIFIERS. 5. STUDY OF CLIPPERS AND CLAMPERS. 6. STUDY OF BJT TRANSISTOR 7. STUDY OF LOGIC GATES 8. STUDY OF UNIVERSAL LOGIC GATES. 9. STUDY OF OPAMP APPLICATIONS.

3 Experiment 1 OBJECT-: STUDY OF CRO, FUNCTION GENERATOR AND MULTIMETER. APPARATUS REQUIRED-: CRO, FUNCTION GENERATOR AND MULTIMETER AND CONNECTING PROBES. THEORY-: TECHNICAL SPECIFICATION ',WORKING MODES:- Channel -I, Channel-II, channel I&Il Alternate, ADD/SUB, invert CH-II. TIME.1BAciE:- 13 calibrated steps 0.5µs/cm -.2s/cm with magnifier 5 to with variable control.50/.40 ns/cm. Accuracy ± 3% out put.5vpp (app) COMPONENT TESTER Test. Voltage Max-8.6Vrms test current max 8mA rms (shorted) test frequency 50HZ Test circuit grounded to continuity tester. Beeper sound 100 Ohm (approx.) 411 "GENERAL INFORMATION- Cathode ray tube Rectangular medium short resistance. 414 Accelerating potential 2000V Display: 8*10 CM. Trace rotations adjustable on front panel. CALIBRATOR:- Square wave generator 1 khz, 0.2 V for probe compression The protection is likely to be impaired if for example the instrument - Shows visible damage. - Fails to perform intended measurement. - Has been subjected to prolonged storage under unfavorable conditions. - Has been subjected to sever transport stresses. Z- Modulation:- TTL level stabilized. Power supply all operating voltages including HT, mains voltage Hz. Fluctuation- 10% Power consumption: 33 VA Weight 7.5 kg. Dimension Operating temperature 40. 'NZ ROSTT PANEL CONTROLS:- POWER ON/OFF - Push button switch for supplying power to instrument. XS: switch when pushed inwards gives magnification of x signal. XY: Switch when pressed cuts the time base and allows across the external horizontal signal to be fed through CH --II CH-I / CH -I CH-II. Switch when selected trigger CH I and when pressed selects and trigger CH-11. vaz-- MONO DUAL - Switch selects the dual operation. Q ALT/CHOP/ADD - Selects alternate or chopped in dual mode. If MONO is selected it starts addition or subtraction of channel. TIME /DIV:- It selects the time speeds controls the trigger level peak-to-peak amplitude of signal. TIG 1N-P:- feeds external trigger signal in ext. mode. CAL,OUT:----C-k4out for square wave. Allows external triggering signal to be fed form, select marked TRIG INP. X.POS:- Controls horizontal position of the trace. VAR :- Controls time speed in between two steps oftime/div switch. TV:- Allows video signal from frequency up to 20 khz to be locked. TENS:- Controls the brightness of trace. F:..._:;)COLIS-:---Gontrols the sharpness of trace. CT:- Switch when pressed starts CT operation. AC/G0:- Input coupling switch for each channel. In AC through 0.1,ifF capacitor. B p CONTROLS: - 1. FUSE: ma fuse is panel spare fuse are provided inside the instrument.

4 Z-Mode:- amana socket provided for modulating signal input the signal is coupled provided at the back. ---FUNCTION GENERATOR:- Frequency range.1 hz to 1MHZ Operating models:- SINE,SQUARE TRIANGLE,DC 30 V PEAK signal out put, Display for frequency and amplitude. FM input sweep, mode. The various signals available from the SM 5060 function generator e it a versatile signal source useful for most measurement and test applications. Its low frequency range is particularly well suited for stimulated and serve techniques) Frequencies are read out on a $ digit LED display controls facilities accretes. Frequency adjustment, additional quality features include the relatively low, distortion factors of the generator of the generated signals and without constant amplitude flatness through the entire frequency of instrument FRONT PANEL CONTROLS- 1- Power: push button switch for suppling power to instruments 2- DIGITAL DISPLAY-4 digit, 1 frequency, 1 'amplitude meter LED indicates for Hz, KHz, my and v 3- freq/ amp: selects display of frequency or amplitude. 4- AMP: continuous adjustment of the output amplitude from 0 to 20 db. 5- output BNL connector- short ckt proof signal output of the generator the output impedance if.5011 switch selectable max. output amplitude amounts to 30Vpp or 15 Vpp respectively /60011 Push button when switched else.500 is released position. 7-FVAR- Continuous and linear frequency adjustment from.1h2 to 1M1I2in steps; selecty with freqiiency-rniage. 8- VAR- When trigger output is selected in CMOS output can be set with VAR to approx. l5vp. 9- ITL/CMOS- Switch selects trigger output TTL or CMOS. MULTIMETER: Theory- The new scientific hand held DMM roll is a compact light. weight and "TRULY MULTI" multimeter. The high class engineering and rugged design. RESISTANCE: Insert b back lead into 'COM' and red into P/M terminal. Set the switch to R position. Auto/0.00 mfl appears with MCB if the resistance being measured is connected to circuit. Remove power from the circuit being tested and discharge all capacitors. SAFETY RULES: Never exceed the following: D. C. volts 1000V AC volts 750 V Ohms ma 200 ma COM '.1.41o,;t more than 100V from earth 1) Never raise to a multimeter with battery compartment open 2) Always insure light and Observe the above written s way rules. 2) Remove the batt eries to prevent leakage when not in use for longer direction. RESULTS: Studied the performance of CRO multimeter and function generator.adequate connecting 3) Remove test leads before replacing batteries fuses and saving.

5 EXPERIMENT -2 OBJECT: To study V-I characteristics of a P-N junction diode. APPARATUS REQUIRED Diode operating board, connecting wires, battery. THEORY : Diode, electronic device that allows the passage of current in only one direction. The symbol of P-N junction diode is shown in fig. (1). As show in fig. (1).a semiconductor diode has two terminals. It conducts only when it is forward biased i.e. when terminal connected with arrowhead is at higher potential than saw' the terminal connected to the bar. However, it is reversed biased, practically it does not conduct any current through it. The V-I characteristic of P-n junction is just a curve between voltage across the Junction and the circuit current. When the positive terminal of a DX source is connected to positive terminal of,node and negative terminal is connected to negative terminal of diode is called forward biasing.

6 When the positive terminal of a ILC source is connected to negative terminal of diode and negative terminal of D.C source is connected to.} Positive terminal of diode.. RESULT In forward biasing the current increases very slowly and the curve is non linear till potential barrier (0.3V for Ge and.7v for Si). After this barrier potential a small increment in voltage make a major change in current. In reverse biasing a very small current of the order of microamperes flows through the circuit. And after breakdown voltage a large current flows through the circuit. PRECAUTIONS + Use all instruments properly. All connection should be right and tight. Take readings carefully.

7 EXPERIMENT 3 OBJECT: To plot V.I. characteristics curve for Zener Diode. APPARATUS REQUIRED: Zener Diode kit, connecting wires, milliammeter and voltmeter. THEORY: A PN junction diode normally does not conduct when reverse biased. But if the reverse bias is increased at a particular voltage it starts conducting heavily. This voltage is called breakdown voltage. To avoid high current, we connect a resistor in series with it. Once the diode starts conducting it maintains almost constant voltage across its terminals whatever may be the current through it. That is, it has very low dynamic resistance. A zener diode is a pn junction diode, specially made to work in the breakdown region. It is used in voltage regulators. PROCEDURE: 1. Make circuit connections as given in fig Note type and number' of the zener diode from the experimental board.

8 3. Note the value of current limiting resistor. 4. Connect milliarnmeter and voltmeter of range 100mA and 60V. 5. Measure Input applied voltage using multimeter or CRO. 6. Switch on the power supply. Increase slowly the supply voltage. In steps measure the voltage V1 and Vz and current Iz. Once breakdown occurs, Vz remains fairly constant even though Iz increases. 7. Plot the graph between Vz and Iz and compare this graph with the expected one as shown in fig.2. OBSERVATION TABLE:

9 RESULT: PRECAUTIONS: 1. The equipment should be dealt with care. 2. Connections should be made tightly. 3. Silence should be maintained in the laboratory while performing the experiments. 4. The ratings of current and voltage to be supplied to the equipment should not be exceeded.

10 EXPERIMENT 4 OBJECT: - To study of a I. Half wave rectifier circuit. II. Full wave center tapped rectifier circuit. Bridge-erectifier circuit And determination of the ripple factor. Apparatus required: - CRO, Electronic multimeter, diodes and resistors, Connecting wires, bread board, and power supply. Theory:- A diode conducts in one direction only, In another direction it doesn't conduct. This property of a diode can be made use of in converting an alternating voltage into a D.C. voltage. The circuits accomplishing this phenomenon are known as rectifiers. The various types of rectifiers are 1. Half wave rectifier. 2. Full-wave center tapped rectifier. e ectifier. Half-wave rectifier: - Figure 1 depicts a half wave rectifier. Let the input to this rectifier circuit be a sinusoidal signal. During the positive half cycle of the input signal, the diode is forward biased and conducts. The current completes its path through the load resistance RL. The voltage across RL has the same shape as to that of the input signal: During the second half of the input signal wave i.e. negative half cycle, the diode is reverse biased and therefore doesn't conduct. This has been depicted in fig. 1. The average value of any voltage is the value measured by a D.C. voltmeter. The average value of the half wave rectified output voltage Va can be determined using Va =Vmhr = Vm Where Va-, is the maximum value of the voltage. Full-wave center tapped rectifier: -In case of a full wave rectifier, the output voltage appears across the load resistance for the full cycle. The average value of the output of the full wave rectifier would be double to that of the half -wave rectifier i.e. Va = 2Vm / Ir =0.637 Vm A center-tapped full wave rectifier has been depicted in fig 2. During the positive half cycle of the input signal the diode DI is forward biased and conducts, but the diode D2 is reverse biased and doesn't conduct. The current completes it

11 path through the Di and R1 giving an out voltage similar to the input voltage. On the other hand during negative half cycle of the input voltage, the diode D2 is forward biased and conducts. Whereas the diode D1 is reverse biased and doesn't conduct. The voltage similar (but in the reverse direction) to the input voltage. We know that for the transformer ratio as 1:1, only half of the primary voltage appears across each half of the secondary winding Therefore, And Vsec = Vpri Vout =Vsec/ 2 Full-wave bridge rectifier:-it employs four diodes as shown in fig. 3. For the positive half cycle of the input signal, the diodesd1 and D2 are forward biased whereas the diodes D3 and D4 are reverse biased. The current completes circuit through the path A DI BRL D2 C. A voltage is developed across RL This is similar to the positive half cycle of the input voltage. On the other hand for the negative half cycle of the input voltage. The diodes D3 and D4 are forward biased whereas the diodes DI and D2 are revered biased. The current completes the circuit through the path C D4B RL D3 A. In this case a voltage is developed across RL which is with the reverse polarity to that of input voltage. This way a full-wave rectified output appears across RL. For a transformation ratio of 1:1 for the transformer we have Vm (in) Vm (pri) Vm (sec) Vm (out) If the diode drops are taken into account, we have, Vm (out) Vm (sec) -1.4 V Note the figure of 1.4 V on the rms of the above equation; it is because two diodes are in series at any instant of time. The peak inverse voltage, PIV which any of the diodes should be capable of withstanding remains Vm (out). It can be appreciated that a bridge rectifier requires diodes with half the PIV rating of those required in case of a Center-tapped full wave rectifier or the same output voltage.

12 A Ripple factor: - It is a measure of purity of the D.C. output of a rectifier. Mathematically it is defined as, r = r.m.s. value of the wave /average or D.C. value =11'21 for half wave rectifier =0482 for a full wave rectifier. Procedure:- The experiment can be performed in the following steps. 1. Connect the circuit as shown in fig. 1(b) 2. Observe the wave shapes of the input voltage and the output voltage of the rectifier circuit. Plot these shapes on your note book. 3. Using multimeter measure the following quantities. I. A.C. voltage at the input. This gives rms value. II. A.C. voltage at the out put points. III. D.C. voltage at the out points. This gives average value. 4. Obtain the peak value by multiplying the rms value by A/2. Calculate the average value using eqn. (1) compare this value with the measured value of D.C. voltage. 5. Using the observed values of A.C. out put voltage and D.0 out put voltage, calculate ripple factor. It should come out to be 1.21 for a half wave rectifier. 6. Repeat step 1 to 5 for other rectifier circuit using corresponding figures and equations for calculation. Observations and calculations ;- S.N. Measured values Calculations A.C. voltage input D.c. voltage at output A.C. voltage at output Vav Precautions:- 1. All connection should be neat and right & tight 2. CRO should be handled carefully. 3. Turn off the power supply when it is not needed.

13 Experiment- 5 OBJECT: Study of clipper and clamper circuits using,different waveforms. APPARATUS REQUIRED: 5V 'DC power supply, diodes, resistors, capacitors, function generator, CRO, bread board, connecting wires, connecting leads. THEORY: CLIPPING CIRCUITS: Clipping circuits are used for transmitting a part of the signal that lies above/below a reference line. Precisely, clipping circuits are employed to fulfill any of the following requirements: (i) To cut off positive/negative part of any signal. (ii) To convert a sine wave into a rectangular wave. In clipper circuits we make use of the behavior of a diode as a switch. These are also known as amplitude limiters or simply LIMITERS. Fig.1 below shows a clipper circuit which cuts off the positive part of the input signal. During the positive half cycle of the input signal, the diode is forward biased, therefore, the diode conducts. Upto the point input signal attains a magnitude of 0.7V (for silicon diode),the voltage across diode remains of the same shape as that of the input signal. Fig.2.NEGATIVE CLIPPER (a) INPUT SIGNAL (b) THE CIRCUIT (c)output SIGNAL However, instead of completely clipping off a part of input signal, if we are interested in clipping off a portion of the input signal above a specified level, the objective can be attained by using a bias D.C.

14 voltage in series with the diode. Such circuits alongwith the input signal waveform and the output signal waveform have been depicted in FIG.3 & 4. Fig.3.POSITIVE CLIPPER WITH BIAS (a) INPUT SIGNAL (b) CIRCUIT (c) OUTPUT SIGNAL Fig.4.NEGATIVE CLIPPER WITH BIAS (a) INPUT SIGNAL (b) CIRCUIT (c) OUTPUT SIGNAL

15 CLAMPING CIRCUIT: A clamping circuit holdspither peak of an A.C. voltage to a definite level without distorting the. waveform, tramping may be positive or negative. A positive clamping circuit shifts the signal in positiv side so that the negative peak of the signal falls on the zero level of the output signal. A negative clamping circuit shifts the signal in negative side so that the positive peak of the sgnal falls to zero. Clampers are also known as DC RESTORERS. Fig.1 depicts a positive clamper. It inserts a positive d.c. level. Consider the first negative half cycle of the input signal. The diode becomes forward biased. As a result the capacitor gets charged to a voltage (Vm-0.7), where Vm represents the maximum value (peak) of the input signal. In the time immediately following the negative peak, the diode becomes reverse biased. The only path for the capacitor to discharge is through the load resistance which is very high. For. good clamping action, the time constant should be about ten times the period of input signal. The result is that the capacitor remains charged and stays at a voltage (Vm -0.7). This is equivalent to putting a battery in series with the input signal. This justifies the output waveform as shown in FIG.1. A negative clamper has been depicted in FIG.2. V

16 PROCEDURE: The experiment can be performed in the following steps: 1. Make the connections as shown in the fig.1 above. 2. Select the sine wave as input to the circuit from function generator. 3. Connect the output of the circuit to the CRO. 4. Observe the output waveform on the CRO by adjusting tirne/div. and voltage/div. switches of CRO. 5. Repeat steps 2 to 4 for other clipper and clamper circuits given in figures above for different waveforms. OBSERVATIONS: Draw the waveforms observed on CRO and compare these with the waveforms shown in FIG.1 to 6 PRECAUTIONS: Following precautions should be taken care off while performing this experiment. 1. All the connections should be neat and tight. 2. Turn off the power supply, when.it is not needed. 3. CRO should be used carefully.

17 Experiment-6 Object: - Determination of characteristics of BJT in CB&CE Configuration. Apparatus required:-transistor, power supply, milliameter, voltmeter, bread board, and potentiometer. Theory:- A transistor is a three terminal active device; the three terminals are emitter, base, and collector. Common Base configuration:-in CB configuration we make the base common to both emitter and collector. Input characteristic;- It is the curve of I/P current verses I/p voltage for a given 0/P voltage. Output characteristic:- It is the curve of the 0/P current verses 0/P voltage for a given I/P current. The figure 1 depicts the PNP transistor in CB configuration. Figure 2 depicts the I/P characteristic of PNP transistor in CB configuration.

18 Figure 3 depicts the 0/P characteristic of a PNP transistor in CB configuration.

19

20 Common emitter configuration In this configuration emitter is common to both base & collector. Input characteristic-it is the curve between I/P current versus I/P voltage for a given 0/P voltage. 0/P characteristics:- It is the curve between 0/P current versus 0/P voltage for a given I/P current. The figure4 depicts the PNP transistor in CE configuration. C.

21

22 Figure 5 shows the I/P characteristic of CE Configuration and figure 6 shows the 0/P characteristic of CE configuration. Procedure :-1. Connect the circuit as shown in figure 4. For UP characteristic 1. Adjust VcE by varying R2. Note this value. 2. Vary VBE with the help of R1 & note different values of IB. 3. Repeat step 2 to 3 for different values of VCE. For 0/P characteristic 4. Fix IB by varying R& note this value. 5. Vary Vce by varying R2 & note different value of lc 6. Repeat step 5 to 6 for different value of IB

23 The values of voltages VBE and VcE should be changed in small steps. Result: - Successfully determined the I/P & 0/P characteristic of PNP transistor in CE & CB Configurations. Precaution:-1. All connection should be neat & right. 2. Check/adjust the zero settings of the meters before connecting them in the circuit. 3. The current rating of the transistor shouldn't be exceeded.

24 OBJECT- Study of various logic gates. EXPERIMENT NO-7 APPARATUS- IC's of various gates, bread board, LED, connecting wires, battery. THEORY- Boolean expression contains sum and product of one or more literals. OR- GATE- The OR gate performs logical addition known as OR function. Output occurs when any or all of the inputs are high. OR gate has single output and can have any number of inputs greater than one. The output is 1 only if any one or all the inputs are 1. Figl shows the standard symbol of OR gate. Table 1 shows the truth table. (Fig. 1 OR GATE) The truth table is a tabular form of all inputs and their corresponding outputs. IC 7432 is an OR- gate IC. Its pin diagram has been depicted in fig. 2 Fig. 2 Pin diagram for IC 7432

25 The AND gate performs logical multiplication known as AND junction. Output occurs when all the inputs are high. AND gate is composed of two or more inputs and only oneoutput. This output is active (1) when all the inputs are 1. Fig 3 shows the standard symbol of AND gate with 2 inputs and 1 output. Table 2 shows the truth table. Fig.3 AND GATE) Table 2-Truth table for AND Gate AND operation is indicated by a dot (.) or a cross(x) placed in between the symbols. E.g. Y= A.B.0 = AxBxC IC 7408 is 2 input AND gate IC. Its pin diagram has been depicted in fig. 4 NOR- GATE- Fig. 8 Pin Diagram for IC 7400 The term NOR came from contraction of NOT-OR. It performs an OR function with an inverted o/p. The o/p of NOR-Gate is opposite of OR gate. This means o/p of NOR gate ti is HIGH only when all the inputs are L04. NOR gate is composed of two or more inputs and only 1 o/p. This o/p is low(0) when any one of the inputs is HIGH(1)., (Fig. 9 NOR GATE) Table 5-Truth table for NOR Gate IC 7402 is 2 input NOR-Gate. Fig 10 depicts the pin diagram for this IC. X-OR GATE-

26 Fig. 10 Pin Diagram for IC 7402 The term X-OR came from contraction of EXCLUSIVE -OR. The circuit of this gate is also called as inequality comparator or detector because it produces a HIGH o/p only, Fig. 4. Pin diagram of IC 7408 INVERTER NOT- GATE)- The NOT gate performs logical Negation known as NOT function. In other words NOT gate is an inverter. Output is high when input is low and vice versa. It has a single input and a single output. Fig 5 shows the standard symbol of NOT gate. Table 3 shows the truth table. The symbol to show a logic negation is a small circle at the point where a single line joins standard logic symbol. NOT : operation is indicated by a bar(-) or by a prime('). IC 7404 is an INVERTER IC. Fig 6 depicts pin diagram for this IC

27 Fig. 6 Pin Diagram for IC 7404 The term 'NAND" came from contraction of NOT- AND. It performs an AND function with an inverted output. The output of NAND gate is opposite of AND gate. This means output of NAND gate is high when any one, two or all inputs are low and output is low.only when all the inputs are high. NAND gate is composed of two or more inputs and only one output. This o/p is low (0) when all the inputs are high (1). Fig.7 shows the standard symbol of NAND gate with 2 inputs and 1 output. (Fig 7 NAND GATE) Table 4-Truth table for NAND Gate Table 4 shows the truth table. IC 7400 is a 2 input NAND gate IC.

28 NOR- GATE- Fig. 8 Pin Diagram for IC 7400 The term NOR came from contraction of NOT-OR. It performs an OR function with an inverted o/p. The o/p of NOR-Gate is opposite of OR gate. This means o/p of NOR gate it is HIGH only when all the inputs are Low. NOR gate is composed of two or more inputs and only 1 o/p. This o/p is low(0) when any one of the inputs is HIGH(1). Table 5 shows the truth table of NOR gate.

29 Table 5-Truth table for NOR Gate IC 7402 is 2 input NOR-Gate. Fig 10 depicts the pin diagram for this IC. X-OR GATE- Fig. 10 Pin Diagram for IC 7402 The term X-OR came from contraction of EXCLUSIVE -OR. The circuit of this gate is also called as inequality comparator or detector because it produces a HIGH o/p only when the two of its inputs are different.output of this gate is HIGH(1) if either of its input but not both is HIGH(1). The o/p is LOW(0) when the i/ps are same. Fig 11 shows the standard symbol for 2 i/p and 1 o/p. (Fig. 11 X-OR GATE) Table 6 shows the truth table of 2 input X-OR gate IC 7486 is a 2 input X-OR gate IC. Its pin diagram is shown in fig.13 Table 6-Truth table for X-OR Gate

30 Fig. 13 Pin Diagram for IC 7486 PROCEDURE-This experiment should be performed in the following steps. OR-GATE 1. Place the 2 input OR-gate 7432 lc on the bread board. 2. Connect the pin 14 to positive, terminal of battery (5v) and pin 7 should be :'rounded. 3. Let us consider the first gate connected between the pins 1, Put one wire in pinl and 2 each for inputs mark them as A, B. 5. Connect a LED between pin 3 and 7 to show the o/p (when LED glows it indicates HIGH or 1) 6. Nov make the truth table by inserting all combinations of inputs & noting the corresponding o/p. To insert the input logic as (1) connect the input wire to positive terminal of battery and to insert the logic as (0) connect to negative terminal of battery. AND - GATE 1. Place the two input AND gate 7408 IC on bread board. 2. Repeat steps 2 to 6 as given for OR- Gate. NOT GATE Place the 7404 IC on the bread board. Connect the pin 14 to positive, terminal of battery (5v) and pin 7 should be grounded. 3. Let us consider the first gate connected between the pin 1 and Put a wire in pin 1 for input & mark it as A. 5. Connect the LED between pin 3 and 7 to show the o/p. 6. Now make the truth table by inserting inputs & noting the corresponding outputs.

31 NAND GATE 1. Place two input NAND gate IC 7400 on the bread board. 2. Repeat steps 2 to 6 as given for OR gate. NOR GATE 1. Place two input NOR gate IC 7402 on the bread board. 2. Repeat steps 2 and 3 as given for OR gate. 3. Put one wire in pin2 and 2 each for inputs mark them as A, B. 4. Connect a LED between pin 1 and 7 to show the o/p (when LED glows it indicates HIGH or 1) 5. Now make the truth table by inserting all combinations of inputs & noting the corresponding o/p. X-OR GATE 1. Place two input X-OR gate IC 7486 on the bread board. 2. Repeat steps 2 to 6 as given for OR gate. OBSERVATIONS- Following the steps as given in procedure the observed truth table should be as follows. Truth table for 2 input OR gate

32 EXPERIMENT 8 OBJECT: -To implement different gates using NAND Gate and NOR Gate. APPRATUS: -NAND gate IC 7400, NOR gate IC 7402, bread board, LED, Connecting wires and battery (5V) THEORY:- Implement using NAND gate. NAND gate can be used to produce any logic function that is why it is referred to as universal gate. NAND gate can be used to generate the AND, OR, NOT, NOR, X-OR and X-NOR function To implement NOT Gate NOT gate can be made from NAND gate by connecting all its input together and getting a single output as shown in the Fig.1 Since both the inputs are tied together both have same input voltages when input A is at OV (low) output Y is at 5V (high) and when input is at IV (high) output y is at OV (low). This shows the circuit is equivalent to an inverter circuit. AND gate can be made from NAND gate by connecting the inputs of second gate together and getting a single output as shown in the Fig. 2.

33 Output of the first NAND gate is AB. By connecting another NAND gate with all its inputs shorted to the first NAND gate, the output of first gate is inverted; we get which is the logic function of AND Gate. Y = (A.B) = AB To implementation OR-Gate OR gate can be made from NAND gate. By connecting an inverter to each input. Then their output is connected to third NAND gate, getting a single output as shown in Fig. 3. The inputs are inverted separately, using the NAND gates with shorted inputs. The inverted inputs are then applied to another NAND gate to give the logic function of an OR gate. In this circuit input NAND gates act as inverters and output NAND gate acts as bubbled OR-gate. The double inversion cancels and circuit is equivalent to OR gate. The output we get is (A.B)' which can be proved by De Morgan's theorem equals A+B. A.B)' = (A)'+ (B)'=A+B

34 To implement X-OR Gate X-OR gate can be made from NAND gate using five NAND gates as shown in Fig Two NAND gates with shorted inputs which work as inverters are used to complement the input signal..the output of these gates and a direct input are fed to two separate NAND gates. The outputs of these gates are applied to another NAND gate. The final output we get is A+B To implement X-NOR Gate X-NOR gate can be made using six NAND gates as shown in fig. 5 using five gates in the same manner as for X-OR as explained above. The sixth gate is used to invert the output of the five gates. The final output we get is =A B + AB Which is the logic function of an X-NOR gate

35 Implement using NOR gate NOR gate can be used to produce any logic function that is why it is referred to as universal gate. NOR gate can be used to generate the AND, OR, NOT, NOR, X-OR function. To implement NOT logic gate The circuit diagram is as shown in fig.6 Y=A Inverter logic can be obtained from NOR gate by connecting all its input together and getting single output

36 NOR gate can be used to produce any logic function that is why it is referred to as universal gate. NOR gate can be used to generate the AND, OR, NOT, NOR, X-OR function. To implement NOT logic gate The circuit diagram is as shown in fig.6 Y = A, Inverter logic can be obtained from NOR gate by connecting all its input together and getting single output. NOR gate can be used to produce any logic function that is why it is referred to as universal gate. NOR gate can be used to generate the AND, OR, NOT, NOR, X-OR function. Inverter logic can be obtained from NOR gate by connecting all its input together and getting single output.

37 To implement AND gate We make the logic of AND gate using three NOR gates. Inverting both the inputs using two different NOR gate with their input shorted,. Output of these gates are fed to as input of third NOR gate whose output is equal to the AND logic function i.e. product of the input signals. Circuit is shown in Fig. 7 The logic function of AND gate is Y = AB To implement OR gate We require only two gates to implement OR logic. Two input signals A and B are fed in a NOR gate. Output of the first gate is connected to the input of the second gate which is in an inverter configuration and complements the output of first gate. This gives the logic function of an OR gate i.e. Y=A+B

38 Procedure:- This experiment should be performed in the following steps. 1. Take the NAND gate and NOR gate IC 7400 and 7402 respectively and check it. 2. Fix the IC'S on bread board and connect the pin 7 to the negative terminal of battery and pin 14 to positive terminal as required. 3. Make the connection as shown in fig 1 for NOT gate, fig 2 for AND gate fig. 3 for OR gate, fig. 4 for X-OR gate and fig 5 for X-NOR as required for IC 7400 and fig.6 for NOT gate, fig 7 for AND gate, fig. 8 for OR gate, fig. 9 for X-OR gate as required for IC To observe the output connect the LED between Y and ground i.e. connect positive of LED to Y and negative to negative terminal of battery. 5. Note the observation in the form of truth table with different input conditions and verify from ideal truth table of different gates.

39 Observations. The observed truth table of different gates is same as the ideal truth table. Precautions Following precautions should be taken care of while performing this experiment. 1. LED's should be checked before using 2. Wires used should be short and connected properly. 3. The input voltage should kept constant during the experiment. Result We have implemented the logic functions of all gates using only NAND gate and NOR gate. So we can call NAND gate and NOR gate as a UNIVERSAL GATE.

40 Object:- Study of OPAMP -741 applications EXPERIMENT NO.9 Appartus Required:-Bread board,ic-741,connecting wires, power supply, resistors, Theory: An operational amplifier (op-amp) is a DC-coupled high-gain electronic voltage amplifier with a differential input and, usually, a single-ended output. An op-amp produces an output voltage that is typically hundreds of thousands of times larger than the voltage difference between its input terminals. OPAMP AS A DIFFERENTIATOR Differentiator is a circuit that is designed such that the output of the circuit is approximately v proportional to the rate of change (the time derivative) of the input. An active Differentiator includes some form of amplifier. A passive differentiator circuit is made of only and capacitors. Output is proportional to the time derivative of the input Hence, the op amp acts as a afferentiator; - The minus sign indicates the phase difference of 180 degrees between the output and the input; Above equation is true for any frequency signal.

41 OPAMP AS AN INTEGRATOR Integrator is a device to perform the mathematical operation known as integration. Amplifier is a very flexible circuit based upon the standard Inverting Operational that can be used for combining multiple inputs. We saw previously in amplifier tutorial that the inverting amplifier has a single input voltage, ( Vin ) lie inverting input terminal. If we add more input resistors to the input, each equal in original input resistor, Rin we end up with another operational amplifier circuit a S_-:-.ming Amplifier, "summing inverter" or "voltage adder" circuit as shown Fig.

42 OPAMP AS SUBTRACTOR Differential amplifiers amplify the difference between two voltages making this type of operational amplifier circuit a Sub tractor unlike a summing amplifier which adds or sums together the input voltages. This type of operational amplifier circuit is commonly known as a Differential Amplifier Procedure: 1. Place the IC in a breadboard. 2. Connect Resistors & Capacitors according to ckt. 3. Connect Internal power supply through pin 5,2,6. 4. Give the External input through pin Get the output through pin 7. * -observation: To design and implementation only. Hence we have studied operational amplifier as various applications using IC-741

43 Procedure: 1. Place the IC in a breadboard. 2. Connect Resistors & Capacitors according to ckt. 3. Connect Internal power supply through pin 5,2,6. 4. Give the External input through pin Get the output through pin observation: To design and implementation only. Hence we have studied operational amplifier as various applications using IC-741