A Novel General Purpose Current Mode Oscillating Circuit for the Read-Out of Capacitive Sensors

Transcription

1 A Novel General Purpose Current Mode Oscillating Circuit for the Read-Out of Capacitive Sensors A. De Marcellis, C. Di Carlo, G. Ferri, V. Stornelli Department of Electrical and Information Engineering, University of L Aquila, Monteluco di Roio, L Aquila, Italy Tel.: , Fax: ; giuseppe.ferri@univaq.it Abstract In this paper we present a novel general purpose current mode (CM) solution for the interfacing of capacitive sensors. The designed circuit, which utilizes only two second generation current conveyors (CCIIs) as active blocks, allows to detect, through a capacitance-to-time conversion (C-T), capacitive values as well as their variations (also lower than 1pF) both in a small and a wide range. Its main operation is based on a current differentiation, instead of voltage integration, typical of interfaces developed in the voltage-mode approach. The proposed circuit, which does not need any initial calibration, has been designed as integrated solution at transistor level in a standard CMOS 0.35µm technology. Waiting for the chip fabrication, preliminary experimental results have been performed through a discrete-component board and sample capacitors and resistors. Both simulation and experimental results have shown low percentage errors and a good agreement with theoretical expectations for more than five frequency decades. The system sensitivity has been set to about 1.8µs/pF. Introduction With the development of microelectronic technologies in silicon, new applications of research in sensors have been opened. The sensor and its integrated interface are going towards the direction of battery-operated and portable systems, where the sensing elements and the processing circuitry can be integrated on the same chip to realize smart sensors [1-6]. This fact allows to have both a reduction of the whole system size and an improvement of the signal processing quality. Capacitive sensors can be used in a wide range of applications, in particular automotive (for measuring the position, speed and acceleration of moving objects) and mechanical (for measuring force, pressure, liquid levels, dielectric properties and flow) [7-17]. Some capacitive sensors have a baseline value that could vary from few pf up to some µf. For this reason, a wide-range general purpose universal interface suitable for any kind of capacitive sensor can be extremely useful. In the literature, there is a lack of circuit solutions as capacitive interfaces having, contemporarily, good performances in terms of high linearity, high sensitivity, good resolution and capability to reveal high dynamic ranges of capacitance variations. Nowadays, some current-mode (CM) solutions, based on the second generation current conveyor (CCII), are able to reveal, with a good linearity, the capacitance variations, but are unsuitable for low value capacitive sensors because of both CCII bandwidth limitations and its parasitic impedances which, depending on the particular operating point to which the CCII is biased, strongly changes, so affecting the capacitive measurements [18,19]. For all these reasons, we have developed a novel solution of capacitive analog front-end which, utilizing only two CCIIs and performing a capacitance-to-time conversion (C-T), allows to overcome the above mentioned problems. Its main operation, as shown in the following, is based on a current differentiation and does not need any initial calibration. This interface has been designed both as integrated solution at transistor level in a standard AMS CMOS 0.35µm technology and as discrete element board, for preliminary measurements, using the commercial component AD844 as CCII. Post-layout simulation results, obtained on the integrated solution, have confirmed all the theoretical expectations and also the preliminary experimental results on the prototype board, using sample capacitors as sensors, have shown high linearity and reduced percentage error when compared to theoretical values. The Second Generation Current Conveyor Second generation current conveyors are current-mode basic blocks [20-26] utilized in numerous applications, both in linear and nonlinear contexts, which sometimes can excellently substitute the traditional operational amplifier.

2 In a CCII device, if a voltage is applied at Y node, an equal voltage will be obtained at node while the current flowing into node is either equal or opposite to the current flowing into Z node. Ideal CCII behaviour can be summarized in the following matrix representation: In Figure 2 the implemented CCII, used in the proposed interface, is shown, while Table I summarizes its transistor sizes and Table II its main characteristics, obtained by suitable simulations in Cadence environment. IY V Y V I =, I Z 0 ± 1 0 V Z (1) where Z and Y nodes show ideal infinite impedances and node zero impedance. Positive (CCII+) and negative (CCII ) current conveyors are respectively obtained for I Z =I and I Z = I. Non-ideal CCIIs present the following relations: V I Z = αv = β I Y, (2) even if typically α and β are very close to 1. Generally, a unity voltage transfer function V /V Y is ensured by implementing a differential input pair, when large output resistances are required in order to obtain an α parameter dependent only on the transconductance ratio of the input pair. Concerning the current transfer function, unfortunately it is not independent from the load connected to Z node. If this load impedance is negligible with respect to the transistor output resistances, β parameter is very close to its ideal unitary value. This means that non ideality problems are related to the parasitic impedances at CCII terminals that have to be necessarily taken into account (see Figure 1) in a large number of low voltage low power applications [22-26]; in particular, the main attention must be paid in the design of low-impedance node and high-impedance Z terminal. The parasitic impedance at node, that is required to be low, is inversely proportional to the input transistors g m. A small input resistance requires large values of g m, so a trade-off between node parasitic resistance and power consumption has to be made. Concerning the Z parasitic impedance, it must be ensured to be high by a suitable configuration for the output stage. Figure 2: Schematic circuit, at transistor level, of the basic CCII+ designed in AMS 0.35µm standard CMOS technology. TABLE I: Designed CCII+ Transistor Sizes. Transistor Dimension [µm] W L M 1,M M 3,M M 5,M M 7,M M 8,M TABLE II: The CCII+ Main Characteristics. Parameter Total supply voltage Value ±1.65V Static power consumption 215µW α, β 0.95, 1 R, L, C R Z, C Z C Y 488Ω, 2mH, 0.5pF 652kΩ, 2.8pF 0.16pF The Proposed Interface Figure 1: Real CCII representation showing typical parasitic impedances at CCII terminals. Figure 3 shows the scheme of the proposed front-end at block level. It performs a C-T conversion and is formed by two CCIIs: the first, CCII1, is a voltage-to-current converter, while the second one, CCII2, is a hysteresis current comparator, based on the Schmitt trigger. Referring to Figure 4, where the signal levels at main interface nodes have been reported, the whole interface works as follows:

3 the saturated output current of the CCII2 comparator, converted into a saturation voltage (V OUT = ± VSAT ) through R 5 and R 6, represents both the output periodic signal, whose period is proportional to sensor capacitance C SENS, and the input signal (V A ), reduced by the voltage divider implemented through R 5 and R 6, for the voltage-to-current converter, CCII1. The latter gives an AC excitation current for the capacitive sensor C SENS. More in detail, the output signal of CCII1 is a square-wave current signal which is differentiated by the C SENS -R 3 passive cell. Consequently, an exponential signal is generated at D node (V D ), as shown in Figure 4. This signal is converted into a current I 2, through CCII2, compared with the saturation current I Z2 by the same hysteresis comparator CCII2, so generating the square-wave voltage V OUT. Through a straightforward analysis, considering ideal CCII behaviour and R 2 =R 3 =R, it is possible to determine the expression for the period T of the generated output square wave signal, revealed at V OUT node, as a function of the sensor capacitance C SENS, as follows: Figure 3: Block scheme of the proposed interface. Figure 8 shows the measured periods, compared with simulated and theoretical ones (eq. (3)), for capacitance values ranging from 1pF up to 100nF, obtained with the same setting values of the passive components utilized for Cadence simulations. The relative error, with respect to theoretical expectations, is lower than 10% for C SENS values ranging in about five decades. T C R RR R R = 4 SENS ln R1 R4 (3) From eq. (3), we have that the circuit sensitivity can be opportunely set by choosing suitable values of resistances R 1, R 2 =R 3 =R, R 4 and R 6. In order to validate the novel interface topology, we have firstly performed simulations, in Cadence environment, choosing the following values for employed passive components: R 1 =R 2 =R 3 =100kΩ, R 4 =100Ω, R 5 =4.7kΩ, R 6 =10kΩ. In this manner, the circuit sensitivity for ideal CCIIs has been set to about 1.8µs/pF. Figure 5 depicts a typical frequency-domain system response, highlighting the main frequency component of the generated output squarewave signal, related to signal period T, and its odd harmonics of reduced amplitude. Simulation results are in a good agreement with theoretical expectations, as depicted in Figure 6 where the output period shows a good linearity for capacitance values lower than 1pF up to 100nF, so covering a large number of commercial capacitive sensors (i.e., pressure and humidity sensors) baseline values. Waiting for the fabrication of the complete integrated solution, preliminary experimental measurements have been conducted through the prototype board, whose photo is reported in Figure 7. The commercial component AD844 of Analog Devices (supplied at ±15V) has been utilized as CCII. Data have been achieved utilizing simple laboratory instrumentations (oscilloscope and generators), and employing commercial capacitances for emulating the capacitive sensor behaviour. Figure 4: Signals behaviour at all nodes. Figure 5. Frequency-domain analysis of the interface output signal.

4 Figure 6. Simulated output signal period T vs. C SENS. Conclusion The proposed capacitive sensor interface shows good performances in a high capacitance variation range, more than five decades. Moreover, it is able to reveal also small capacitances (lower than 1pF) through a novel simple circuit topology implemented by only two CCIIs, so suitable for the integration on chip in a standard CMOS technology with low power characteristics. This interface circuit allows to neglect the Z and Y nodes saturation effects in capacitive sensor behaviour estimation, utilizing only resistive load on nodes, whose values can be chosen sufficiently higher than parasitic resistances. Finally, there are not limitations for high oscillation frequency values since it is possible to easily set the interface working range through several external parameters (only resistances) which allow also to adjust the front-end sensitivity. C SENS Acknowledgments The authors want to thank F. Mancini and M. De Meis for their help in implementing and measuring the prototype board. References Figure 7. Fabricated PCB prototype. Figure 8. Measured, theoretical and simulated periods T vs. C SENS. 1. T. Smith, J. Bardyn, B. De Geeter, O. Nys, Low power capacitive sensor interfaces, Technical Digests of Advanced on Analog Circuit Design (AACD), vol. 1, April H. Huijsing, Integrated smart sensors, Sensors and Actuators A, vol. 30, pp , H. Baltes, A. Haberli, P. Malcovati, F. Maloberti, Smart sensor interfaces, Technical Digest of International Conference on Circuits and Systems (ISCAS), pp , J. Bryzek, A. Rastegar, Advances in state of art in smart sensor signal conditioning, Technical Digests of Advanced on Analog Circuit Design (AACD), G.C.M. Meijer, F.M.L. Van der Goes, Low-cost smart sensor interfaces, Technical Digests of Advanced on Analog Circuit Design (AACD), April C. Falconi, E. Martinelli, C. Di Natale, A. D Amico, P. Malcovati, A. Baschirotto, V. Stornelli, G. Ferri, Electronic Interfaces, Sensors and Actuators B, vol. 121, pp , R. Puers, Capacitive sensors: when and how to use them, Sensors and Actuators A, vol. 37, pp , R. Puers, E. Peeters, A. Vandenbossche, W. Sansen, A capacitive pressure sensor with low impedance output and active suppression of parasitic effects, Sensors and Actuators A, vol. 21, pp , B. De Geeter, O. Nys, G.P. Bardyn, A high temperature micropower capacity pressure sensor interface circuit, Analog Integrated Circuits and Signal Processing, vol. 14, pp , 1997.

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