A Compact Analytical Design of Dual-Loop 18 GHz Frequency Synthesizer to Enhance Signal Reliability in Digital Millimeter Radio Link System

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1 Department of Electrical Engineering, University of Malaya From the SelectedWorks of Hossein Ameri Mahabadi July, 0 A Compact Analytical Design of Dual-Loop GHz Frequency Synthesizer to Enhance Signal Reliability in Digital Millimeter Radio Link System M. Moghavvemi Hossein Ameri Mahabadi, Department of Electrical Engineering, University of Malaya A. Attaran Available at:

2 Frequenz, Vol. (0), pp. Copyright 0 De Gruyter. DOI 0./FREQ.0.00 A Compact Analytical Design of Dual-Loop GHz Frequency Synthesizer to Enhance Signal Reliability in Digital Millimeter Radio Link System Mahmoud Moghavvemi, ; Hossein Ameri and Aliyar Attaran University of Malaya, Malaysia Abstract. In this paper a high resolution dual-loop.. GHz frequency synthesizer is presented which is compatible with ITU-R (F.-) standards. The investigations of phase noise and spur frequency contents are discussed in detail. The simulated and measured phase noise and spur frequency contents are similar to one another. Phase noise of dc/hz in. GHz at 0 KHz offset frequency is measured by (HP0) series Spectrum analyzer and it matches with predicted measurements. Keywords. Dual-and, Frequency Synthesizer, IRTU-R (F.-), Digital Millimeter Radio Link System. PACS (00). 0.0.Ft, 0.0.fb,.0.-x, 0..Kp, 0..Hm. Introduction A high frequency dual-loop frequency synthesizer is very complex to construct but it is a crucial functional block in telecommunication systems. It has the least trade-offs among all synthesizer structures. In a dual-loop frequency synthesis structure, one synthesizer loop operates in high frequency and consumes more power than other loops. In wireless transmission systems, synthesizers are the heart of the system in which data transmission performances such as channel speed switching, signal purity and integrity are determined. Indirect synthesis such as dualloop structure can offer these performance requirements unlike direct-digital synthesis (DDS) where the modulated signal is directly synthesized at the output frequency with adequate performance quality ([ ]). The high resolution Corresponding author: Mahmoud Moghavvemi, Center of Research in Applied Electronics CRAE, Department of Engineering, University of Malaya, 00 Malaysia; mahmoud@um.edu.my. Received: October, 00. property allows not only a fine channel frequency selection, but accurate constant-amplitude continuous-phase modulation at the output frequency ([]). Figure illustrates a general synthesizer block diagram. The relationship between input reference frequency and output frequency is shown by equation (): F output D M R F r: () The relationship between the output phase noise and reference frequency phase noise is as below: PN output D PN r C0 log M R : () For achieving an acceptable phase noise with good resolution, a dual-loop synthesizer structure is introduced, in which one loop generates low frequency with low step size, and the other loop generates high frequency with large step size. y mixing the output frequency of these two loops, a high frequency with low step size can be achieved. A general dual-loop synthesizer block diagram is shown in Figure. The output frequency equation is given by equation (): F out D M R F r C M R F r : () For dual-loop synthesizers working in Ku band, one single loop in L band and one single loop in X-band are designed to achieve GHz output. The modeled phase noise contributed from each functional synthesizer loop block is shown in Figure. Table shows an extensive performance comparison between various synthesizer structures based on their performance. Phase Noise Modeling Phase noise dictates the performance quality of the highspeed telecommunication transceivers. Phase noise in frequency-domain and jitter noise in time-domain are used to characterize digital micrometer wave link systems for high-speed radio application.

3 0 M. Moghavvemi, H. Ameri and A. Attaran Figure. asic single loop block diagram of a synthesizer. In Figure, the third order loop filter, trans-impedance can be expressed as: G.s/ D G.s/ D Z i.f / if C Z i.f / C R C if C ; () ifr C C if.ifr C C C C C C / : () Generally, every functional loop block in the synthesizer is a noise source (intrinsic). All the intrinsic noise sources in the synthesizer loop are uncorrelated. Hence the powerspectrum density (PSD) noise at the output is the superposition of all the noise contributions from each block multiplied by their noise transfer function ([]). Reference noise N ref is the phase noise contribution of reference oscillator in.f / offset frequency, and it can be modeled as: N ref.f / D N ref. f /. f / f C N ref-floor () where N ref. f / is the phase noise at f offset frequency in the 0 d/dec spectrum region, N ref-floor is the noise floor of the reference oscillator. The noise from the reference oscillator in the output will be N ref;inoutput D N ref N H where H D C H 0 N : () Phase detector noise N PDF-ref is generated in transistorlevel integrated-circuitry (IC) fabricated in factory, whose noise floor is proportional to 0 log.f ref = Hz/. The actual noise is flat with respect to the operating frequency, and by setting a proper loop bandwidth, the effective N PFD can be filtered out ([]). log.n PFD / D G cl.f / N PDF-ref C 0 log. F ref Hz / 0 where G cl.f / is the close-loop gain of the synthesizer loop ([]). () Loop filter noise N fil can be modeled from noise current and the admittance of the loop filter, Y fil. N fil.s/ D K T Re.Y fil.s// () where K is oltzmann s constant, T is the absolute temperature, and Y fil is =Z i C =Z o, as shown in Figure, the complex admittance of the loop filter. Finally the loop filter contribution in output can be expressed as ([, ]) N fil;inoutput D N fil.s/ jg.s/j ˇˇˇK VCO s ˇ ˇ. H / (0) Charge-pump noise N CP exhibits flicker noise (=f / and thermal noise, which is proportional to the duty cycle CP. For a large CP, the flicker noise corner will be high and the generated thermal noise will be small compared to flicker noise ([]). N CP;inoutput D N CP jg.s/j ˇ ˇ ˇKVCO ˇ. H /: () s VCO noise N VCO can be modeled as N VCO.f / D N VCO. f /. f / f C f c;vco f C N VCO;floor () where N VCO. f / is the VCO phase noise at f offset frequency, f c;vco is the =f noise corner of VCO and N VCO;floor is the noise floor of VCO. The VCO noise contribution in the output frequency can be expressed as ([]) N VCO;inoutput D N VCO j H j : () For uncorrelated noise sources, the respective noise spectra must be summed up to obtain total phase noise spectrum at the frequency synthesizer output. N total;inoutput D N ref;inoutput C N PFD;inoutput C N CP;inoutput C N fil;inoutput C N VCO;inoutput C N divider;inoutput : The modeled phase noise contributed from each functional synthesizer loop block is shown in Figure. Table shows an extensive performance comparison between various synthesizer structures based on their performance.

4 A Compact Analytical Design of Dual-Loop GHz Frequency Synthesizer Figure. asic block diagram of dual-loop synthesizer. System lock Diagram The block diagram of the GHz synthesizer is shown in Figure. The structure is dual loop and thus there are two phase lock loops to generate the IF and LO signals. oth signals are combined in a sub harmonic mixer, generating the desired output frequency. In the IF PLL, a TCXO0 is used as the reference of 0 MHz half sinewave signal. The used crystal s high phase noise performance (Table ) and high slope in the lower edge of the signal are the main advantages of this chip which improves the phase detector efficiency. For the phase detection part, a chip is selected that includes a phase/frequency detector and two internal digital frequency dividers M and R. The M and R values are determined by a programmable microcontroller and applied to the phase detector. An MMIC is used as the VCO. This MMIC operates at v, 0 ma DC bias. The output signal frequency of the VCO is in the 0 0 MHz range and has a good phase noise as indicated in Table. The VCO s output signal is sampled and used as a feedback to PD. In the fabricated synthesizer, the R and M values are programmed to be and, respectively. The resulting Figure. Modeled phase noise spectrum using the formulas. output frequency signal f IF in the locked loop state is equal to f IF D M R f r H) f IF D 0 MHz : () The IF signals is passed through an amplifier to have an acceptable power level at the mixer input. The schematic of

5 M. Moghavvemi, H. Ameri and A. Attaran Figure. The GHz synthesizer block diagram. VCC D C VCC L C C U out R C C C C 0 Fr Fin- 0 Fin Cext S_Data S_Clk VCC S_WR LD VCC Dout UA PD_U PD_D C C R R C R R C R0 - - VCC R C U R C U VTUNE RF VCC 0 L C C C C S-DAT S-CLK S-WR R C C0 0 R R R S-LD dm coup C R R R LO C0 R0 C U NC IN C R VCC IN C0 VCC L A C C Title Size Number Revision Date: 0-Nov-00 Sheet of File: H:\sotoodeh\synthesizer Drawn y papers\synth_.ddb : Figure. The IF PLL circuit schematic.

6 A Compact Analytical Design of Dual-Loop GHz Frequency Synthesizer Reference Frequency range (GHz) Structure Technology Tuning (%) Phase noise (dc/hz) Supply voltage (V) Spurs content (dc) Gain power [] step upconversion mixer [0].. Integer-N 0.um 0.um [] MMIC 0.um PHEMT [] Integer-N, QVCO 0.um []. Integer-N 0.um [] 0 Integer-N 0.um [] Directconversion 0.um SiGe ic- MOS []. Integer-N 0.um []. Integer-N, mixer 0.um []. Integer-N 0.um SiGe ic- MOS this work.... dm. MHz 00 KHz. MHz 0 MHz MHz MHz 00 0 MHz. 00 KHz Dual-loop 0 KHz Table. Performance comparison between various synthesizer structures.. 0 dc <... / d... d. 0.. d VCC C VCC L C C U out R C C C C 0 Fr Fin- 0 Fin Cext S_Data S_Clk VCC S_WR LD VCC Dout UA PD_U PD_D C C R R C R R C R0 - - VCC R C U R C U VTUNE RF L VCC 0 C C C C S-DAT S-CLK S-WR R C C0 0 R R R S-LD dm coup C R R R LO C0 R0 C U NC IN C R VCC IN C0 VCC L C C Title Size Number Revision Figure. The LO PLL circuit schematic. Date: 0-Nov-00 Sheet of File: H:\sotoodeh\synthesizer Drawn y papers\synth_.ddb :

7 M. Moghavvemi, H. Ameri and A. Attaran Offset frequency Phase noise (dc/hz) D IF D KHz 0 0 KHz 00 KHz MHz Table. VCO phase noise versus offset frequency. Offset frequency KHz 0 KHz 00 KHz 0 MHz Phase noise (dc/hz) Table. Xtal phase noise versus offset frequency. the IF PLL is indicated in Figure. In the LO PLL, the reference frequency is generated by another TCXO, a product of RAKON Inc., to have a very low noise and high stability of PPM. The phase noise versus offset is presented in Table for this chip. The applied PD in the loop is the same chip as described in the previous section. An MMIC is selected for the VCO block. The MMIC has an operation frequency range of.. GHz and is capable of changing the output frequency by a tune voltage of v range. A 0 d directional coupler is used to sample the output frequency, since the power level of the output is high enough ( dm). The sampled frequency is passed through a frequency divider, so f in D f LO =. The selected chip for the frequency divider block has a very low noise. Its operation frequency range is from DC to. GHz and its supply voltage and current are v, 00 ma, respectively. In the fabricated synthesizer, M and R are set to and, to provide the LO output signal frequency f LO : f LO D M R f r H) f LO D 00 MHz : () The schematic diagram of the LO PLL is shown in Figure. Finally, the IF and LO signals are applied to a sub harmonic mixer in order to generate the required frequency. The sub harmonic mixer MMIC has a LO internal amplifier and its conversion loss is equal to 0 d. The frequency ranges of IF and LO signals of this chip are DC GHz and 0. GHz respectively. Considering the sub harmonic mixer characteristic, the output signal frequency will be equal to f out D f LO C f in D 0 MHz : () Figure illustrates the schematic of the sub harmonic mixer. The phase noise of the fabricated synthesizer is measured and presented in the next section. C A Title Size VCC C Number C Date: 0-Nov-00 Sheet of File: H:\sotoodeh\sy nthesizer papers\sy nth_.ddb Drawn y : LO LO Revision Figure. Modeled mixer circuit schematic. Fabrication and Measurement Results IF The synthesizer is fabricated and shown in Figure. The LO and IF PLL loop s VCOs have a phase noise around 0 dc/hz and dc/hz at 0 KHz offset, respectively, according to their datasheets. The phase noise of the LO signal decreases by 0log factor, after multiplying by in the sub harmonic mixer. Therefore, there are two signals at the sub harmonic mixer inputs: a signal with frequency of f LO and dc/hz phase noise, and an IF signal with dc/hz phase noise. The output signal phase noise follows the f LO signal phase noise considering the higher phase noise of the IF signal. So a phase noise of dc/hz is predicted for output signal because of the sub harmonic mixer characteristic. Measurement results of the fabricated synthesizer are shown in Figure. The frequency spectrum is observed by an HPA spectrum analyzer. The frequency span, RW, and VW are set to 0 KHz, KHz, and 0 Hz, respectively. The difference between carrier and 0 KHz offset power level is equal to. d, as indicated in Figure. Thus the phase noise of the output signal is obtained by the following relation ([0, ]): Measured phases noise D U RF : 0 logrw D : dc/hz: () Phase noise at KHz and 00 KHz offset are 0 and 00 dc/hz, respectively. Spur frequency contents are measured at dc. The predicted performance parameters such as gain, spur contents and phase noise are in comparable to the measured results. The comparison results indicate that the phase noise of the system is superior to its rivals. Conclusion The modeling representations of all intrinsic phase noise spectrum sources of frequency synthesizer loop are discussed. The block-circuit analysis of a dual-loop synthesizer is presented. A carefully calculated frequency resolutions and design parameters in each loop are analyzed. This C A

8 A Compact Analytical Design of Dual-Loop GHz Frequency Synthesizer Figure. The fabricated synthesizer. Figure. The measurement result. method is proposed to dramatically reduce the phase noise effect in output oscillating frequency due to performance trade-offs in all the other synthesizer loop structures. In this paper, the methodology analysis of dual-loop frequency synthesizer and spur frequency contents and phase noise are analyzed. The performance comparison between the proposed method and previous works in this frequency is presented. The channel switching is fully programmable for.. GHz frequency range. Test results indicate that the fabricated synthesizer has a phase noise of dc/hz, much superior to the phase noise reported in the references. Acknowledgments The first author was supported by the Center of Research in Applied Electronics CRAE. The second author was supported by the University of Malaya. References [] N. M. Filiol et al., An agile ISM band frequency synthesizer with built-in GMSK data modulation, IEEE Journal of Solid- State Circuits (), no., 00. [] T. A. D. Riley, M. A. Copeland and T. A. Kwasniewski, Delta-sigma modulation in fractional-n frequency synthesis, IEEE Journal of Solid-State Circuits (), no.,. [] A. Attaran, M. Moghavvemi and H. Ameri, Design a to 0GHz stable source, Microwave and RF (00),. [] M. H. Perrott, T. L. Tewksbury and C. G. Sodini, A mw fractional-n synthesizer/modulator IC, Solid-State Circuits Conference, Digest of Technical Papers, rd ISSCC, IEEE International,. [] S. A. Osmany, F. Herzel, J. C. Scheytt, K. Schmalz and W. Winkler, An integrated -GHz low-phase-noise frequency synthesizer in SiGei technology, IEEE Compound Semiconductor Integrated Circuit Symposium, Technology Digest, pp., 00. [] F. Herzel, S. A. Osmany and J. C. Scheytt, Analytical Phase- Noise Modeling and Charge Pump Optimization for Fractional PLLs, IEEE Transactions on Circuits and Systems I Regular Papers (00), PP(),. [] A. Attaran, H. Ameri and M. Moghavvemi, Design an X- band frequency synthesizer, Microwaves and RF (00), -0. [] L. Lascari, Accurate Phase Noise Prediction in PLL Synthesizers Part : Here is a method that uses more complete modeling for wireless applications, Applied Microwave & Wireless (000), no., 0. [] A. Natarajan, A. Komijani and A. Hajimiri, A fully integrated -GHz phased-array transmitter in, IEEE Journal of Solid-State Circuits 0 (00), no., 0. [0] P. Yu-Hsun and L. Liang-Hung, A -GHz Triple-Modulus Phase-Switching Prescaler and Its Application to a -GHz Frequency Synthesizer in 0.um, IEEE Transactions on Microwave Theory and Techniques (00), no.,. [] J. Mondal et al., A highly integrated multifunction macro synthesizer chip (MMSC) for applications in GHz synthesized sources, IEEE Journal of Solid-State Circuits (), no., 0 0. [] A. W. L. Ng and H. C. Luong, A -V -GHz -mw Quadrature VCO ased on Transformer Coupling, IEEE Journal of Solid-State Circuits (00), no.,. [] T. Geum-Young et al., A. -GHz fast settling PLL for M-OFDM UW applications, IEEE Journal of Solid- State Circuits 0 (00), no.,. [] T. H. Lin and Y. J. Lai, An Agile VCO Frequency Calibration Technique for a 0-GHz PLL, IEEE Journal of Solid- State Circuits (00), no., 0. [] V. Jain et al., A Single-Chip Dual-and -GHz/ - GHz i Transceiver for Automotive Radars, IEEE Journal of Solid-State Circuits (00), no.,. [] A. W. L. Ng et al., A -V -GHz.-mW phase-locked loop in a 0.um process, IEEE Journal of Solid- State Circuits (00), no.,. [] Z. Hui et al., A. GHz to.0 GHz Single-Chip Transceiver for M-OFDM UW in 0. um Process, IEEE Journal of Solid-State Circuits (00), no.,. []. A. Floyd, A.-GHz Sub-Integer-N Frequency Synthesizer for 0-GHz Transceivers, IEEE Journal of Solid- State Circuits (00), no., 0 0.