PWB Solutions for High Speed Systems

Transcription

1 PWB Solutions for High Speed Systems Benson Chan, John Lauffer, Steve Rosser, Jim Stack Endicott Interconnect Technologies 1701 North Street, Endicott NY Abstract The authors of this paper will describe a method to assist system designers of High Speed Systems in the selection of PWB design / build attributes. The attributes that will be covered are; dielectric material, circuit trace width and thickness, PWB thickness, copper surface roughness, and Plated Through Hole (PTH) stub length. Changes to these attributes are weighed against the cost and the risk of each change to arrive at an optimal system design. Manufacturability limitations that must be considered include board size, drill and plate aspect ratio capabilities, minimum spacing and internal layer registration capabilities. The system requirements may drive design attributes such as low loss dielectrics, subcomposites, microvias, buried vias, and/or back drilling. Such complex board designs will limit the number of capable suppliers that can be quoted so unnecessary complexity needs to be avoided. PWB Market Drivers In today s market for high performance PWBs, there are two seemingly opposing drivers. The first driver is for enhanced electrical performance, primarily in the area of clock speeds and data bandwidth. For the last 20 years, the computer industry has been basically following Moore s law. This law states that the number of transistors used in an Integrated Circuit will double every 18 months. To accomplish this, the size of the transistor is made smaller and is packed closer together. This packing is done with finer and finer lithographic techniques where now transistors are in the 90namometer size features. When the transistors are packed this close together, the time it takes to go from one transistor to the next is reduced thus the circuits can be made to run at higher clock speeds. This speed increase allows a microprocessor to perform calculations at an ever increasing rate The second major driver in the market is for higher integration of functions available on a single part, this can either be achieved by using larger ASICs or by adding more components onto a given board space. Putting more components onto a PWB requires tighter wiring densities to fit all the signals necessary for the communications between all the components. Line widths are being pushed to the limits of existing photolithography where 01 lines on redistribution layers and 02 lines in inner cores are used. This allows for more lines per channel to escape the various components. To accommodate the increased speeds of the processor and associated memory, the system level clock must also increase speeds accordingly. In the Personal Computer world, the FSB or front side bus is the most noticeable. The bus frequency was around 33Mhz in the early i386 days, where now it is at 800Mhz for the current Pentium 4 processors. In the high end servers, this gets even faster. System clocks beyond 1GHz are already in production with the expectation of clocks greater than 5GHz by As the speeds increase in these high end server boards, more attention must be placed on the attributes of the individual elements used in the construction of these boards. Characteristics of the circuitry are now more important. While Moore s law require the transistors to get smaller and smaller, the speed increases in the boards drive the copper being used to transmit the signals in the opposite direction. The line widths in today s high complexity high reliability server boards are from (3-4 mils). These lines will now move to widths of 05 (5mils) and wider to improve the signal integrity with the faster clock rates. In order to accommodate the wider lines, a stumbling block has been identified. To achieve a given impedance for the signal lines, thicker dielectric needs to be used between the signal plane and the reference planes. A rough approximation of the dielectric thickness equal to the line width For Example, for a 5 mil wide trace, the dielectric material needs to be 5 mils on top and 5 mils on the bottom of the signal plane. Another consequence of wider lines is the need to increase the number of signal planes needed. This is primarily due to the reduction in wiring density in the high congestion areas such as under an Application Specific Integrated Circuit (ASIC) or microprocessor. For example, where the escape using a 3 mil line is 3 lines per channel, going to 5 mils will reduce the number of lines per channel to 2. To achieve the same number of interconnects, we will have to increase the number of signals planes along with reference planes to complete the design. PWBs utilizing these wider lines will require board thickness to go up 50 to 50 from current thicknesses. This of course depends on the density of the component being escaped. Recent advances in printed circuit board technology and manufacturing capabilities put multiple attributes at the finger tips of the system designer. This paper will describe a design process that optimizes the selection of these attributes based on system performance criteria. The criteria may include electrical (signal attenuation), and density (wireability). The key electrical performance criteria is to reduce the signal attenuation in a critical system path incorporating multiple boards and connectors. This attenuation reduction must be achieved without compromising the characteristic impedance and crosstalk specifications. Wireability requirements will drive the PWB design, but manufacturability limitations will restrict options that can be considered. An area of concern is within the connector footprint where the pin/pad pitch will limit the lines per

2 channel that can be used to wire out the signals. Another such area is wireability limitations within dense pitch component footprints such as large 1mm pitch module sites. Fewer lines per channel will drive more signal layers which in turn will drive more power plane for signal reference. An alternative may be to keep layer count in check by defining component and connector pin assignments such that board wiring flows smoother with a limited number of crossings. Another alternative will be to consider a combination of manual and automated trace routing to optimize layer count. Time and effort put into the design will pay dividends in board manufacturability, reliability, and price. Variables to Consider for High Speed PWBs In the construction of PWBs, there are a number of variables that can be changed that will affect the performance of the finished system. The design of the PWB will have an impact on its performance. To achieve performance in a PWB, many factors need to be considered both in the design phase as well as the fabrication phase to ensure that the ultimate system meets the requirements set out at the beginning of the project. The following list describes the parameters that are available to meet a system performance goal. These parameters are affected in both the design phase of the project as well as the fabrication of the PWBs. Line width and spaces Line Thickness PTH stub length reduction Elimination or limitation of the length of a PTH that is not actually used to complete a circuit. PWB Cross section provide shielding to signals and to provide for proper power / ground distribution. Connector footprint the PTH pattern defined by a card connector which may require compliant pin or SMT attach. Subcomposite construction This type of construction allows for variable length PTHs in the cross section. HPC is an example of a subcomposite construction being practiced at Endicott Interconnect. Copper roughness The roughness of the copper in both the signal lines as well as the reference planes will have an effect on attenuation due to skin effects. Dielectric material The material surrounding the circuit traces. The choice of material will have an impact on the performance on the overall system. Fabrication Analysis The design variables could obviously have some impacts on board manufacturability, cost, reliability and other factors. Table 1 provides a summary of these impacts. Design Solution Effect Impacts Low Loss Dielectric Dielectric Losses Process Optimization, Reliability Verification, Increased Cost Increased Line Width Skin Effect Reduced Wireability, Thicker Dielectric, Thicker Board Increase Line Skin Effect Circuit Trace Resolution Thickness Cu Roughness Skin Effect Circuit Line Adhesion Back Drill Sub Composite Sub Composite with Z-Interconnect Stub Reduction Stub Reduction Stub Reduction Table 1 - Fabrication Analysis Loss (db) Yield Impact / Increased Cost, Reliability Exposure, Reduced Wireability Increased Cycle Time Differential Insertion Loss of 50cm Link Non-backdrilled Backdrilled EI Board Figure 1 Comparison of Backdrilled board and a Subcomposite build board Introduction of new low loss dielectrics in board fabrication requires process optimization, primarily in the areas of lamination, drill, hole clean and plate to insure product quality and reliability is maintained. The low loss dielectric materials typically come with higher raw material cost and may or may not impact manufacturing cost. Increased line width, in itself, will improve circuitize yields, however, it can significantly effect board thickness, potentially even resulting in an unmanufacturable board. The increased line width can result in less wiring per layer (reduced lines per channel), thus requiring more wiring layers to achieve the required interconnects. Additionally, the wider lines will require thicker dielectric layers to maintain the desired impedance. The combination of additional wiring layers and increased layer thickness could result in a board thickness beyond the standard drill and plate aspect ratio capabilities. Skin effect is the phenomenon whereby current flow is forced to the perimeter of the trace as operating frequency increases. Increased line thickness will improve skin effect resistive losses, but not nearly as much as increased line width. For example, doubling the thickness of a typical circuit line (e.g. 3 mil trace in one ounce Cu) will result in a 32% perimeter increase, while doubling the width of the same circuit trace will provide a 68% perimeter increase. Note that a 6 mil trace in 1 ounce Cu is easily manufacturable, while a 3 mil trace in 2 ounce Cu would be very difficult to produce.

3 The trace sidewall angle in the thicker Cu would also be much shallower. Copper roughness can significantly impact resistive losses due to the skin effect. This rough Cu essentially acts to increase path length when the current is flowing through this roughness. The roughness of both the signal trace and the reference plane are important in skin effect resistive losses. However, without some degree of Cu roughness, the laminate adhesion could be impacted. Without the proper precautions, the board could delaminate during assembly or lead to system reliability exposures. Figure 2 Cross Section showing a Subcomposite build with reduced PTH length Figure 3 HPC-Z EI Technology showing variable length PTHs Back drilling, or removal of the unused portion of a PTH, is becoming a popular way to address effects (unwanted signal reflections) of PTH stubs. This can be a very effective technique for eliminating stubs, as stubs can be reduced to as little as a couple of mils in length. However, it becomes very complex to handle if the number of high performance nets that require this back drill exceed a couple of hundred. Back drilling is performed as one of the final operations in the PWB manufacturing sequence. As such, the impact of a broken drill, drill too deep or any number of other potential problems can be catastrophic to board cost and delivery schedule. Obviously, this risk is increased as the number of nets to be drilled increases. Back drilling is typically performed with a drill diameter that is 4 to 10 mils larger than originally drilled hole. This requires that all layers that the back drill will penetrate be cleared out by this diameter, plus an additional annular ring sufficient to minimize yield and reliability exposures. Clearing out of these layers can have a significant effect on wireability. Additional work is required to demonstrate that there is no reliability impact associated with the back drill process. Sub composite build can also be an effective way to reduce or eliminate PTH stubs Figure 2 and Figure 3 show two version of sub-composite build technology that is available at Endicott Interconnect. Figure 2 shows two short PTHs that extend only half way through a cross section. By reducing the PTH stubs, we are able to reduce the impact of a long stub and achieve performance equivalent to a back drilled board. Figure 1 shows the results of electrical measurements performed on a sub-composite build and a board that had back drilled PTHs. Both boards performed equally well when compared to a board that retained all full length PTHs. Depending on the granularity of the sub composite breakdown, stubs can be totally eliminated, or reduced in length. Care must be taken by the designer to insure that critical nets are wired in the stack-up where stubs are minimized. An additional benefit of sub-composite build is that since the sub composites will be thinner than the full composite, smaller drills can be used. This also allows for reduced pad and anti-pads so wiring channels are larger to increase wireability. If we now look at Figure 2, the layers beneath where the sub composite PTH terminate can now be used for additional routing channels, opening up significant opportunities to increase wireability. Basically we can have a signal trace directly under the PTH and not have to be concerned of an electrical short since there is no path between the trace and the PTH. A drawback to the sub composite approach is that the build cycle time will likely be increased, due to the fact that additional sequential drill and plate operations are required. On the other hand, subcomposites may be the only practical way to manufacture thick PWBs greater than The maximum benefit in performance and density is achieved when the sub composite approach is combined with Z-interconnect technology, such as Endicott Interconnects HPC-Z EI TM 1 technology shown in Figure 3. In this technology, sub composites are conductively joined to each other, obviating the need for a final composite level drill and plate operation. As in the sub composite approach, subs can be defined with as few as one layer (e.g. power plane), or with several layers (signal or power). Via stubs can be totally eliminated, and the ultimate wireability can be achieved. 1 TM HPC-Z EI is a registered trademark of Endicott Interconnect Technologies

4 Electrical Modeling By far the largest contributor of attenuation in the system will be the signal traces on the PWB. It would be useful to understand both the mechanisms for this attenuation and the leverage for various design and fabrication variables to reduce this attenuation. Can a system attenuation specification be met by merely widening the traces? Will it be necessary to hurdle the processing challenges associated with a low loss dielectric material or thicker or smoother traces? To this end, a model of trace attenuation was developed. This model accounts for the frequency dependent nature of the conductor and dielectric attenuation components. There are numerous 2D and 3D field solver tools available in the industry for assessing the transmission line attenuation problem. However, most of these tools require a large investment of resource and deliver marginal results when considering the effects of surface roughness on attenuation. Consequently, the model developed here is one based on the fundamentals but qualified with an empirical bias to accurately represent the surface roughness factor. Series attenuation along a signal trace is linearly proportional to the trace length. It can be expressed as the following: α * d (neper) = [α 1 (conductor) + α 2 (dielectric)]*d (1) α 1 (conductor) (R/2Zo)*(1+ SR) (2) α 2 (dielectric) (tan δ) * πfτ HF (3) where: d = signal trace length R = series resistance at frequency f Z0 = characteristic impedance, usually 50 ohms SR = surface roughness factor = (atan{1.4( /δs) 2 }/π] = rms surface roughness (a.k.a. Rq, or Rrms) δs = skin depth at frequency f tan δ = effective loss tangent of the dielectric material τ HF = propagation time constant of the dielectric material at high frequency The series resistance in Equation (2) must take into account the skin effect and the roughness effect. Trace resistance is dominated by the skin effect at higher frequencies. As current is crowded to the trace surface, the dependence of resistance on conductor cross-sectional area is replaced by a dependence on conductor cross-sectional perimeter. The perimeter is more easily influenced by the conductor width than conductor thickness. Attenuation in the Dielectric (db/cm) 1.0E E E E E E E E E E+02 Figure 4 Comparison of Dielectric loss vs Frequency Roughness (um) Representative Measured Surface Roughness Data Measured on Dektak 1 oz LP Standard 1/2 oz LP Standard 12 um Standard Ra (um) Rrms (um) Rtm (um) Figure 5 Comparison of Copper roughness with different units of measure Equation 2 includes a roughness factor, SR, which is essentially a curve-fitted correction to account for surface roughness. The impact of surface roughness on resistance is not so readily intuitive. While a smooth surface will have a smaller perimeter than a rough one, it is the effect of the roughness along the length of the conductor that is so dramatic. The length of the conductor is effectively increased by the surface roughness. It has been shown that surface roughness can increase series resistance by up to 100%. 2 There are numerous metrics used to define surface roughness, but the factor most appropriate for the consideration of the flow of current is the rms roughness, often termed Rq. This roughness metric was commonly used in the microwave industry in days past, but is difficult to obtain from copper foil suppliers today. Other metrics such as Ra (average) and Rtm (average peak to valley) are more popular and perhaps more appropriate for adhesion and reliability considerations. Df = 24 Df = 20 Df = 16 Df = 12 Df = 08 Df = 04 2 See reference labeled "Surface Roughness"

5 There is often no relationship between a surfaces Ra, Rtm and Rrms. Most modeling tools which attempt to accommodate the effect of surface roughness require a definition of Rrms. The characterization of Rrms is often accomplished with standard Profilometry procedures. Additionally, a thicker copper foil may inherently have a larger Rrms, depending on fabrication methods. Surface roughness can also be influenced by PWB processes. It is important to characterize the Rrms of a surface that has seen all the representative PWB fabrication processes that a fully constructed signal conductor will be subjected to. Figure 5 shows conductor surface roughness characterizations in the form of Rrms for various copper foils. This model was then exercised to predict the total trace attenuation for various design points, including an array of dielectric loss, trace width, trace thickness and surface roughness assumptions. A number of factors become readily apparent upon review of the results. Before we discuss these factors, let s define the framework of a representative system in order to put these factors in light of a practical application. Consider a system with the following attributes: Total trace length of 80 cm Trace attenuation target of GHz for singleended signal transmission Via attenuation target of GHz over 6 vias 1.0 Total Trace Attenuation Dielectric Loss = 05 Signal Thickness = 1.3 mil Trace Width = 4 mil let s assume that a move away from FR4 and to APPE LD621 is in order. We buy about GHz of attenuation back by going with a low loss material. With the material choice out of the way, let s examine the factors which influence the conductor component of trace attenuation. Equation 2 illustrates that conductor attenuation is proportional to Resistance, which in turn is proportional to the square root of frequency due to the skin effect. This is further reinforcement that we made the right decision to move to a lower loss dielectric: Dielectric loss will tend to dominate at higher frequencies due to its direct proportionality to frequency. As we look at the impact of trace width on conductor attenuation, let s fix the conductor thickness to that of a standard 1 oz Cu foil, or 1.3 mils. (From Figure 6, we see that the Rrms of this standard foil has been measured to be about 1.5 um.) Figure 7 includes total trace attenuation, including all conductor and dielectric losses, for a 4 mil and 7 mil trace width in 1 oz LP copper foil and an APPE dielectric. A 4 mil trace exhibits GHz total attenuation, or 7 db for 80 cm of trace length. Widening the trace to 7 mils reduces the total attenuation to GHz for 80 cm of trace length. Each 1 mil of width reduces the total attenuation for 80 cm of trace length by about GHz. Wider traces may reduce the attenuation, but additional considerations including wireability, crosstalk, and impact on PWB thickness required to maintain a 50 ohm Z0 must all be considered for the ultimate design solution. Total Trace Attenuation Dielectric Loss = 05 Signal Thickness = 1.3 mil Rq = 1.5 um 1.0 Attenuation (db/mm) Rq = 0.5 um Rq = 1.5 um Attenuation (db/mm) 4 mil trace width 7 mil trace width 1.0E E E E E E E E E E E E+02 Figure 6 Trace Attenuation of a 4 mil wide line vs Frequency First, in order to meet this attenuation specification, it may be necessary to change the dielectric medium to a material with a lower loss factor. From Equations (1) and (3), we see that attenuation due to the dielectric is directly proportional to frequency, trace length, and a material s dielectric loss factor. For example, an FR4 dielectric with a loss factor of 2 develops 47 db/cm of dielectric 1.5 GHz. For 80 cm of trace length, this translates to GHz. Similarly, a lower loss material such as APPE LD621, with a loss factor of 05, would only develop GHz. Figure 4 shows the relationship between attenuation due to dielectric loss and frequency for various dielectric loss factors. With only 6 db of total trace attenuation available, Figure 7 Trace Attenuation of a 1.3 mil thick line vs Frequency Now that we have an idea of the leverage to be gained by dielectric material choice and signal trace line width, let s examine the impact that surface roughness has on total attenuation. Is there significant leverage to justify a move to a smoother copper surface? Is it possible to process a perfectly smooth copper surface and still maintain adequate adhesion after lamination? Since this seems impractical, let s exercise the model to see what leverage exists for a reduced Rq. Figure 6 includes curves of total trace attenuation for a 4 mil trace in 1 oz copper foil and APPE dielectric, with Rq varied from 1.5 to 0.5 um. As expected, the reduction in attenuation is only realized at

6 higher frequencies. A 4 mil trace with Rq of 1.5 um has a total attenuation of GHz or GHz for 80 cm of trace length compared to a total of GHz and 80 cm of trace length with an Rq of 0.5 um. So at this frequency of interest, we can buy about GHz of attenuation by reducing the Rq from 1.5 to 0.5 um. That translates to 17 % of the total attenuation specification for our sample system. Figure 8 Electrical model of a PTH with a long stub The last trace attribute considered for potential attenuation reduction is the trace thickness. Of all the factors considered previously, trace thickness offers the least leverage. The model was exercised for a 1.5 oz standard foil, and total trace attenuation was reduced by less tan GHz for 80 cm of trace length. Perhaps there is more incentive to reduce the attenuation of the vias in our sample system. justification in terms of reduced model complexity and analysis resource. The accuracy issue is reduced in significance when comparing design points as the analysis of each design point incorporates similar inaccuracies. The emphasis on reducing via attenuation is best placed on reducing the stub length. This can be accomplished by numerous means previously discussed. A 3D full wave model was constructed of a via with maximum stub length. This would represent a PWB construction with no subcomposites, where a full plated-through-hole (PTH) is required for each z-interconnect, with signal trace routing on the outer-most signal layers in the PWB layup. The actual PTH length and associated stub length will be dependent on the total PWB thickness and signal layer count required to meet wireability requirements. For this study, a PWB thickness of greater than 200 mils was assumed, resulting in a maximum stub length of 180 mils. An attenuation of 0.28 db was extracted from this worst case stub length via model at 1.5 GHz. The 3D model (Figure 8) was modified to represent a minimum stub length of 20 mils. This best case stub length via model exhibited 6 db of 1.5 GHz. Reducing the via stub length eliminated GHz of attenuation. Multiply this by the 6 vias in the system and there is a total leverage of 1.3 db to be gained (Figure 9). A benefit of using a subcomposite construction over a conventional sequential build up is the use of smaller diameter PTHs in the subcomposites. Smaller diameter PTHs have s smaller impact on PTH discontinuity therefore less of an effect on signal integrity. With subcomposites, we can use thickness of 50 or less. This means that PTHs can be constructed using drills of 06 to 08 vs a more standard 12 or larger. Total Trace Attenuation Correlation 7 mil 1 oz LP Cu APPE Dielectric Attenuation (db/cm) Modeled Data Measured Data Figure 10 Comparison of Model result vs Measured Data Figure 9 The number of PTHs present in a two card net For the purpose of this study, via attenuation was considered independently from trace attenuation. A more accurate analysis would incorporate both the vias and traces in an all inclusive model, being sure to capture the interaction between the two components. While there is some accuracy lost in an independent analysis, there is certainly a Empirical Modeling Results While this trace attenuation model stands in need of additional correlation, it has been shown to be reasonably accurate over the GHz bandwidth of interest in tomorrow s high speed PWB systems. Good model to hardware correlation is shown in Figures 10 and Figure 11 in the form of per unit length attenuation (db/cm) vs. frequency curves for trace widths of 4 and 7 mils. Table 2 summarizes the reduction in high speed system attenuation possible with each PWB design and fabrication

7 attribute. Each of these attributes has an associated set of manufacturing, cost, and reliability implications. The system designer s task is to weigh each of these factors and deliver an optimized solution which meets the electrical performance objective. This paper has discussed the tradeoffs associated with delivering such a PWB solution. As system speeds increase, it becomes increasingly challenging to deliver a high performing PWB design. New technology advances such as sub-composite fabrication and Z-interconnect bring new PWB features to the table which will enable the high speed systems of tomorrow. Summary This paper described the major PWB attributes that influence attenuation and defined their contribution to attenuation reduction. It is intended to help you decide what changes in PWB technology make sense for you as you drive towards lower attenuation designs. This information can be added to your knowledge of the capabilities of your suppliers, the product cost you re willing to accept, and the change associated risks you re willing to take as you come to your decision. System (1) PWB Attribute Attenuation Advantage 1.5 GHz Low Loss Dielectric 2.8 Material Trace Width Increase from to 7 mils Via Stub Reduction 1.3 Smoother Cu Surface 1.0 Signal Thickness Increase to oz Cu (1) 80 cm trace length, 6 vias Table 2 Summary of PWB Attribute vs db gain Attenuation (db/cm) 1 1 Total Trace Attenuation 4 mil line 1oz LP Cu APPE Dielectric Figure 11 4Mil trace attenuation Measured Data Modeled Data Matick, R. E., Transmission Lines for Digital and Communication Networks, McGraw-Hill Inc. (New York, 1969). The Morphology of the Metal-Polymer Interface and its Implication to High Frequency Signal Transmission R. Schulz, E. Klusmann, J. Schulze, H. Meyer, H. Reichl, and G. Sommer ( posted ) A Cost-Effective Methodology for Improving System Signal Integrity by Back-Drilling Plated Through Holes in Backplanes Sergio Camerlo, Yida Zou, and Scott Priore ( posted ) "Surface Roughness", H. Johnson, Phd., EDN Magazine, Dec. 6, Acknowledgments The author would like to acknowledge Chi-Shih Chang for his work on the electrical modeling of these systems References DesignCon 2004 Priest et al Edwards, T. C., Foundations for Microstrip Design, John Wiley and Sons (New York, 1981). Andy Byers, HFSS Users Conference 2003