FSUSB104 Low-Power, Two-Port, Hi-Speed, USB2.0 (480 Mbps) Switch

Transcription

1 FSUSB104 Low-Power, Two-Port, Hi-Speed, USB2.0 (480 Mbps) Switch Features Low On Capacitance: 3.7 pf Typical Low On Resistance: 3.9 Ω Typical Low Pow er Consumption: 1 μa Maximum - 15 μa Maximum ICCT over an Expanded Voltage Range (VIN=1.8 V, V CC=4.3 V) Wide -3 db Bandw idth: > 720 MHz Packaged in Pb-free 10-Lead UMLP (1.4 x 1.8 mm) 8 kv ESD Rating, >16 kv Pow er/ ESD Rating Pow er-off Protection on All Ports When V CC=0 V - D+/D- Pins Tolerate up to 5.25 V Applications Cell phone, PDA, Digital Camera, and Notebook LCD Monitor, TV, and Set-Top Box Description The FSUSB104 is a bi-directional, low -pow er, tw o-port, Hi-Speed, USB2.0 sw itch. Configured as a double-pole, double-throw sw itch (DPDT) sw itch, it is optimized for sw itching betw een tw o Hi-Speed (480 Mbps) sources or a Hi-Speed and Full-Speed (12 Mbps) source. The FSUSB104 is compatible w ith the requirements of USB2.0 and features an extremely low on capacitance (CON) of 3.7 pf. The w ide bandw idth of this device (720 MHz) exceeds the bandw idth needed to pass the third harmonic, resulting in signals w ith minimum edge and phase distortion. Superior channel-to-channel crosstalk also minimizes interference. The FSUSB104 contains special circuitry on the sw itch I/O pins for applications w here the VCC supply is pow ered-off (VCC=0), w hich allow s the device to w ithstand an over-voltage condition. This device is designed to minimize current consumption even w hen the control voltage applied to the SEL pin is low er than the supply voltage (VCC). This feature is especially valuable to ultra-portable applications, such as cell phones, allow ing for direct interface w ith the generalpurpose I/Os of the baseband processor. Other applications include sw itching and connector sharing in portable cell phones, PDAs, digital cameras, printers, and notebook computers. Ordering Information Part Number Top Mark Operating Temperature Range FSUSB104UMX JF -40 to +85 C Package 10-Lead, Quad, Ultrathin Molded Leadless Package (UMLP), 1.4 x 1.8 mm HSD1+ HSD2+ HSD1- HSD2- D+ D- Sel Control /OE Figure 1. Analog Symbol 2008 Semiconductor Components Industries, LLC. Publication Order Number: November-2017, Rev. 2 FSUSB104/D

2 Pin Assignments Pin Definitions D- D HSD2-4 9 HSD HSD1- HSD1+ Sel V CC /OE Figure 2. Pin Assignment (Top Through View) Pin # Name Description 1 D+ USB Data Bus 2 D- USB Data Bus 3 Ground 4 HSD2- Multiplexed Source Inputs 5 HSD2+ Multiplexed Source Inputs 6 HSD1- Multiplexed Source Inputs 7 HSD1+ Multiplexed Source Inputs 8 /OE Sw itch Enable 9 V CC Supply Voltage 10 Sel Sw itch Select Truth Table Sel /OE Function X HIGH Disconnect LOW LOW D+, D-=HSD1+, HSD1- HIGH LOW D+, D-=HSD2+, HSD2-2

3 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VCC Supply Voltage V V CNTRL DC Input Voltage (S, /OE) (1) -0.5 V CC V VSW DC Sw itch I/O Voltage (1) V I IK DC Input Diode Current -50 ma IOUT DC Output Current 50 ma TSTG Storage Temperature C ESD Human Body Model, JEDEC: JESD22-A114 All Pins 7 I/O to 8 Pow er to 16 Charged Device Model, JEDEC: JESD22-C101 2 Note: 1. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit V CC Supply Voltage V V CNTRL Control Input Voltage (S, /OE) (2) 0 V CC V VSW Sw itch I/O Voltage V kv TA Operating Temperature C Note: 2. The control input must be held HIGH or LOW and it must not float. 3

4 DC Electrical Characteristics All typical values are at 25 C unless otherw ise specified. Symbol Parameter Conditions V CC (V) T A =- 40ºC to +85ºC Min. Typ. Max. VIK Clamp Diode Voltage IIN=-18 ma V VIH V IL Input Voltage High Input Voltage Low Units 3.0 to V V 3.0 to V V IIN Control Input Leakage VSW=0 to VCC µa IOZ IOFF Off State Leakage Pow er-off Leakage Current (All I/O Ports) 0 Dn, HSD1n, HSD2n 3.6V V SW=0 V to 4.3 V, V CC=0 V Figure 4 R ON HS Sw itch On Resistance ( ) VSW=0.4 V, ION=-8 ma 3 Figure 3, µa µa Ω R ON HS Delta Ron ( 4 ) V SW=0.4 V, I ON=-8 ma Ω I CC Quiescent Supply Current V CNTRL=0 or V CC, I OUT= µa ICCT Increase in ICC Current per Control Voltage and VCC VCNTRL =2.6 V, VCC=4.3 V µa V CNTRL =1.8 V, V CC=4.3 V µa Notes: 3. Measured by the voltage drop betw een HSDn and Dn pins at the indicated current through the sw itch. On resistance is determined by the low er of the voltage on the tw o (HSDn or Dn ports). 4. Guaranteed by characterization. Not tested in production. 4

5 AC Electrical Characteristics All typical value are for V CC=3.3 V at 25 C unless otherw ise specified. Symbol Parameter Conditions V CC (V) ton toff Turn-On Time S, /OE to Output Turn-Off Time S, /OE to Output R L=50 Ω, CL=5 pf VSW=0.8 V Figure 5, Figure 6 RL=50 Ω, CL=5 pf VSW=0.8 V Figure 5, Figure 6 tpd Propagation Delay ( ) CL=5 pf, RL=50 Ω 5 Figure 5, Figure 7 t BBM O IRR Xtalk BW Break-Before-Make Off Isolation Non-Adjacent Channel Crosstalk -3db Bandw idth R L=50 Ω, C L=5 pf V SW1=V SW2=0.8 V Figure 9 RL=50 Ω, f=240 MHz Figure 11 RL=50 Ω, f=240 MHz Figure 12 RL=50 Ω, C L=0 pf Figure 10 R L=50 Ω, C L=5 pf Figure 10 Note: 5. Guaranteed by characterization. Not tested in production. USB Hi-Speed-Related AC Electrical Characteristics T A =- 40ºC to +85ºC Min. Typ. Max. Units 3.0 to ns 3.0 to ns ns 3.0 to ns 3.0 to db 3.0 to db 3.0 to 3.6 Symbol Parameter Conditions Vcc (V) tsk(p) Skew of Opposite Transitions of the Same Output (6) C L=5 pf, RL=50 Ω Figure MHz 550 MHz T A =- 40ºC to +85ºC Min. Typ. Max. Units 3.0 to ps tj Total Jitter (6) tr=t F=500ps (10-90%) at 480 Mbps RL=50 Ω, C L=5 pf, (PRBS=2 15 1) Note: 6. Guaranteed by characterization. Not tested in production. 3.0 to ps Capacitance Symbol Parameter Conditions T A =- 40ºC to +85ºC Min. Typ. Max. Units C IN Control Pin Input Capacitance V CC=0 V 1.5 CON D+/D- On Capacitance V CC=3.3 V, /OE=0 V, f=240 MHz Figure pf COFF D1n, D2n Off Capacitance V CC and /OE=3.3 V See Figure

6 Test Diagrams V SW V SW V ON R ON = V ON / I ON Dn Select = 0 orvcc Figure 3. On Resistance Dn C L Figure 5. AC Test Circuit Load I ON R L,, and C L are functions of the application environment (see AC Tables for specific values) C L includes test fixture and stray capacitance. R L NC I Dn(OFF) A Select = 0 orvcc **Each switch port is tested separately Figure 4. Off Leakage t RISE = 2.5ns V CC Input V /OE, 90% 90% V CC /2 V CC /2 V OH V SW t FALL = 2.5ns 90% 90% Output- V OL t ON t OFF Figure 6. Turn-On / Turn-Off Waveforms t RISE= 500ps t FALL = 500ps Input 0V t PLH 50% 50% 400mV t PHL +400mV -400mV 0V 90% 90% Output 50% 50% V OH V OL Output t PHL t PLH Figure 7. Propagation Delay (t Rt F 500 ps) Figure 8. Intra-Pair Skew Test t SK(P) 6

7 Test Diagrams (Continued) V SW1 V SW2 and are functions of the application environment (see AC Tables for specific values). Figure 10. Bandwidth Dn C L R L R L,, and C L are functions of the application environment (see AC Tables for specific values) C L includes test fixture and stray capacitance. Figure 9. Break-Before-Make Interval Timing Network Analyzer V IN V S NC V cc Input - 0V t RISE = 2.5ns 0.9*V out 90% V cc /2 t BBM and are functions of the application environment (see AC Tables for specific values). 0.9*V out Network Analyzer Figure 11. Channel Off Isolation Network Analyzer V IN V S V IN V S Off isolation = 20 Log ( / V IN ) and are functions of the application environment (see AC Tables for specific values). Crosstalk = 20 Log ( / V IN ) Figure 12. Non-Adjacent Channel-to-Channel Crosstalk Capacitance Meter S = 0 or V cc Capacitance Meter S = 0 or V cc Figure 13. Channel Off Capacitance Figure 14. Channel On Capacitance 7

8 Physical Dimensions 2X DETAIL A PIN#1 IDENT 0.05 C PIN#1 IDENT 0.10 C 0.08 C 0.025± ±.05 (9X) 0.40±.05 1 TOP VIEW SEATING PLANE SIDE VIEW 3 BOTTOM VIEW ± DETAIL A SCALE : 2X 6 A C B C 2X 1.40±.05 (0.20) 4X 0.20±.05 (10X) 1.00± ± ±.05 (0.60) 4X 0.10 C A B 0.05 C (9X) (10X) (10X) NOTES: RECOMMENDED LAND PATTERN X 0.45 OPTIONAL MINIMIAL TOE LAND PATTERN A. PACKAGE DOES NOT CONFORM TO ANY JEDEC STANDARD. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, D. LAND PATTERN RECOMMENDATION IS EXISTING INDUSTRY LAND PATTERN. E. DRAWING FILENAME: MKT-UMLP10Arev6. PACKAGE EDGE LEAD OPTION 1 SCALE : 2X LEAD OPTION 2 SCALE : 2X Figure Lead, Ultrathin Molded Leadless Package (UMLP) 8

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