FSA3200 Two-Port, High-Speed USB2.0 Switch with Mobile High-Definition Link (MHL )
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1 FSA3200 Two-Port, High-Speed USB2.0 Switch with Mobile High-Definition Link (MHL ) Features Low On Capacitance: 2.7 pf / 3.1 pf MHL / USB (Typical) Low Pow er Consumption: 30μA Maximum Supports MHL Rev. 2.0 MHL Data Rate: 4.68 Gbps VBUS Pow ers Device w ith No VCC Packaged in 16-Lead UMLP (1.8 x 2.6 mm) Over-Voltage Tolerance (OVT) on all USB Ports Up to 5.25 V w ithout External Components Applications Cell Phones and Digital Cameras Ordering Information Description The FSA3200 is a bi-directional, low -pow er, tw o-port, high-speed, USB2.0 and video data sw itch. Configured as a double-pole, double-throw (DPDT) sw itch for data and a single-pole, double-throw (SPDT) sw itch for ID; it is optimized for sw itching betw een high- or full-speed USB and Mobile Digital Video sources (MDV), including supporting the MHL Rev. 2.0 specification. The FSA3200 contains special circuitry on the sw itch I/O pins, for applications w here the VCC supply is pow ered off (VCC=0), that allow s the device to w ithstand an over-voltage condition. This sw itch is designed to minimize current consumption even w hen the control voltage applied to the control pins is low er than the supply voltage (VCC). This feature is especially valuable to mobile applications, such as cell phones, allow ing direct interface w ith the general-purpose I/Os of the baseband processor. Other applications include sw itching and connector sharing in portable cell phones, digital cameras, and notebook computers. Part Number Top Mark Operating Temperature Range Package FSA3200UMX GB -40 to +85 C 16-Lead, Ultrathin Molded Leadless Package (UMLP), 1.8 x 2.6 mm Figure 1. Analog Symbol All trademarks are the property of their respective owners Semiconductor Components Industries, LLC. Publication Order Number: November-2017, Rev. 2 FSA3200/D
2 Switch Power Operation In normal operation, the FSA3200 is pow ered from the VCC pin, w hich typically is derived from a regulated pow er management device. In special circumstances, such as production test or system firmw are upgrade, the device can be pow ered from the VBUS pin. In this mode of operation, a valid VBUS voltage is present (per USB2.0 specification) and VCC=0 V, typically due to a no-battery condition. With the SELn pins strapped LOW (via external resistor), the FSA3200 closes the USB path, enabling the initial programming of the system directly f rom the USB connector. Once the system has normal V BUS V CC Charge Pump & Regulator operating supply pow er w ith VCC present, the V BUS supply is not utilized and normal sw itch operation commences. Optionally, the Pow er Select Override (PSO) pin can be set HIGH to force the device to be pow ered from VBUS. The V BUS / V CC detection capability is not intended to be an accurate determination of the voltages present, rather a state condition detection to determine w hich supply should be used. These state determinations rely on the voltage conditions as described in the Electrical Characterization tables below. Figure 2. Simplified Logic of Sw itch Pow er Selection Circuit Table 1. Sw itch Power Selection Truth Table V CC V BUS PSO (1) Switch Power Source No sw itch pow er, sw itch paths high-z V BUS V CC V CC No sw itch pow er, sw itch paths high-z VBUS (2) V CC V BUS Notes: 1. Control inputs should never be left floating or unconnected. If the PSO function is used, a w eak pull-up resistor (3 MΩ) should be used to minimize static current draw. If the PSO function is not used, tie directly to. 2. PSO control is overridden w ith no VBUS and the pow er selection is sw itched to V CC. PSO Switch Power Selection Switch Power Source Switch Power Table 2. Data Switch Select Truth Table SEL1 (3) SEL2 (3) Function 0 0 D+/D- connected to USB+/USB-, IDCO connected to IDUSB 0 1 D+/D- connected to USB+/USB-, ID COM connected to ID MDV 1 0 D+/D- connected to MDV+/MDV-, IDCOM connected to IDUSB 1 1 D+/D- connected to MDV+/MDV-, ID COM connected to ID MDV 3. Control inputs should never be left floating or unconnected. To guarantee default sw itch closure to the USB position, the SEL pins should be tied to w ith a w eak pull- dow n resistor (3 MΩ) to minimize static current draw. 2
3 Pin Configuration Pin Definitions D+ D- PSO VCC SEL1 VBUS IDCOM USB+ IDMDV ID USB MDV+ USB- MDV- SEL2 Figure 3. Pin Assignments (Top-Through View) Pin# Name Description 1 Ground 2 D+ Data Sw itch Output (Positive) 3 D- Data Sw itch Output (Negative) 4 PSO Pow er Select Override 5 SEL1 Data Sw itch Select 6 USB- USB Differential Data (Negative) 7 USB+ USB Differential Data (Positive) 8 Ground 9 SEL2 ID Sw itch Select 10 MDV- MDV Differential Data (Negative) 11 MDV+ MDV Differential Data (Positive) 12 ID USB ID Sw itch MUX Output for USB 13 IDMDV ID Sw itch MUX Output for MDV 14 IDCOM ID Sw itch Common 15 V BUS Device Pow er w hen V CC Not Available 16 VCC Device Pow er from System (4) 4. Device automatically sw itches f rom V BUS w hen valid V CC minimum voltage is present
4 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit V CC, V BUS Supply Voltage V VCNTRL DC Input Voltage (SELn, PSO) (5) -0.5 VCC V VSW (6) DC Sw itch I/O Voltage (5) V I IK DC Input Diode Current -50 ma IOUT DC Output Current 100 ma T STG Storage Temperature C MSL Moisture Sensitivity Level (JEDEC J-STD-020A) 1 ESD Human Body Model, JEDEC: JESD22-A114 All Pins 3.5 IEC , Level 4, for D+/D- and V CC Pins (7) Contact 8.0 IEC , Level 4, for D+/D- and V CC Pins (7) Air 15.0 Charged Device Model, JESD22-C Notes: 5. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. 6. VSW refers to analog data sw itch paths (USB, MDV, and ID). 7. Testing performed in a system environment using TVS diodes. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit V BUS Supply Voltage Running f rom V BUS Voltage V V CC Supply Voltage Running from V CC V t RAMP(VBUS) Pow er Supply Slew Rate from V BUS µs/v tramp(vcc) Pow er Supply Slew Rate from VCC µs/v Θ JA Thermal Resistance 336 C /W V CNTRL Control Input Voltage (SELn, PSO) (8) V VSW(USB) Sw itch I/O Voltage (USB and ID Sw itch Paths) V kv V SW(MDV) Sw itch I/O Voltage (MDV Sw itch Path) V TA Operating Temperature C 8. The control inputs must be held HIGH or LOW; they must not float. 4
5 DC Electrical Characteristics All typical value are at T A=25 C unless otherw ise specified. Symbol Parameter Condition V CC (V) T A =- 40ºC to +85ºC Min. Typ. Max. VIK Clamp Diode Voltage IIN=-18 ma V VIH Control Input Voltage High SELn, PSO 2.7 to V VIL Control Input Voltage Low SELn, PSO 2.7 to V IIN IOZ(MDV) IOZ(USB) I OZ(ID) I CL(MDV) I CL(USB) I CL(ID) I OFF RON(USB) R ON(MDV) R ON(ID) R ON(MDV) RON(USB) R ON(ID) Control Input Leakage Off-State Leakage for Open MDV Data Paths Off-State Leakage for Open USB Data Paths Off-State Leakage for Open ID Data Path On-State Leakage for Closed MDV Data Paths (9) VSW=0 V to 3.6 V, VCNTRL=0 V to 1.98 V VSW=1.65 V MDV 3.45 V Unit µa µa VSW=0 V USB 3.6 V µa VSW=0 V ID 3.6 V µa V SW=1.65 V MDV 3.45 V µa On-State Leakage for Closed (9) USB Data Paths VSW=0 V USB 3.6 V µa On-State Leakage for Closed (9) ID Data Path Pow er-off Leakage Current (All I/O Ports) HS Sw itch On Resistance (USB to D Path) HS Sw itch On Resistance (MDV to D Path) LS Sw itch On Resistance (ID Path) Difference in RON Betw een MDV Positive-Negative Difference in RON Betw een USB Positive-Negative Difference in RON Betw een ID Sw itch Paths V SW=0 V ID 3.6 V µa VSW=0 V or 3.6 V, Figure µa V SW=0.4 V, I ON=-8 ma Figure 4 V SW=V CC-1050mV, ION=-8mA, Figure 4 V SW=3V, I ON=-8mA Figure 4 V SW=V CC-1050 mv, ION=-8 ma, Figure 4, V SW=0.4 V, I ON=-8 ma Figure 4 VSW=3 V, ION=-8 ma Figure Ω Ω Ω Ω Ω Ω RONF(MDV) Flatness for RON MDV Path VSW=1.65 V to 3.45 V, ION=-8 ma, Figure Ω I VBUS V BUS Quiescent Current VBUS=5.25 V, V CNTRL=0 V or 1.98 V, IOUT= µa ICC VCC Quiescent Current VBUS=0 V, VCNTRL=0 V or 1.98 V, IOUT= µa 9. For this test, the data sw itch is closed w ith the respective sw itch pin floating. 5
6 AC Electrical Characteristics All typical value are for V CC=3.3 V and T A=25 C unless otherw ise specified. Symbol Parameter Condition V CC (V) t ON toff Turn-On Time, SELn to Output Turn-Off Time, SELn to Output RL=50 Ω, C L=5 pf, VSW(USB)=0.8 V, VSW(MDV)=3.3 V, Figure 6, Figure 7 RL=50 Ω, CL=5 pf, VSW(USB)=0.8 V, VSW(MDV)=3.3V, Figure 6, Figure 7 tpd (10) Propagation Delay CL=5 pf, RL=50 Ω, Figure 6, Figure 8 t BBM Break-Before-Make (10) V ID=V MDV=3.3 V, V USB=0.8 V, R L=50 Ω, C L=5 pf, Figure 10 V S=1 V pk-pk, R L=50 Ω, Off Isolation (10) f=240 MHz, Figure 12 VS=400m Vpk-pk, RL=50Ω, f=240mhz, Figure 12 O IRR(MDV) OIRR(USB) Xtalk MDV XtalkUSB BW Non-Adjacent Channel (10) Crosstalk Differential -3 db Bandw idth (10) 10. Guaranteed by characterization. VS=1 V pk-pk, R L=50 Ω, f=240 MHz, Figure 13 V S=400 mv pk-pk, RL=50 Ω, f=240 MHz, Figure 13 V IN=1 V pk-pk, MDV Path, RL=50 Ω, CL=0 pf, Figure 11, Figure 16 V IN=400 mv pk-pk, USB Path, RL=50 Ω, C L=0 pf, Figure 11, Figure 17 ID Path, R L=50 Ω, C L=0 pf, Figure 11 T A =- 40ºC to +85ºC Unit Min. Typ. Max. 2.7 to ns 2.7 to ns 2.7 to ns 2.7 to ns 2.7 to db 2.7 to db 2.7 to db 2.7 to db 2.7 to GHz 100 MHz 6
7 USB High-Speed AC Electrical Characteristics Typical values are at T A= -40ºC to +85ºC. Symbol Parameter Condition V CC (V) Typ. Unit tsk(p) Skew of Opposite Transitions of the Same (11) CL=5 pf, RL=50 Ω, Figure to ps Output tj Total Jitter (11) tr=tf=500 ps (10-90%) at R L=50 Ω, CL=5 pf, 480 Mbps, PN7 11. Guaranteed by characterization. MDV AC Electrical Characteristics Typical values are at TA= -40ºC to +85ºC. 3.0 to ps Symbol Parameter Condition V CC (V) Typ. Unit t SK(P) Skew of Opposite Transitions of the Same (12) Output RPU=50 Ω to VCC, CL=0 pf 3.0 to ps (12) f=2.25 Gbps, PN7, t J Total Jitter RPU=50 Ω to V CC, C L=0 pf 12. Guaranteed by characterization. Capacitance Typical values are at T A= -40ºC to +85ºC. 3.0 to ps Symbol Parameter Condition Typ. Unit C IN Control Pin Input Capacitance (13) V CC=0 V, f= 1 MHz 1.5 C ON(USB) USB Path On Capacitance (13) V CC=3.3 V, f=240 MHz, Figure COFF(USB) USB Path Off Capacitance (13) VCC=3.3 V, f=240 MHz, Figure C ON(MDV) MDV Path On Capacitance (13) V CC=3.3 V, f=240 MHz, Figure COFF(MDV) MDV Path Off Capacitance (13) VCC=3.3 V, f=240 MHz, Figure Guaranteed by characterization. pf 7
8 Test Diagrams 14. HSD refers to the high-speed data USB or MDV paths. Input 0V Figure 4. On Resistance Figure 6. AC Test Circuit Load t PLH HS D n V SW G ND 50% V O N R O = V O / I ON Dn Select 50% I ON GN D V S el= 0 or V C 400mV t PHL NC I Dn(OFF) A Select V Sel = 0 orvcc **Each switch port is tested separately Figure 5. Off Leakage V SW Figure 7. Turn-On / Turn-Off Waveforms +400mV -400mV t RIS E = 2.5 n s V CC 90% 90% Inp u t V SEL1, V SEL V CNTRL-HI 10% V OH 10% t RISE= 500ps V CNTRL-HI 90% 90% 0V t F AL L = 2. 5 ns 10 % 90 % 90% Output- V OUT VO L t ON t O FF t FALL = 500ps 10% Output 50% 50% V OH V OL Output t PHL t PLH Figure 8. Propagation Delay (t Rt F 500 ps) Figure 9. Intra-Pair Skew Test t SK(P) 8
9 Test Diagrams (Continued) Network Analyzer V S V S V IN V IN V SW1 V Sel HSD n FSA3200 V SW2 Figure 11. Insertion Loss Dn C L R L, R L Figure 10. Break-Before-Make Interval Timing V S, and R T are function of application environment (see AC/DC Tables for values) V Sel V OUT Figure 12. Channel Off Isolation Crosstalk = 20 Log (V OUT / V IN ) Figure 13. Non-Adjacent Channel-to-Channel Crosstalk Vcc Input - V Sel 0V V OUT t RISE = 2.5ns 10% 0.9*Vout and C L are function of application 90% Vcc/2 t BBM environment (see AC Tables for specific values) C L includes test fixture and stray capacitance Network Analyzer R T R T V OUT V OUT NC R T V Sel 0.9*Vout and R T are functions of the application environment (see AC Tables for specific values). and R T are functions of the application environment (see AC Tables for specific values). R T Network Analyzer V IN R T V S V OUT Network Analyzer V IN R T V OUT V S Off isolation = 20 Log (V OUT / V IN ) Capacitance Meter HSD n S V Sel = 0 or V cc Capacitance Meter HSD n S V Sel = 0 or V cc HSD n HSD n Figure 14. Channel Off Capacitance Figure 15. Channel On Capacitance 9
10 Insertion Loss One of the key factors for using the FSA3200 in mobile digital video applications is the small amount of insertion loss experienced by the received signal as it passes through the sw itch. This results in minimal degradation of the received eye. One of the w ays to measure the quality of the high data rate channels is using balanced Figure 16. MDV Path SDD21 Insertion Loss Curve ports and 4-port differential S-parameter analysis, particularly SDD21. Bandw idth is measured using the S-parameter SDD21 methodology. Figure 16 show s the bandw idth (GHz) for the MDV path and Figure 17 the bandw idth curve for the USB path. Figure 17. USB Path SDD21 Insertion Loss Curve 10
11 Typical Applications Figure 18 show s the FSA3200 utilizing the VBUS connection from the micro-usb connector. The 3M resistor is used to ensure, for manufacturing test via the micro-usb connector, that the FSA3200 configures for Baseband or Application Processor Baseband or Application Processor D+ D- UART_Tx UART_Rx Spkr_R Spkr_L D+ D- UART_Tx UART_Rx Spkr_R Spkr_L FSA9280A ID CBUS HDMI to MHL Bridge connectivity through the FSA9280A accessory sw itch. Figure 19 show s the configuration for the FSA3200 self pow ered by the battery only. MHL_SEL 16 V BAT 15 FSA To USB Battery Charging Block 100 ohm M Figure 18. Typical FSA3200 Application Using V BUS FSA9280A ID CBUS HDMI to MHL Bridge 12 USB_D+ 7 USB_D MHL+ 11 MHL USB_D+ 7 USB_D MHL+ 11 MHL- 10 MHL_SEL 16 V BAT 15 FSA M VBUS D+ D- ID microusb Connector To USB Battery Charging Block VBUS D+ D- ID microusb Connector Figure 19. Typical FSA3200 Self-Powered Application Using VBAT 11
12 Physical Dimensions 2X 0.10 C PIN#1 IDENT 0.10 C 0.08 C PIN#1 IDENT 1.80 TOP VIEW 0.55 MAX BOTTOM VIEW 2X C C A B 0.05 C NOTES: A. PACKAGE DOES NOT FULLY CONFORM TO JEDEC STANDARD. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, D. LAND PATTERN RECOMMENDATION IS BASED ON FSC DESIGN ONLY. E. DRAWING FILENAME: MKT-UMLP16Arev4. F. TERMINAL SHAPE MAY VARY ACCORDING TO PACKAGE SUPPLIER, SEE TERMINAL SHAPE VARIANTS A SEATING C PLANE SIDE VIEW B (16X) RECOMMENDED LAND PATTERN LEAD OPTION 1 SCALE : 2X (15X) 2.90 TERMINAL SHAPE VARIANTS X 15X PIN 1 NON-PIN 1 Supplier X 15X PIN 1 NON-PIN 1 Supplier 2 R0.20 PACKAGE EDGE LEAD OPTION 2 SCALE : 2X Figure Lead, Ultrathin Molded Leadless Package (UMLP) Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact an ON Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor s worldwide terms and conditions, specifically the warranty therein, which covers ON Semiconductor products. 12
13 ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor s product/patent coverage may be accessed at /site/pdf/patent-marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. Typical parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor E. 32nd Pkwy, Aurora, Colorado USA Phone: or Toll Free USA/Canada Fax : or Toll Free USA/Canada orderlit@onsemi.com N. Amer ican Technical Support: Toll Free USA/Canada. Eur ope, Middle East and Afr ica Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Or der Literature: For additional information, please contact your local Sales Representative 13
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Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers
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