Synchronized Crystal Oscillator, General Requirements. AH-ASCMXXXG-X Series PATENT PENDING

Transcription

1 PATENT PENDING Description The Synchronized Crystal Oscillator is intended for use in the system, which requires multiple clocks in different nodes of the system to run synchronously in frequency without master clock. The Synchronized Crystal Oscillator is ideal for mission critical applications where optimization of system speed, bandwidth and redundancy is desired. The module has two differential (complementary) outputs with logic type specified by the customer: PECL, LVDS, or HCSL compatible. It covers the frequency range of 25 MHz to 500 MHz. Device also has one additional output for synchronization at lower frequency and one internally AC-coupled synchronization input. Synchronized Crystal Oscillator is packaged in 17x14x6 mm (tentatively) FR4 based SMD package with 8 gold plated pads. Applications and Features Unlimited scalability/easily expandable Ideal for blade applications Provides a complete, system-wide clock redundancy solution High reliability systems with multiple synchronous clocks. Greatly improved system reliability Low Phase Noise and jitter No master clock, no PLL required for the system Eliminates additive jitter degradation associated with clock distribution Hot swappable Synchronize independent of power application sequence/no special power sequence required Improves Phase jitter at every node While in sync all units exhibit identical phase noise characteristics Low cost COTS/Dual use

2 Creating a Part Number AH - A SCM X X X G - X Package code AH 8 pad 17x14 SMD Operating Voltage A 3.3 V ± 5% Enable Option L Enable Low N N/C Output Option P PECL L LVDS H HCSL Temperature Range, ºC A 0 to 50 B 0 to 70 C -20 to 70 D -40 to 85 9 Customer Specific Environmental L Contains a level of lead that is in excess of RoHS directive and is not designed for reflow R RoHS compliant Frequency Stabilty, Overall, ppm G ±50

3 Drawing Specification Electrical Connections Pin out Pin 1=Vcc; Pin 2=Sync In; Pin 3=Sync Out; Pin 4=GND; Pin 5=Output; Pin 6= Comp Output; Pin 7=GND; Pin 8=En/Dis Operating temp. Range Mechanical Shock Thermal Shock Vibration Hermetic Seal Soldering conditions Environmental and Mechanical Characteristics see part # table Per MIL-STD-202, Method 213, Cond. A Per MIL-STD-883, Method 1011, Cond. A Per MIL-STD-883, Method 2007, Cond. A Leak rate less than 1x10-8 atm.cc/s of helium, crystal only. See MAX reflow profile below MAX Reflow Profile

4 Absolute Maximum Ratings Parameter Symbol Value Unit Operating Temperature Range To -40 to +85 ºC Storage Temperature Range Tst -50 to +90 ºC Supply Voltage Vcc -0.5 to 5.5 V Control Voltage Vc -0.5 to 5.5 V Enable/Disable Voltage Ven/dis 0 to Vcc V Electrical Parameters Parameter Symb Conditions, Note MIN TYP MAX Unit Nominal Frequency, Fo MHz Differential Outputs Synchronization Fs MHz frequency Supply Voltage Vcc Code A V Supply current Icc Fo = 200 MHz ma Load At receiving end Ohm between the outputs Output Levels Vod Differential amplitude mv Amplitude error 50 mv Vof Offset Voltage V LVDS OUTPUT LVPECL OUTPUT HCSL OUTPUT Jitter, see note 4 Offset voltage error 50 mv Duty Cycle (Symmetry) At outputs crossing, room temperature 45/55 50/50 55/45 % Rise/Fall Time Tr/Tf 20 to 80, 80 to 20 % ns Load Output to Vcc-2V, or 50 Ohm Thevenin Equivalent Output Levels Voh overall Vcc- V Vol Vcc Duty Cycle At 50% of output 45/55 50/50 55/45 % (Symmetry) voltage swing Rise/Fall Time Tr/Tf 20 to 80, 80 to 20 % ns Load At receiving end each 50 Ohm output, Rs = 0 Ohm Output Levels Voh Output High 1, mv Vol Output Low 1,2 0 V Vcr Crossing Point mv Duty Cycle (Symmetry) At outputs crossing, room temperature 45/55 50/50 55/45 % Rise/Fall Time Tr/Tf From to V ns Integrated J Integrated from Phase ps Noise, 12 KHz to 20 MHz, RMS Wavecrest characterized 100Hz to 80KHz,RMS 1.0 ps 50 KHz to 80 MHz 0.3 ps Random 2.5 ps period, Accumul. 21 ps

5 , pk-to-pk Determini stic F = ps MHz Sub-harmonics F = 200 MHz dbc Phase Noise (Δf) dbc/hz Frequency Stability, individual unit, see note 3. Frequency Stability in ensemble, up to 100 units Synchronization Range, individual unit Number of SCM per system Settling Time, hotswap, or powered up, powered down ΔF/F Overall Initial Calibration Over temp 0 to 70 ºC -40 to 85 ºC ±30 ±5 ±10 ±15 ±35 ppm Aging, 1 st year 15 years ±1 ±5 Load, Vcc, shock, ±5 Vibration, reflow ΔF/F Overall ±40 ppm ΔF/F Vsync in > 1.5 V pk-pk ±40 ppm Ts After Vcc reaches 0.9 Vcc nom to plugged-in unit See note ms Sync out delay Td 1 s Enable Pin 8 = Low, 0 to Vcc- Enabled 1.62 V, or floating V Disable, see note2. Pin 2 = High, Vcc- Disabled, Pin5 = Logic 1, V to Vcc Pin6 = Logic 0 V Phase Synchronized Tolerance see note 5 10 Degrees Notes 1. Consult Factory 2. En/Dis feature applies only to the clock outputs, the oscillator will keep running in sync and Sync Out will be enabled. 3. Though it appears that there s very little margin of Sync range vs. Overall stability, following considerations should be taken into account a. The temperature difference in the same system between the nodes is much smaller than operating temperature range, assumed not to be greater than 10ºC b. Frequency drift of different units caused by aging, Vcc variations and reflow goes in the same direction Therefore in real life the margin will increase by ppm. 4. Specified phase noise and jitter is for individual units tested separately. Using an ensemble of synchronized clock modules can produce system level phase noise and jitter performance akin to individual unit specified performance. This assumes that appropriate synchronization ensemble layout, isolation, and power supply filter techniques were used. 5. Based on propagation delay related skew between units being negligible.

6 The following oscilloscope pictures (taken on an Agilent 54845A) illustrate the basic concept of all oscillators being synchronous during normal operation. Note that all 12 oscillators are synchronous.

7 The following plot is from a Modulation Domain Analyzer (HP 53310A) showing the frequency change verses time of position 1 as position 2 is turned on. Note that the full scale is about 60 ppm. The shift in frequency is about 4ppm negative and then about 6 ppm positive from the nominal position 1 starting frequency. This next plot show a wider view of what happens looking at position 1 with position 2, then 3, then 4, etc. switched in.

8 Jitter on Wavecrest Histogram analysis (ps except Dj=fs) 1 sigma Peak to peak Condition Avg rms Dj Accum Accum One osc on Two osc on All 12 osc on Jitter data on various output conditions were taken. Jitter data was taken on a Wavecrest DTS RMS jitter integrated from Phase noise, 12 khz to 20 MHz = 85 fs for all cases. Start time of the oscillators was measured under various conditions: Start Start time using power supply turn on one at a time time (ms) Unit Unit Unit Unit Unit Unit Unit Unit Unit Unit 10 7 Unit Unit With All units on using power supply Unit 1 3 Unit 2 3 Unit 12 3 W/2,4,7,10,11 on 7.76

9 The following is some of the phase noise data taken on the modules. The first plot is the difference between having one oscillator, two oscillators and all 12 oscillators on in the 10Hz to 1 khz range where the difference is the greatest. The second plot shows a typical phase noise plot of one oscillator from 10 Hz to 1 MHz. at 10 Hz PN at 100Hz at 1 khz at 10 khz at 100 khz at 1 MHz One osc. on Two osc. on All osc. On