Model 653 Very Low Jitter LVPECL or LVDS Clock
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- Grace Warner
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1 Features Ceramic Surface Mount Package Very Low Phase Jitter Performance, 500fs Maximum Fundamental or 3 rd Overtone Crystal Design Frequency Range MHz * +2.5V or +3.3V Operation Output Enable Standard Tape and Reel Packaging, EIA418 Applications SerDes Storage Area Networking Broadband Access SONET/SDH/DWDM PON Ethernet/GbE/SyncE Fiber Channel Test and Measurement Part Dimensions: mm 62.00mg Standard Frequencies 25.00MHz MHz MHz 50.00MHz MHz MHz MHz MHz MHz 74.25MHz MHz MHz MHz MHz MHz * See Page 9 for additional developed frequencies. Check with factory for availability of frequencies not listed. Description CTS is a low cost, high performance clock oscillator supporting differential LVPECL or LVDS outputs. Employing the latest IC technology, M653 has excellent stability and very low jitter/phase noise performance. Ordering Information Model 653 Output Frequency Code Frequency Type [MHz] Stability P XXX or XXXX 3 Temperature Supply Packaging Range Voltage I 3 T Code Output Code Stability Code Voltage P LVPECL Pin 1 Enable 6 ±20ppm Vdc L LVDS Pin 1 Enable 5 ±25ppm Vdc E LVPECL Pin 2 Enable 3 ±50ppm V LVDS Pin 2 Enable 2 ±100ppm Code Frequency Code Temp. Range Code Packing A 10 C to +60 C T 1k pcs./reel Product Frequency Code 1 C 20 C to +70 C I 40 C to +85 C Notes: 1] Refer to document , Frequency Code Tables. 3digits for frequencies <100MHz, 4digits for frequencies 100MHz or greater. 2] Consult factory for availability of 6I Stability/Temperature combination. Not all performance combinations and frequencies may be available. Contact your local CTS Representative or CTS Customer Service for availability. This product is specified for use only in standard commercial applications. Supplier disclaims all express and implied warranties and liability in connection with any use of this product in any noncommercial applications or in any application that may expose the product to conditions that are outside of the tolerances provided in its specification. DOC# Rev. C Page 1 of 9
2 Operating Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Maximum Supply Voltage V CC V Supply Voltage Supply Current ±5% V LVPECL Maximum Load LVDS Operating Temperature T A +25 C Storage Temperature T STG C Frequency Stability PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Frequency Range LVPECL LVDS Frequency Stability [Note 1] Δf/f O 20, 25, 50 or 100 ±ppm Aging Δf/f 25 First +25 C, nominal V CC 3 3 ppm Output Parameters PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Output Type LVPECL Output Load R L Terminated to V CC 2.0V 50 Ohms Output Voltage Levels V CC I CC f O ] Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 1st year aging V OH V CC V CC PECL Load, 20 C to +70 C V OL V CC V CC V OH V CC V CC PECL Load, 40 C to +85 C V OL V CC V CC Output Duty Cycle V CC 1.3V % Rise and Fall Time T R, T 20%/80% Levels, R L = 50 Ohms ns ma MHz V V Output Type LVDS Output Load R L Between Outputs 100 Ohms Output Voltage Levels V OH LVDS Load V OL V Output Duty Cycle 1.25V % Differential Output Voltage V OD R L = 100 Ohms mv Offset Voltage V OS LVDS Load V Rise and Fall Time T R, T 20%/80% Levels, R L = 100 Ohms ns DOC# Rev. C Page 2 of 9
3 Output Parameters PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Start Up Time T S Application of V CC 2 5 ms Enable Function [Standby] Enable Input Voltage V IH Pin 1 or 2 Logic '1', Output Enabled 0.7V CC V Disable Input Voltage V IL Pin 1 or 2 Logic '0', Output Disabled 0.3V CC V Disable Time T PLZ Pin 1 or 2 Logic '0', Output Disabled 200 ns Enable Time T PLZ Pin 1 or 2 Logic '1', Output Enabled 2 ms Phase Jitter, RMS tjrms Bandwidth 12 khz 20 MHz fs Period Jitter, RMS pjrms 2.6 ps Period Jitter, pkpk pjpkpk 25 ps Enable Truth Table Pin 1 or Pin 2 Pin 4 & Pin 5 Logic 1 Output Open Output Logic 0 High Imp. Test Circuit LVPECL LVDS Output Waveform LVPECL or LVDS DOC# Rev. C Page 3 of 9
4 Performance Data Phase Noise [typical] 25MHz, LVPECL, V CC = 3.3V, T A = +25 C 100MHz, LVPECL, V CC = 3.3V, T A = +25 C DOC# Rev. C Page 4 of 9
![Performance Data Phase Noise [typical]](/docs-images/96/128022060/images/5-1.jpg "312.50MHz, LVPECL, V CC = 3.")
5 Performance Data Phase Noise [typical] MHz, LVPECL, V CC = 3.3V, T A = +25 C MHz, LVDS, V CC = 3.3V, T A = +25 C DOC# Rev. C Page 5 of 9
6 Phase Noise Tabulated Typical, V CC = 3.3V, T A = +25 C PARAMETER SYMBOL CONDITIONS TYP UNIT PARAMETER SYMBOL CONDITIONS TYP UNIT 25.00MHz MHz Phase Noise Single Side Band Phase Noise Single Side 10Hz 10Hz 100Hz 100Hz 1kHz kHz kHz 10kHz 100kHz 100kHz 1MHz 1MHz 5MHz 5MHz Phase Jitter, RMS tjrms Integration Bandwidth 12kHz 20MHz fs Phase Jitter, RMS tjrms Integration Bandwidth 12kHz 20MHz fs PARAMETER SYMBOL CONDITIONS TYP UNIT PARAMETER SYMBOL CONDITIONS TYP UNIT MHz MHz Phase Noise Single Side Band Phase Noise Single Side 10Hz 10Hz 100Hz 100Hz 1kHz kHz kHz 10kHz 100kHz 100kHz 1MHz 1MHz 10MHz 20MHz Phase Jitter, RMS tjrms Integration Bandwidth 12kHz 20MHz fs Phase Jitter, RMS tjrms Integration Bandwidth 12kHz 20MHz fs DOC# Rev. C Page 6 of 9
7 Mechanical Specifications Package Drawing CTS**D 653OSTV xxxx Marking Information 1. ** Manufacturing Site Code. 2. D Date Code. See Table I for codes. 3. O Output Type; P or E = LVPECL, L or V = LVDS. 3. ST Frequency Stability/Temperature Code. [Refer to Ordering Information] 4. V Voltage Code; 3 = 3.3V, 2 = 2.5V. 5. xxxx Frequency Code. 3digits, frequencies below 100MHz 4digits, frequencies 100MHz or greater [See document , Frequency Code Tables.] Recommended Pad Layout Notes 1. JEDEC termination code (e4). Barrierplating is nickel [Ni] with gold [Au] flash plate. 2. Reflow conditions per JEDEC JSTD020; +260 C maximum, 20 seconds. 3. MSL = 1. Pin Assignments Pin Symbol Function 1 EOH or N.C. Enable [std] or No Connect 2 N.C. or EOH No Connect or Enable [opt] 3 GND Circuit & Package Ground 4 Output RF Output 5 Output Complimentary RF Output 6 V CC Supply Voltage Table I Date Code MONTH YEAR JAN FEB MAR APR MAY JUN JUL AUG SEP OCT NOV DEC A B C D E F G H J K L M N P Q R S T U V W X Y Z a b c d e f g h j k l m n p q r s t u v w x y z DOC# Rev. C Page 7 of 9
8 Packaging Tape and Reel Tape Drawing Reel Drawing Notes 1. Device quantity is 3k pieces maximum per 180mm reel. 2. Complete CTS part number, frequency value and date code information must appear on reel and carton labels. DOC# Rev. C Page 8 of 9
9 Addendum Additional Developed Frequencies MHz A A A Frequency Codes for Cover Page Table MHz A DOC# Rev. C Page 9 of 9
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FD5T Series FD51xxT-32.768KHz Pletronics FD51T Series is a quartz crystal controlled precision square wave generator Output frequency 32.768KHz Selectable low jitter or spread spectrum output. Device characteristics
Logic & Supply Voltage: HC = HCMOS +5V L = LVHCMOS +3.3V P = LVPECL +3.3V
. and 5.0Vdc -.000MHz to 56.2MHz Description Q-Tech s surface-mount QTCV56 VCXOs consist of an IC 5Vdc,.Vdc clock square wave generator and a miniature strip AT quartz crystal built in a low profile ceramic
DSC x 1.2 mm Low-Power Ultra-Miniature Oscillator. General Description. Features
1.6 x 1.2 mm General Description The is an ultraminiature, lowprofile complete timing solution in a 1.6 x 1.2 mm footprint. The device is available in frequencies from 1 to 150 MHz with frequency stability
Solder Dip Options T = Standard S = Sn60Pb40 G=SAC305. Package 86 =Leaded 80 = Formed Leads 85=SMT. VCXO model
Description Q-Tech s 5x7mm LVCMOS Voltage Controlled Crystal Oscillators consist of an IC operating at a supply voltage 3.3Vdc and a miniature strip quartz crystal that operates at the fundamental frequency.
Rakon Product Proposal
RS1490P XO `Tiger' SMD Clock Oscillator Series High Performance PLL Crystal Clock Oscillator. Product description This PLL XO offers ultra low RMS phase jitter and high frequency stability in an industry
CMOS/LVCMOS HF VCXO AE-X32BXX-X Series
CMOS/LVCMOS HF VCXO Description The AE-X32BXX Series of voltage controlled crystal oscillators (VCXO) provides high frequency with CMOS/LVCMOS output. The device does not use any frequency multiplication,
VS-751 VS-751. Dual Frequency VCSO. Description. Features. Applications. Block Diagram. Vcc COutput Output SAW 1 SAW 2. Vc FS Gnd
VS-751 Dual Frequency VCSO VS-751 The VS-751 is a SAW based voltage controlled oscillator that operates at the fundamental frequencies of the internal SAW filters. These SAW filters are high-q quartz devices
Ultra Low Quiescent Current 5V/150mA Fixed-Voltage Ultra Low LDO
Ultra Low Quiescent Current 5V/150mA Fixed-Voltage Ultra Low LDO DESCRIPTION TS4264 is a 5V low-drop fixed-voltage regulator in an SOT-223 package. The IC regulates an input voltage in the range of 5.5V
Low-Jitter I 2 C/SPI Programmable CMOS Oscillator
Datasheet General Description The DSC2110 and series of programmable, highperformance CMOS oscillators utilize a proven silicon MEMS technology to provide excellent jitter and stability while incorporating
DSC400. Configurable Four Output, Low Jitter Crystal-less Clock Generator. General Description. Block Diagram. Applications.
DSC400 Configurable Four Output, Low Jitter Crystalless Clock Generator General Description The DSC400 is a four output crystalless clock generator. It utilizes Micrel s proven PureSilicon MEMS technology
VVC1 VVC2 Voltage Controlled Crystal Oscillator
VVC1 VVC2 Voltage Controlled Crystal Oscillator Features The VVC1 Voltage Controlled Crystal Oscillator VCXO with a CMOS output Small 5.0 X 7.0 X 1.9 mm package Output frequencies to 66 MHz 5.0 or 3.3
SiT9102. Benefits. Features. Applications. Block Diagram. Pinout. LVPECL / HCSL / LVDS / CML 1 to 220 MHz High Performance Oscillator
Features Extremely low RMS phase jitter (random)
PSE Technology Corporation
PSE Technology Corporation SPECIFICATION FOR APPROVAL CUSTOMER NOMINAL FREQUENCY HOLDER TYPE SPEC. NO. ( P/N ) CUSTOMER P/N ISSUE DATE VERSION 50.000000 MHz TYPE FK 3.2x2.5 SEAM SEALED CRYSTAL CLOCK OSCILLATOR
Features. o HCSL, LVPECL, or LVDS o HCSL/LVPECL, HCSL/LVDS, LVPECL/LVDS. o Ext. Industrial: -40 to 105 C. o o. o 30% lower than competing devices
DSC55703 General Description The DSC55703 is a crystalless, two output PCI express clock generator meeting Gen1, Gen2, and Gen3 specifications. The clock generator uses proven silicon MEMS technology to
PSE Technology Corporation
PSE Technology Corporation SPECIFICATION FOR APPROAL CUSTOMER NOMINAL FREQUENCY PRODUCT TYPE SPEC. NO. ( P/N ) CUSTOMER P/N ISSUE DATE ERSION 156.250000 MHz TYPE UX 7.0x5.0 SEAM SEALED CRYSTAL CLOCK OSCILLATOR
PECL, LVDS, CMOS Output Low Jitter SMD Crystal Oscillator
PECL, LDS, CMOS Output Low Jitter SMD Crystal Oscillator 7. x. x 1.mm Moisture Sensitivity Level (MSL) This product is Hermetically Sealed and not Moisture Sensitive - MSL = N/A: Not Applicable FEATURES:
BLOCK DIAGRAM. Functionality Table 1 details the differences between the parts to assist designers in selecting the optimal part for their design.
FEATURES LVPECL Outputs Optimized for Very Low Phase Noise (-165dBc/Hz) Up to 800MHz Bandwidth Selectable 1, 2 Output Selectable Enable Logic 3.0V to 3.6V Operation RoHS Compliant Pb Free Packages BLOCK