Logic & Supply Voltage: HC = HCMOS +5V L = LVHCMOS +3.3V P = LVPECL +3.3V

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1 . and 5.0Vdc -.000MHz to 56.2MHz Description Q-Tech s surface-mount QTCV56 VCXOs consist of an IC 5Vdc,.Vdc clock square wave generator and a miniature strip AT quartz crystal built in a low profile ceramic package with gold plated contact pads. Features Broad frequency range from.000mhz to 56.2MHz Small footprint HCMOS, LVHCMOS, LVPECL logic 5.0Vdc,.Vdc supply Operating temperature -40ºC to +85ºC available Tri-State Output Standard Hermetically sealed ceramic package Fundamental and rd Overtone designs Military screening tests per MIL-PRF-5 available Tape and reel packaging Lead Free, Compliant Applications Designed to meet today s requirements for low voltage applications Gun launched munitions and systems Smart munitions Instrumentation Ethernet/SynchE SONET Microprocessor clock Logic & Supply Voltage: HC = HCMOS +5V L = LVHCMOS +.V P = LVPECL +.V Ordering Information Sample part number QTCV56LDK2-.000MHz QTCV56 L D K MHz Output Frequency Screening Blank = Unscreened M = Per MIL-PRF-5, Level B See our Stock List (Updated Monthly) Tristate D = Tristate Absolute Pull Range vs. Temperature Code: L2 = ± 00ppm APR at -0ºC to +70ºC L7 = ± 00ppm APR at -40ºC to +85ºC K2 = ± ppm APR at -0ºC to +70ºC K7 = ± ppm APR at -40ºC to +85ºC J2 = ± 0ppm APR at -0ºC to +70ºC J7 = ± 0ppm APR at -40ºC to +85ºC Other Options Available For An Additional Charge Hot Solder Dip Sn60/Pb40 per MIL-PRF 5 Specifications subject to change without prior notice. Frequency stability vs. temperature codes may not be available in all frequencies. For Non-Standard requirements, contact Q-Tech Corporation at Sales@Q-Tech.com

2 Package Outline and Pin Connections Dimensions are in inches (mm). and 5.0Vdc -.000MHz to 56.2MHz Pin No. Function VOLTAGE CONTROL 2 ENABLE/DISABLE GND/CASE 4 OUTPUT 5 COMP. OUTPUT, OR NC 6 VDD An external bypass capacitor 0.µF or 0.0µF is required between Vdd and GND Marking Line : QXXX.XXXXXX (Q for Q-Tech, no space 9 or 0 Characters of Frequency including decimal) Line 2: Dot (Pin Indicator) + Date code (YY/WW), Internal Traceability Code Package Information Termination pads (4x), Electro nickel plating.27µm ~ 8.89µm typ., with gold 0.µm ~.0µm flash plate Weight: 0.057g typ. 2

3 Electrical Characteristics Parameters QTCV56HC QTCV56L QTCV56P Output frequency range (Fo).544MHz MHz.000MHz.000MHz MHz 56.2MHz Logic HCMOS LVCMOS LVPECL Supply voltage (Vdd) 5.0Vdc ± 0%.Vdc ± 5% Absolute Pull Range (APR) See Part Number on Page Linearity 5% typ. Operating temperature (Topr) See Part Number on Page Storage temperature (Tsto) -62ºC to + 25ºC Operating supply current (No Load) Symmetry (% of ouput waveform ) 8mA typ. ma max. 5mA typ. 40mA max. ma typ. 90mA max. 45/55% Rise and Fall times 5ns max. 0.ns typ. 0.5ns max. Output Load 5pF max. Ω into Vdd-2V Start-up time (Tstup) 0ms max. Output Enable/Disable (Vih/Vil) Control Voltage Range for Pull Range (Vc) Control Voltage Input Impedance (Zin) 0.9*Vdd min. / 0.*Vdd max. 0.5V min. 4.5V max. 0.V min..0v max. MΩ min. 0MΩ min. Control Voltage Modulation BW 0 khz min. 20 khz min. Period Jitter Typical Pk-Pk (6.44 MHz) RMS (6.44 MHz) 2ps.0ps Jitter, RMS (2kHz to 20MHz) N/A 0.2ps typ. 0.5ps max. N/A Phase Noise Typical 0 Hz 00 Hz khz 0 khz 00 khz MHz 0 MHz Aging -6 dbc/hz -97 dbc/hz -29 dbc/hz -44 dbc/hz -59 dbc/hz -64 dbc/hz 0 years aging included in Frequency Stability (at MHz) -68 dbc/hz -98 dbc/hz -25 dbc/hz -48 dbc/hz -67 dbc/hz

4 VOH Tr CMOS Output Waveform (Typical) TH SYMMETRY = x 00% T Tf. and 5.0Vdc -.000MHz to 56.2MHz Vdd 0.9xVdd 0.5xVdd Vcc Test Circuit Vcc-2V Q Q VDD ^ IDD + _.uf.0uf Vc 6 4 ^ + _ IC OUT.5pF VOL TH T 0.xVdd GND Vc Vcc-2V STANDARD TERMINATION LVPECL cmos vcxo The Tristate function on pin 2 has a built-in pull-up resistor so it can be left floating or tied to Vdd without deteriorating the electrical performance. Reflow Profile TYPICAL REFLOW PROFILE FOR Sn-Pb ASSEMBLY Embossed Tape and Reel Information FEEDING (PULL) DIRECTION TEMP(*C) 2 Ramp up (ºC/s Max) 240º.75±0. 0.±.005 ø.5 2.0±0. 4.0± º min. 240º max. s max. Ramp down (6ºC/s Max) 5º MAX B P/N FREQUENCY D/C S/N 7.5±0. 6.0± s max s max. C ø.5 8±0. A 5.4±0. 25 ø.0± Time (s) 2.5 ø80± ø78± 20º Environmental and Mechanical Specifications Dimensions are in mm. Tape is compliant to EIA-48-A. Package A B C QTCV ±0. 5. ±0..40 ±0. Reel size (Diameter in mm) Qty per reel (pcs) 78,000 Environmental Test Test Conditions Temperature cycling MIL-STD-88, Method 00, Cond. B Constant acceleration MIL-STD-88, Method 200, Cond. A, Y Seal: Fine and Gross Leak MIL-STD-88, Method 04, Cond. A and C Vibration sinusoidal MIL-STD-202, Method 204, Cond. D Shock, non operating MIL-STD-202, Method 2, Cond. I Resistance to solder heat MIL-STD-202, Method 20, Cond. B Resistance to solvents MIL-STD-202, Method 25 Solderability MIL-STD-202, Method 208 ESD Classification MIL-STD-88, Method 05, Class Moisture Sensitivity Level J-STD-020, MSL= 4

5 . and 5.0Vdc -.000MHz to 56.2MHz DCO REV REVISION SUMMARY PAGE DATE 666 A 804 B Replace LVDS test circuit with CMOS test circuit (LVDS not offered) 4 Add Linearirty to table Supply current changed to 8/ 5/40 /90 from /90 for all Control voltage impedance changed to k typ/m min from 2M min Add jitter and phase noise information Fix Package Outline (bypass capacitor had incorrect connections) Was: Connected to pins and 5 2 Is Now: Connected to pins and 6 Fix CMOS VCXO Test Circuit pinout numbers, add missing Ground 4 2//207 /29/208 5