TONE DECODE FILTER CLKS CLKS CLKS/XTAL DIGITAL INTERFACE AND CLOCK GENERATION CLKS/XTAL A0-A5 D0-D10 CLK. 300Hz AUDIO FILTER + -

Transcription

1 D UIN MX465 OW VOG SS NODR/DODR with x and Rx udio Filters Features Meets I/I-603 Standards 47 SS ones + Notone X/RX Speech Filters Improved Sinad Serial or arallel rogramming asy µ Interface Scanning on any hannel Standard 4Mz Xtal (See MX165 for 1Mz) ow Voltage 3.3V to 5.0V pplications Mobile Radio hannel Sharing Scan runking Wireless Intercom raffic ontrol ookswitch Supervision Repeater ontrol ON IN ON IN FIR f ON KS + - KS ON DOD FIR - + RFRN VOG OD/ D5/SRI N 1 D4/SRI N 2 D3/SRI D IN D2/SRI OK D1 D0 RX/ X X/K X DIGI INRF ND OK GNRION KS/X KS/X 0-5 D0-D10 ON D OGI ON OU FIR ON ROM 48 x 10 RX ON D X ON OU VDD VSS VIS X UDIO IN K X UDIO OU RX UDIO IN DOD OMROR RF. DOD OMROR IN 300z UDIO FIR + - RX UDIO OU RX ON DOD he MX465 SS ncoder/decoder is a low voltage, MOS device that meets I/I-603 Standards. he MX465 will encode and decode the tones 159.8z, 183.5z, 189.9z, 196.6z, 199.5z, 206.5z, 229.1z, and 254.1z in addition to the 39 standard SS tones, for a total of 47 SS tones + Notone. With the incorporation of the on-chip X and RX speech filter, the MX465 enhances voice/tone multiplexing by attenuating X and RX speech 36d at frequencies below 250z while passing signals > 300z with only 1d of ripple. his not only minimizes SS talk-off in the X mode but also improves um and Noise performance in the RX mode. vailable in the following package styles: 24-pin SSO (MX465N), 24-pin SSO (MX465DS), 24-pin SOI (MX465DW), 24-pin (MX465), 24-pin DI (MX465), and 24-pin DI (MX465) the MX465 requires a single 3.3V to 5.0V supply and a 4Mz clock or crystal.

2 ow Voltage SS ncoder/decoder 2 MX465 Section ONNS age 1. lock Diagram Signal ist xternal omponents General Description Description I/O onditions Filter Response Serial and arallel Mode iming SS rogramming erformance Specification lectrical erformance bsolute Maximum Ratings Operating imits ackaging MX-OM, Inc. Reserves the right to change specifications at any time and without notice

3 ow Voltage SS ncoder/decoder 3 MX465 1 lock Diagram ON IN ON IN FIR f ON KS + - KS ON DOD FIR - + RFRN VOG OD/ D5/SRI N 1 D4/SRI N 2 D3/SRI D IN D2/SRI OK D1 D0 RX/ X X/K X DIGI INRF ND OK GNRION KS/X KS/X 0-5 D0-D10 ON D OGI ON OU FIR ON ROM 48 x 10 RX ON D X ON OU V V V DD SS IS X UDIO IN K X UDIO OU RX UDIO IN 300z UDIO FIR RX UDIO OU DOD OMROR RF. DOD OMROR IN + - RX ON DOD Figure 1 : lock Diagram

4 ow Voltage SS ncoder/decoder 4 MX465 2 Signal ist in No. Signal ype Description 1 V DD power ositive supply. his pin should be bypassed to V SS by a capacitor mounted close to the device pins. 2 X/OK input Input to the on-chip inverter used with a 4 Mz Xtal or external clock source. 3 X output Output of the on-chip inverter (clock output). 4 OD / input ontrols 8 on-chip latches. It is used to latch RX / X,, and D0-D5. logic 1 applied to this input places the 8 latches in the transparent mode. logic 0 applied to this input places the 8 latches in the latched mode. In arallel Mode, data is loaded and latched by a logic 1-0 transition (see Figure 4). In Serial Mode, data is loaded and latched by a strobe pulse on this pin (see Figure 5). Internally pulled to V DD 5 D5 / SRI N 1 input Data input D5 (arallel Mode). logic 1 applied to this input together with a logic 0 applied to D4/SRI N 2 will place the device in Serial Mode (see Figure 5). Internally pulled to V DD. 6 D4 / SRI N 2 input Data input D4 (arallel Mode). logic 0 applied to this input together with a logic 1 applied to D5 / SRI N 1 will place the device in Serial Mode (see Figure 5). Internally pulled to V DD. 7 D3 / SRI D IN input Data input D3 (arallel Mode). In Serial Mode this pin becomes the serial data input for D5-D0, RX/ X and (see Figure 5). D5 is clocked first and last. Internally pulled to V DD. 8 D2 / SRI OK input Data input D2 (arallel Mode). In Serial Mode this pin becomes the SRI OK input. Data is clocked on the positive going edge (see Figure 5). Internally pulled to V DD. 9 D1 input Data input D1 (arallel Mode). Internally pulled to V DD. 10 D0 input Data input D0 (arallel Mode). Internally pulled to V DD. 11 V SS power Negative supply. 12 DOD OMROR RF. input Internally biased to V DD /3 or 2 V DD /3 via 1M resistors depending on the logic state of the RX ON DOD pin. RX ON DOD = 1 will bias this input 2 V DD /3; a logic 0 will bias this input V DD /3. his input provides the DOD OMROR RFRN voltage, and the switching of bias voltages provides hysteresis to reduce chatter under marginal conditions. 13 RX ON DOD output Gated output of the decode comparator. his output is used to gate the RX udio path. logic 0 on this pin indicates a successful decode and the DOD OMROR IN pin is more positive than the DOD OMROR RF. input (see able 3). 14 DOD OMROR IN input Inverting input of the DOD OMROR. his pin is normally connected to the integrated output of the RX ON D line. 15 RX ON D output In RX mode this output will go to logic 1 during a successful decode. It must be externally integrated to control response and deresponse times (see able 3).

5 ow Voltage SS ncoder/decoder 5 MX465 in No. Signal ype Description 16 X ON OU output he SS sinewave output appears on this pin under control of the RX/ X pin. When not transmitting a tone, X ON OU may be biased to V DD /2. (see able 3). 17 RX/ X input RX or X modes selected in arallel Mode (see Figure 4). In Serial Mode this function is serially loaded. his pin is internally pulled to V DD via a 1M resistor. 18 input In RX mode this pin operates as a ush o isten function by enabling the RX audio path, thus overriding the tone squelch function (arallel Mode). In Serial Mode this function is loaded serially. Internal pull-up to V DD 19 RX UDIO OU output igh pass filtered RX UDIO OU. his pin outputs audio when RX ON DOD = logic 0, = logic 1, or when Notone is programmed (see able 4). In X mode this pin is biased to V DD /2. 20 X UDIO OU output igh pass filtered X UDIO OU pin. In X mode this pin outputs audio present at the X UDIO IN pin. In RX mode this pin is biased to V DD /2 21 V IS output Output of an internally generated V DD /2 bias level that would normally be externally bypassed to V SS via capacitor X UDIO IN input In X mode X UDIO IN may be prefiltered, using the X udio path, thus helping to avoid talk-off due to intermodulation of speech frequencies with the transmitted SS tone. Internally biased to V DD /2. 23 RX UDIO IN input Input to the audio high pass filter in RX mode. Internally biased to V DD /2. 24 ON INU input Input to the SS tone detector. Internally biased to V DD /2. able 1: Signal ist

6 ow Voltage SS ncoder/decoder 6 MX465 3 xternal omponents V DD V DD X/K X1 R1 X OD / D5/SRI N 1 D4/SRI N 2 D3/SRI D IN D2/SRI OK D1 D0 V SS DOD OMROR RF MX ON IN 4 RX UDIO IN 5 X UDIO IN 10 V IS 6 X UDIO OU 11 RX UDIO OU 7 RX / X ON OU 8 RX ON D DOD OMROR IN RX ON DOD R3 R2 D1 9 Figure 2 : Recommended xternal omponents for ypical pplication R1 Note 1 1.0M 10% F 20% R2 560k 10% 7 Note 2 0.1F 20% R3 820k 10% 8 Note 2 0.1F 20% 1 0.1F 20% 9 Note 2 0.1F 20% 2 Note 1 18pF 20% 10 Note 2 0.1F 20% 3 Note 1 33pF 20% 11 Note 2 0.1F 20% 4 Note 2 0.1F 20% D1 small signal 5 Note 2 0.1F 20% X1 Note 1 4Mz 100ppm max. able 2: xternal omponents xternal omponents Notes: 1. he values specified for R1, 2, and 3 have been found to be satisfactory when used with a crystal (X1) whose equivalent series resistance is For best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of V DD, peak to peak. uning fork crystals generally cannot meet this requirement. o obtain crystal oscillator design assistance, consult your crystal manufacturer. 2. he 0.1F value for the D locking capacitors, 4, 5, 7, 8, 9, 10, and 11 is not a requirement. For the capacitors 4, 5, and 10, the input impedance is internal to the device and specified typical as 550k. For the remaining capacitors external circuits will be important in determining the input impedance.

7 ow Voltage SS ncoder/decoder 7 MX465 4 General Description 4.1 Description Voice on shared radio channels are multiplexed with a subaudible SS (ontinuous one ontrolled Subaudible Squelch) tone as a means of directing messages among user groups sharing the same RF frequencies. SS modulates the transmitter with a discrete tone, from 39 standard SS tones in the range (67.0z to 250.0z) according to I/I-603. here are an additional eight SS tones not specified in I/I-603 that the MX465 will encode and decode. hey are : 159.8z, 183.5z, 189.9z, 196.6z, 199.5z, 206.5z, 229.1z, and 254.1z, for a total of 47 SS tones plus Notone. he MX465 also incorporates X/RX on chip speech filters. In early SS designs, X speech was not filtered from the SS tone, rather the filtering was dependent upon the host transmitter s pre-emphasis network. t only 6d/octave, the attenuation of speech components at higher SS tones was only a few d which resulted in talk-off (low frequency voice components unsquelching the receiver audio). 4.2 I/O onditions Input ins ondition D0-D5 one No one one one one No one RX / X X 0 1 X X Decode omparator In X X X Output ins ondition RX ON D X RX ON DOD Result / Function one ransmitter nabled es No (ias) No (ias) No (ias) No (ias) No (ias) X udio ath nabled es es No No No No one Decode nabled No No es es es es RX udio ath nabled No (ias) No (ias) No (ias) es es es Notes Notes: 1. Normal tone transmit condition. 2. Notone programmed in X mode, tone transmit output set to V DD /2. X audio path enabled. 3. Normal decode standby. 4. Normal decode standby with used to enable audio. 5. Normal decode of correct SS tone condition, has no effect. 6. Notone programmed in RX mode, tone transmit output (ias). RX audio path enabled. 7. X = don t care able 3: ombinations of Input / Output conditions

8 ow Voltage SS ncoder/decoder 8 MX Filter Response Gain (d) SS Frequencies Voiceband Frequencies Frequency (z) 4.4 Serial and arallel Mode iming Figure 3 : Voiceband Filter Response D0-D5 RX/X, t S OD/ t Figure 4 : arallel Mode

9 ow Voltage SS ncoder/decoder 9 MX465 SRI N D5 D4 D (Note) SRI OK t 1 D D5 D D4 D3 RX/X t SS t t t 2 D3 D2 OD/ OD D D t / D D DON' R DON' R - 1MΩ U U DON' R - 1MΩ U U D1 D0 Note : Serial bit 1 through bit 8 = D5, D4, D3, D2, D1, D0, RX/X and respectively. oad bit 1 first, bit 8 last Figure 5 : Serial Mode

10 ow Voltage SS ncoder/decoder 10 MX SS rogramming Nominal Frequency (z) one MX465 Frequency (z) rogramming Inputs f0 (%) D5 D4 D3 D2 D1 D0 ex F F F D D D

11 ow Voltage SS ncoder/decoder 11 MX465 Nominal Frequency (z) one MX465 Frequency (z) rogramming Inputs f0 (%) D5 D4 D3 D2 D1 D0 ex Notone N/ Serial input mode N/ 1 0 Data lock X X 2X Not specified in the I/I tone set able 4: SS ones 5 erformance Specification 5.1 lectrical erformance bsolute Maximum Ratings xceeding these maximum ratings can result in damage to the device. Operation of the device outside the operating limits is not implied. General Min. Max. Units Supply (V DD - V SS ) V Voltage on any pin to V SS -0.3 V DD V urrent V DD m V SS m any other pins m N / DW / / DI ackage otal llowable ower Dissipation at M = mw Derating above mw/ above 25 Storage emperature Operating temperature DS ackage otal llowable ower Dissipation at M = mw Derating above 25 9 mw/ above 25 Storage emperature Operating temperature

12 ow Voltage SS ncoder/decoder 12 MX Operating imits orrect operation of the device outside these limits is not implied. Min. Max. Units Supply (V DD -V SS ) V Xtal Frequency Mz Operating emperature Operating haracteristics For the following conditions unless otherwise specified: V DD = 3.3V / 5.0V at M = 25, V SS = 0V, Xtal Frequency = 4.0 Mz, 100ppm max. (Over the life of the X the operating range may vary from 100ppm up to 1000ppm) 0d ref. = 750mV RMS (proportional to V DD ; see note 17) omposite Signal: 1kz test tone = 300mV RMS, f0 SS tone = 30 mv RMS, 75mV RMS Noise (band limited to 6kz Gaussian) Notes Min. yp. Max. Units Static Values Supply voltage / V Supply current V DD = 5.0V m V DD = 3.3V m nalog input impedance k nalog output impedance Digital Input impedance 1, k Input logic %V DD V Input logic %V DD V Output ogic 1 source = 0.1m 2 80%V DD V Output ogic 0 sink = 0.1m 2 20%V DD V Dynamic Values Speech filter otal harmonic distortion 5,8, % Output noise level (input short circuit, audio switch enabled) 8, mv RMS Sinad 8, d Spurious emissions d utoff frequency 300 z andpass ripple d Stopband attenuation <250z 7,8, d assband gain 1kz d X/RX isolation 5 60 d

13 ow Voltage SS ncoder/decoder 13 MX465 ncoder Notes Min. yp. Max. Units one output level d one Frequency ccuracy (f error) %f 0 Risetime to 90% nominal output f 0 >100z 4, ms f 0 <100z 4, ms otal armonic Distortion % Decoder ure tone decode threshold mv RMS omposite signal decode threshold 3 30 mv RMS Decode input signal level d ure tone decode response time 13, ms ure tone decode deresponse time 13, ms Decode response time 3,6, ms Deresponse time 3, ms Decode selectivity: Upper decode band edge 3,11,19, f f f 0+1 z ower decode band edge 3,11,19, f f f 0 z Serial / arallel Inputs arallel Set Up ime (t S ) 400 ns oad / atch ulse Width (t ) 400 ns Serial lock ulse Width (t ) 400 ns Serial Data Set-Up ime (t SS ) 400 ns Serial Data old ime (t ) 400 ns Serial nable ime (t 1 ) 400 ns Serial oad / atch Set-Up ime (t 2 ) 400 ns Serial lock Frequency 1 Mz Operating haracteristics Notes: 1. Refers to RX/X,, Decode omparator Input, D0-D5. 2. ll logic outputs. 3. omposite signal test condition. 4. ny programming tone and R = 10k, = 15pF. 5. With an input level of 6. f 0 >100z (for 100 z> f 0 >67z: t=100/ f 0 z x 250ms) 7. See Figure Measured in a 30kz bandwidth. 9. With an input level of 10. er I/I er I/I-603, device will not decode adjacent I/I-603 ones. 12. one output level is proportional to V DD. 13. f 0 -20d. 14. ypically 12.5 one ycles + 40ms. 15. ypically 7 one ycles + 90ms.

14 ow Voltage SS ncoder/decoder 14 MX Max composite signal is 3.5d with: Noise (band limited 6kz Gaussian) = -12d ref to 1kz test tone f 0 SS tone = -20d ref to 1kz test tone 17. For maximum dynamic range, set audio level to 0d, V DD x150mv RMS, using minimum V DD under which system is intended to work. (e.g. for a 2.7V system, use 0d equal to 405mV RMS ). 18. y characterization only. 19. atch sampled only 20. For example, if: f 0 = 100.0z (f 0-1 = 97.4z f 0+1 = 103.5z) 5.2 ackaging Decode Selectivity Min yp Max Unit Upper Decode and dge z ower Decode and dge z ackage olerances DIM. MIN.. MX. RNIV IN OION MRKING IN (7.70) (7.90) (4.30) (4.50) (1.20) (6.30) (6.50) (0.05) (0.15) (0.17) (0.30) (0.50) (0.75) (0.65) (0.08) (0.20) 0 8 NO : ll dimensions in inches (mm.) ngles are in degrees Figure 6: 24-pin SSO Mechanical Outline: Order as part no. MX465N IN 1 X Z DIM. X Z ackage olerances MIN.. MX (8.07) (8.33) (5.20) (5.39) (1.67) (2.00) (7.65) (7.90) (0.05) (0.21) (0.25) (0.38) (0.55) (0.95) (0.65) (0.13) (0.22) NO : ll dimensions in inches (mm.) ngles are in degrees Figure 7: 24-pin-SSO Mechanical Outline: Order as part no. MX465DS

15 ow Voltage SS ncoder/decoder 15 MX465 ackage olerances RNIV IN OION MRKING IN 1 K W X Z DIM. K W X Z MIN.. MX (15.16) (15.57) (7.26) (7.59) (2.36) (2.67) (9.90) (10.64) (0.08) (0.51) (0.33) (0.51) (0.91) (1.17) (0.41) (1.27) (1.27) (0.23) (0.32) NO : ll dimensions in inches (mm.) ngles are in degrees Figure 8: 24-pin SOI Mechanical Outline: Order as part no. MX465DW D IN 1 G W K W DIM. D F G K W ackage olerances MIN (9.61) (9.61) (3.25) (10.60) (10.60) (0.45) (1.19) (1.24) (0.152) (6.35) (6.35) (0.58) 45 6 MX (10.40) (10.40) (3.70) (11.05) (11.05) (0.55) (1.22) (1.30) (0.22) F NO : ll dimensions in inches (mm.) ngles are in degrees Figure 9: 24-pin Mechanical Outline: Order as part no. MX465

16 ow Voltage SS ncoder/decoder 16 MX465 ackage olerances DIM. MIN.. MX. IN1 K 1 F K1 1 1 F 1 K K (31.50) (13.06) (4.19) (15.23) (2.92) 0.10 (2.54) (32.00) (14.79) (5.84) (17.00) (15.09) (15.61) (27.94) 0.02 (0.51) (0.46) (1.39) (1.27) (1.88) (0.239) (2.03) (2.03) (5.08) (0.269) NO : ll dimensions in inches (mm.) ngles are in degrees Figure 10: 24-pin-DI Mechanical Outline: Order as part no. MX465 ackage olerances IN1 K 1 1 DIM. 1 MIN (30.48) (12.70) (3.84) (15.24) MX (32.26) (14.04) (5.59) (17.02) (14.99) (15.88) (0.38) (1.14) (0.38) (0.58) (1.02) (1.65) K (1.67) (1.88) (3.07) (4.05) (2.54) (0.20) (0.38) 7 NO : ll dimensions in inches (mm.) ngles are in degrees Figure 11: 24-pin DI Mechanical Outline: Order as part no. MX465

17 M Microcircuits OMMUNIION SMIONDUORS M roduct Data In the process of creating a more global image, the three standard product semiconductor companies of M Microsystems lc (onsumer Microcircuits imited (UK), MX-OM, Inc (US) and M Microcircuits (Singapore) te td) have undergone name changes and, whilst maintaining their separate new names (M Microcircuits (UK) td, M Microcircuits (US) Inc and M Microcircuits (Singapore) te td), now operate under the single title M Microcircuits. hese companies are all 100% owned operating companies of the M Microsystems lc Group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. M Microcircuits roduct refix odes Until the latter part of 1996, the differentiator between products manufactured and sold from MXOM, Inc. and onsumer Microcircuits imited were denoted by the prefixes MX and FX respectively. hese products use the same silicon etc. and today still carry the same prefixes. In the latter part of 1996, both companies adopted the common prefix: MX. his notification is relevant product information to which it is attached. M Microcircuits (US) [formerly MX-OM, Inc.] roduct extual Marking On M Microcircuits (US) products, the MX-OM textual logo is being replaced by a M textual logo. ompany contact information is as below: M Microcircuits (UK)td OMMUNIION SMIONDUORS Oval ark, angford, Maldon, ssex, M9 6WG, ngland el: +44 (0) Fax: +44 (0) uk.sales@cmlmicro.com M Microcircuits (US) Inc. OMMUNIION SMIONDUORS 4800 ethania Station Road, Winston-Salem, N 27105, US el: , Fax: us.sales@cmlmicro.com M Microcircuits (Singapore)tetd OMMUNIION SMIONDUORS No 2 Kallang udding Road, 09-05/ 06 Mactech Industrial uilding, Singapore el: Fax: sg.sales@cmlmicro.com D/M (D)/2 May 2002