Multistate Logic Inverter Based on Black Phosphorus/ SnSeS Heterostructure

Transcription

1 COMMUNICATION van der Waals Heterostructures Multistate Logic Inverter Based on Black Phosphorus/ SnSeS Heterostructure Wenxing Lv, Xia Fu, Xin Luo, Weiming Lv, Jialin Cai, Baoshun Zhang, Zhongming Wei,* Zhongyuan Liu,* and Zhongming Zeng* van der Waals (vdw) heterostructures have attracted intensive attention due to their great potential in future functional electronic and optoelectronic devices. Here, a systematic electrical transport investigation on black phosphorus (BP)/SnSeS heterostructures is presented. The BP/SnSeS heterostructure shows diverse diode functional features by modulating BP channel length and back-gate modulation, which is closely associated with the carrier tunneling at the heterojunction interface. The performances of the logic inverter based on the BP/SnSeS heterojunction are effectively enhanced by increasing the source voltage, and a middle state is observed with the increase of BP channel length. These findings could stimulate further research activities on vdw heterostructures for multiple functionality devices. van der Waals (vdws) heterostructure based on 2D layered materials offers new platform for both fundamental science and versatile functional devices by combining the distinctive properties of each individual materials into one composite system. [1 7] W. X. Lv, X. Luo, Dr. W. M. Lv, J. L. Cai, Dr. B. S. Zhang, Dr. Z. M. Zeng Key Laboratory of Nanodevices and Applications Suzhou Institute of Nano-Tech and Nano-Bionics CAS Suzhou , China zmzeng2012@sinano.ac.cn W. X. Lv, J. L. Cai School of Nano Technology and Nano Bionics University of Science and Technology of China Hefei , China Dr. X. Fu Patent Examination Cooperation Jiangsu Center of the Patent Office (SIPO) Suzhou , China Dr. Z. M. Wei State Key Laboratory of Superlattices and Microstructures Institute of Semiconductors Chinese Academy of Sciences & College of Materials Science and Opto-Electronic Technology University of Chinese Academy of Sciences Beijing , China zmwei@semi.ac.cn Prof. Z. Y. Liu State Key Laboratory of Metastable Materials Science and Technology Yanshan University Qinhuangdao , China liuzy0319@yahoo.com The ORCID identification number(s) for the author(s) of this article can be found under DOI: /aelm Graphene, transition metal-dichalcogenides (TMDs), and black phosphorus (BP) are widely exploited as building blocks for such vdws heterostructure due to their unique electrical and optical properties. [8 13] Among these 2D materials, BP has attracted extensive attention because of its high carrier mobility (up to 1000 cm 2 V 1 s 1 at room temperature), moderate tunable direct bandgap on thickness (from 0.3 ev for bulk to 2.0 ev for monolayer), and intrinsic anisotropy arising from the puckered structure. [14 17] In the past years, a host of BP-based vdws heterostructures such as graphene/ BP, TMDs/BP, and h-bn/bp architecture, have been fabricated to explore their electronic and photoelectric properties, which have shown promising applications for fieldeffect transistors (FETs), [18 20] photodetectors, [8,21,22] flexible devices, [23] memory device, [24] logic circuits, [25] and so on. In the most studied BP/MoS 2 heterostructure, [11,20,25] diverse diode characteristics, including back forward rectifying diode, Zener diode, and forward rectifying diode, have been obtained by BP thickness modulation. [20] A tunable multivalued logic performance was also realized in such heterostructure, providing a step forward toward the future logic applications. [25] Recently, tin-based dichalcogenide SnSe x S 1 x, [26 32] a layered semiconductor family with environmental friendly and low cost characteristics, has been explored for nanoelectronic applications. In addition, the wide bandgap ranging from 1 to 2.1 ev opens the possibility of developing versatile devices by band engineering. In this work, we present a realization of BP/SnSeS heterostructure and explore its carrier transport and logic characteristics for the first time. The heterostructure based on Te-doped BP exhibits high carrier mobility and an exceptional ambient stability. [33] Diverse diode characteristics are observed with the modulation of band alignment at BP/SnSeS interface. Furthermore, we demonstrated a multivalued logic state by varying BP length, suggesting that BP/SnSeS heterostructure has promising application in low-power multivalued logic circuits. The schematic of the proposed BP/SnSeS heterostructure is shown in Figure 1a. Both BP and SnSeS flakes were mechanically exfoliated from their bulk crystals. Using a dry transfer technique, the BP flake was first transferred onto the HfO 2 (30 nm)/ Si substrate with prepared electrical pads, and then exfoliated SnSeS flake was artificially stacked atop the BP flake forming BP/SnSeS heterostructure. After that, multiple metal electrodes were fabricated on the top of BP and SnSeS regions by (1 of 7)

2 Figure 1. a) Schematic of BP/SnSeS heterostructure. b) Optical and c) AFM images of BP/SnSeS device. d) Raman spectra of the sample at different positions. standard electron beam lithography and subsequent deposition of 10/50 nm Ni/Au. The electrical transport characteristics with various channel lengths can be studied in one heterostructure by selecting different source and drain electrodes. Figure 1b,c display optical image and AFM image of one representative BP/ SnSeS device, in which the thickness is 7.5 nm for BP and 14 nm for SnSeS. Figure 1d depicts the Raman spectra of the corresponding device. When Raman spectra are taken from the pristine BP region only, the BP A g1 (438.5 cm 1 ), B 2g (361.4 cm 1 ), and A 2 g (465.8 cm 1 ) modes are present, which is consistent with previous studies. [9,17,33,34] While for the pristine SnSeS region, the SnSeS A 1g mode ( 205 and 302 cm 1 ) and another weak broad peak centered at 134 cm 1 are observed. [35] These peaks were all contained in the spectra of BP/SnSeS overlapped region, indicating the successful formation of BP/SnSeS heterostructure. The transport properties of field-effect transistors (FETs) based on individual BP and SnSeS materials are measured first. Figure 2a shows linear output characteristics of the BP or SnSeS FETs when various back-gate voltages are applied at room temperature, indicating good Ohmic contact between BP (SnSeS) and Ni/Au electrodes. Figure 2b displays the corresponding transfer characteristics of the devices, revealing an am-bipolar behavior (p-type dominated) and n-type characteristic for BP and SnSeS, respectively. By using the peak transconductance from the transfer curves, the charge carrier mobility for BP and SnSeS channel can be estimated by µ d Te BP( µ SnSeS) = Ids L (0.4)cm V s dv g WC i V =, where ds L and W are the channel length and width, respectively, and εε 0 Ci = is F cm 2 for 30 nm thick HfO d 2 layer. [36] These observed values of mobility are in the same level with the previously reported devices. [4,18,19,33] Figure 2c shows the current voltage (I ds V ds ) characteristics of BP/SnSeS heterostructure as a function of SnSeS channel length without a back-gate bias, where the BP channel is fixed at 15.5 µm. In these measurements, the V ds is always applied to BP with SnSeS flake grounded. The current shows a negligible difference except the slight increase in the forward direction. The transfer characteristics demonstrated a similar decrease in current with increasing SnSeS channel length (Figure 2d), which can be attributed to the enhancement of resistance arising from the pristine SnSeS region. However, the reverse current increases rapidly when the BP channel length gradually decreases (Figure 2e). The transfer characteristics in Figure 2f also show obvious differences among various BP channel. The impacts of BP channel on electrical properties of BP/ SnSeS heterostructure were investigated based on the three representative cases. As shown in Figure 3a, the device composed of 15.5 µm BP channel shows a normal forward diode characteristic, that is, current in forward V ds is much larger than that in reverse V ds. When the BP channel decreases to 2.5 µm, the forward current displays a similar trend to the case of 15.5 µm BP channel. The current increases when V ds is applied. Simultaneously, the reverse current keeps constant at a small V ds and then increases dramatically at a critical reverse voltage of about 0.1 V (Figure 3c), which matches the performance of Zener diode. [20] Here, the case with 6.5 µm BP channel is considered to be a middle state transformed from forward diode to Zener (2 of 7)

3 Figure 2. The output characteristics of pristine a) BP and SnSeS flakes, the corresponding transfer characteristics of pristine b) BP and SnSeS flakes. c) The current voltage curves and d) transfer characteristics with various SnSeS channel length. e) The current voltage curves and f) transfer characteristics with various BP channel length. diode (see Figure 3b). The inset of Figure 3a c shows the corresponding diagrams for each diode. Generally, the forward V ds could shift down the band of BP and thus lower the interface barrier height. [20] On the contrary, the reverse V ds would shift up the BP band and exaggerate the interlayer potential barrier. The effective reverse V ds on BP/SnSeS heterostructure becomes smaller due to the larger resistance of individual BP channel with longer channel length. In this case, the interface barrier height would be gradually reduced by decreasing effective reverse V ds, leading to the reverse conduction dominated by minority carrier drift for 15.5 µm BP channel (the inset of Figure 3a). Electrons in BP conduction band and holes in SnSeS valence band are the minority carrier. With shorter BP channel, the band-to-band tunneling would only take place at a small reverse V ds due to a higher interlayer barrier (the inset of Figure 3b,c), which is supposed to be the origin of Zener diode performance. [20] To get a deeper insight of the tunneling mechanism at the interface of BP/SnSeS heterostructure, we plotted the current voltage characteristic of another case, where the channel length of BP and SnSeS are 4.5 and 2.5 µm, respectively, in Figure 4a. Similar to the middle state in Figure 3b, a weak Zener diode rectifying behavior is present. As shown in Figure 4b, two distinct linear regimes, which are represented by different slopes (dashed lines) and one transition point (V tr = V), can be seen in the forward V ds region. The current in the regime I is directly proportional to the applied voltage, which implies a direct tunneling (DT) via the thermionic emission. [37,38] The current shows a more rapid increasing trend in the regime II because the interface barrier at the heterojunction becomes more triangular and narrower at higher forward bias, consequently giving rise to the Fowler Nordheim tunneling (FNT). [37,39] Figure 4c shows the transition from DT to FNT. Figure 3. The diverse diode characteristics of BP/SnSeS heterostructure with different BP channel length of a) 15.5 µm, b) 6.5 µm, and c) 2.5 µm. Inset: the corresponding band alignments for BP/SnSeS diodes of diverse functions, where the source drain voltage applied to BP is negative, and carrier transport in the reverse direction of BP/SnSeS diodes was studied (3 of 7)

4 Figure 4. Diode behavior of the heterostructure. Current voltage of the BP/SnSeS heterostructure in a) linear scale, b) double-log scale, and c) Fowler Nordheim plots. d) Band alignments of the heterostructure under different source drain voltages. The DT current at low voltage and the FNT current at high voltage are expressed by [39] I I DT FNT * 4πd 2m Φ Vexp (1) h * 3 2 8πd 2m Φ V exp (2) 3ehV where d, m*, Ф, and h are the tunneling thickness, effective electron mass, tunneling barrier, and Plank constant, respectively. According to Equations (1) and (2), the plot of ln(i/v 2 ) versus 1/V should show linearity with a negative slope for FNT and logarithm regime for DT, as demonstrated in Figure 4c. The threshold voltage of FNT, V th = 1/3.5 V, corresponds to Ф/e, indicating the tunneling barrier Ф is about ev. The tunneling barrier is established from the BP side (see Figure 4d). The band diagram under reverse bias is similar to the inset of Figure 3b,c, where the reverse current is dominated by the Zener tunneling. [20] For better understanding the effects of the back-gate bias on the tunneling at the interface of BP/SnSeS heterostructure, the log-current scale output curves of the device discussed above are shown in Figure 5a. It is noted that diverse functional diodes can be also achieved through the gate bias modulation: 1) 5 V V g 3 V, a weak back forward diode; 2) 3 V < V g 0 V, a conventional forward diode; 3) 0 V < V g 5 V, a Zener diode. Similar phenomena that multifunctional device modulated by gate bias were also reported in BP/MoS 2 heterojunction. [20] Here, a crossover of the output curves is observed in both reverse and forward direction (Figure 5a), which is different from previous work. [20] This behavior could be associated with the different charge tunneling mechanism at the interface of BP/ SnSeS heterostructure. To elucidate the tunneling at the interface with various back-gate bias, we plotted the output curves in a ln(i/v 2 ) versus 1/V scale as shown in Figure 5b. It is evident that there is only DT in the range of V g 3 V, and the FNT current gradually contributes more to the forward current with the increase of V g. This transition from DT to FNT shows a deep insight into the carrier transport at the interface of BP/SnSeS heterostructure. We note that in BP/SnSeS heterostructure, the SnSeS layer is perpendicularly stacked on the top of BP. As such, the applied negative back-gate bias can rise the band of BP up and lower the band of SnSeS, and vice versa. Considering the conduction band minimum (CBM) of SnSeS lied slightly above the valence band maximum (VBM) of BP at the equilibrium state, [33,35] the CBM of SnSeS may locate far below the VBM of BP (similar to the inset of Figure 3c) under the negative back-gate bias. Consequently, this leads to the only DT despite at high forward V ds and higher forward current at small forward V ds. With increasing V g, the interface barrier height would be reduced to allow the electrons flowing into the BP conduction band via the FN tunneling at high forward bias, resulting in larger forward current, as shown in the right region after the crossover point in Figure 5a. The threshold voltage V th as a function of gate bias V g is summarized in Figure 5c. A monotonous decreasing trend of V th is observed until the V g raises up to 3 V, then V th saturates to 0.24 V when V g is over 3 V. The decrease of V th is due to the reduction of barrier height at BP/SnSeS interface. [40] Based on this analysis, we estimate the back-gate bias tunability on interlayer barrier height to be 0.02 ev V 1, as shown in the inset of Figure 5c. The transfer characteristics at different drain source bias are shown in Figure 5d. In region I (V g < 2 V), the current is dominant by both nonoverlapped SnSeS channel region and SnSeS region in the heterojunction. [25] In region II (0 V < V g < 2 V), the drain currents drop fast. This is because the heterostructure is fully turned on and the drain-source current is dominated by the nonoverlapped BP and SnSeS transistor, where current in depleted BP channel decreases more quickly than it increases in SnSeS. [25] Owing to am-bipolar properties of BP, the current in region III results from both BP and SnSeS channels. [25] Under forward bias, the band alignment of the SnSeS raises up and the interface barrier for electron in SnSeS reduces. Thus, the current increases faster with larger V ds, as shown in region I. Last, the logic properties of BP/SnSeS heterostructure were investigated. A schematic of the BP/SnSeS heterostructure-based logic inverter is illustrated in Figure 6a. V in, the input voltage, is applied through the back gate. An electrode (4 of 7)

5 Figure 5. Gate-modulated transfer characteristics through of BP/SnSeS heterostructure. a) Log-current scale I V curves and b) Fowler Nordheim plots versus back-gate bias. c) Threshold voltage V th abstracted from (b) with back-gate biases. The inset shows the calculated variation of Schottky barrier with back-gate biases from (c). d) Transfer characteristics of the heterostructure with different source drain voltages. deposited on the non-overlapped BP channel is employed as V out terminal (V out is the output voltage). V dd and GND were deposited on the BP and SnSeS channel, respectively. The input voltage V in can adjust the carrier density of the whole channel and generate the invert signal by combining with V out. Figure 6b illustrates the output voltage as function of input voltage at different V dd (the V dd increases from 0.1 V to 1 V with a step of 0.1 V). Taking the case of 1 V as an example, the output voltage shows a high logic value of 1 at V in < 1 V and a low logic value of 0 at V in > 2 V. At logic 1, the BP provides a low-resistance path between V dd and V out for the supply voltage. At logic 0, the resistance of heterojunction is small enough that the logic low level is equal to half level of logic 1 when the heterojunction is turned on. [25] By increasing the channel length of BP, a unique middle logic state appears at around V in = 0 V and gradually becomes distinct under longer BP channel length (Figure 6c). This is because by increasing the BP channel length, the transfer characteristics curve of the BP transistor can be modulated and a parallel region of two transistors (individual BP transistor and BP/SnSeS heterojunction transistor) in the transfer characteristics exists at proper BP channel length. In this parallel region, the resistance ratio of two transistors is constant, so a middle logic state occurs in the V out V in characteristics. [12] Figure 6d shows the corresponding output gain dependence of V in. The output gain was defined as g = dv out /dv in. As seen from Figure 6d, it is clear that the second peak at around 1 V gradually becomes distinct with the increase of BP channel, which corresponds to the middle logic state. However, when we fix the length of BP channel and modulate the pull-down transistor by increasing the length of SnSeS channel, there is only inconspicuous change of output voltage of logic 1 and no obvious middle logic state was found. This is due to the increased resistance of SnSeS in such case, leading to the lack of parallel region between the transfer curves of individual BP transistor and BP/SnSeS heterojunction transistor. The output voltage of logic 0 decreases with positive V in in whole. Overall, it can be seen that by changing channel length, the logic performance of BP/SnSeS heterostructure can be obviously modulated, which shows potential for future multivalued logic application. We have investigated the transport properties of the BP/ SnSeS heterostructure. The carrier transfer strongly depends on the length of both BP and SnSeS channel, drain bias and gate bias. Multifunctional diode is achieved by reducing the channel length of BP, which results from the increase of effective drain bias voltage. Moreover, we demonstrate the logic performance at different V dd and channel length. A unique middle state at around V g = 0 V is observed when L BP > 4.5 µm at V dd = 1 V (5 of 7)

6 Figure 6. Logic performance of BP/SnSeS heterostructure diode. a) Schematic view of the heterostructure-based inverter. b) Inverter formed by a BP field effect transistor (FET) and lateral HJFET with different source drain voltages, V dd varies from 0.1 to 1 V. c) Inverter with various BP channel length with a forward bias of 1 V, the channel length of SnSeS was fixed at 2.5 µm. d) The output gain dependence of V in with different BP channel length. e) Inverter with various SnSeS channel length with a bias of 1 V, the channel length of BP was fixed at 15.5 µm. Our work provides an effective way for the designing multifunctional electronics based on 2D heterostructure. Conflict of Interest The authors declare no conflict of interest. Experimental Section Device Fabrication: The BP/SnSeS heterostructure was constructed using a common dry transferred technique. First, thin BP flakes were mechanically exfoliated from their bulk crystals via standard scotch tape to the polydimethylsiloxane film and then transferred onto the HfO 2 (30 nm)/si substrate with prepared electrical pads. Then, few-layer SnSeS were exfoliated onto the polydimethylsiloxane film and artificially stacked atop the BP flake under the optical microscope assisted by an aligned transfer system. Finally, multiple metal electrodes were patterned by standard electron beam lithography and deposited with metal Ni/Au (10/50 nm) by electron-beam evaporation to fabricated source and drain electrodes. Device Characterization: Morphology of the BP/SnSeS vdw heterostructure was investigated by an optical microscope (BX51, OLMPUS). The thickness was conducted by an atomic force microscope (Dimension 3100, Veeco). Raman spectra were taken from pristine BP and SnSeS, overlapped BP/SnSeS region, respectively, on a Horriba-JY LABRAM HR Raman spectrometer with 532 nm laser. All electrical measurements were carried out with two high-precision digital source meters (Keithley 2612B and 2400). Acknowledgements W.X.L. and X.F. contributed equally to this work. This work was supported by the National Natural Science Foundation of China (Grant No , , ). Keywords 2D heterostructures, black phosphorus, diverse functional transistors, multivalued inverters, tin dichalcogenides (SnSeS) Received: July 2, 2018 Revised: August 19, 2018 Published online: September 30, 2018 [1] X. Zhang, H. Cheng, H. Zhang, Adv. Mater. 2017, 29, [2] J. Wang, H. Fang, X. Wang, X. Chen, W. Lu, W. Hu, Small 2017, 13, [3] F. Wang, Z. Wang, C. Jiang, L. Yin, R. Cheng, X. Zhan, K. Xu, F. Wang, Y. Zhang, J. He, Small 2017, 13, [4] Y. Zhou, M. Zhang, Z. Guo, L. Miao, S.-T. Han, Z. Wang, X. Zhang, H. Zhang, Z. Peng, Mater. Horiz. 2017, 4, 997. [5] K. S. Novoselov, A. Mishchenko, A. Carvalho, A. H. Castro Neto, Science 2016, 353, aac9439. [6] W. Xia, L. Dai, P. Yu, X. Tong, W. Song, G. Zhang, Z. Wang, Nanoscale 2017, 9, [7] M. Massicotte, P. Schmidt, F. Vialla, K. G. Schadler, A. Reserbat-Plantey, K. Watanabe, T. Taniguchi, K. J. Tielrooij, F. H. Koppens, Nat. Nanotechnol. 2016, 11, 42. [8] X. Chen, X. Lu, B. Deng, O. Sinai, Y. Shao, C. Li, S. Yuan, V. Tran, K. Watanabe, T. Taniguchi, D. Naveh, L. Yang, F. Xia, Nat. Commun. 2017, 8, (6 of 7)

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