in hbn encapsulated graphene devices

Size: px
Start display at page:

Download "in hbn encapsulated graphene devices"

Transcription

1 Tunability of 1/f noise at multiple Dirac cones in hbn encapsulated graphene devices Chandan Kumar,, Manabendra Kuiri,, Jeil Jung, Tanmoy Das, and Anindya Das, Department of Physics, Indian Institute of Science, Bangalore , India, and Department of Physics, University of Seoul, Seoul , Korea FABRICATION DETAILS AND DEVICE CHARACTERIZATION: The hbn-graphene-hbn heterostructure was obtained using following steps. First hbn sheets (obtained from HQ Graphene) were mechanically exfoliated on highly p doped Si wafer with 300 nm oxide thickness, with a resistivity of Ohm-cm obtained from Nova wafers. Using dry transfer technique, 1 graphene flakes were then transferred on hbn (sitting on top of SiO 2 ). Secondly the electrical contacts were fabricated using standard electron beam lithography (EBL). The metal leads (5nm Cr/ 70 nm Au) were deposited using thermal evaporator at a base pressure of mbar. Next to put the top gate, thin hbn layer (which was mechanically exfoliated) was precisely aligned with already prepared Graphene-hBN heterostructure and transferred using the same technique discussed above. The prepared heterostructure was annealed at 300 C to have moire pattern. 2 Finally using EBL the top gate contacts was fabricated by depositing 5 nm/70 nm of Cr/Al. To whom correspondence should be addressed Department of Physics, Indian Institute of Science, Bangalore , India Department of Physics, University of Seoul, Seoul , Korea Contributed equally to this work 1

2 a) b) Figure 1: (Color Online) (a) Raman spectra of SLG1 and (b) BLG Figure 1 shows the raman spectra of SLG1 (a) and the BLG (b) measured on hbn substrate. The spectra is taken at room temperature with nm laser light. MOBILITY AND δn EXTRACTION: a) hbn-slg1-hbn Figure 2 (a) and (b) shows the conductance as a function of density, varied by the top gate at cloned Dirac (CD) and the primary Dirac (PD) respectively. Blue line is a linear fit to the data which gives the charge inhomogeneity (δn) to be cm 2, which has been shown by the shaded region. Figure 2 (c) and (d) shows the Resistance as a function of top gate voltage at the CD and the PD, respectively. As discussed in the main text the total resistance R T can be written as R T = R ch + R L where R ch is the channel resistance under the top gate and R L is the 2

3 a) b) Conductance ( µs) Conductance ( µs) n ( x /cm 2 ) n ( x /cm 2 ) c) d) Resistance ( κω) Resistance ( κω) Figure 2: (Color Online) Conductance as a function of density for (a) cloned Dirac (b) primary Dirac of SLG1 device. Blue line is a linear line fit to the curve. The shaded yellow region gives the charge inhomogeneity. Resistance as a function of top gate voltage for (c) cloned Dirac (d) primary Dirac. Blue line is a fit to the curves using equation (1). Measurement is performed at 4.2 K resistance coming from the lead (untopgated part with contacts) The R T V T G curve, of figure 2 (c) and 2 (d) is fitted with the following equation as mentioned in the manuscript. L T G R T = R L + weµ δn 2 + n 2 ch (1) From fitting we obtain mobility of 9000 and cm 2 V 1 s 1 at PD and CD, respectively. The dimension of our SLG1 device are L T G = 1.25 µm and w = 2.1 µm. 3

4 b) hbn-blg-hbn Figure 3 (a) shows the conductance as a function of density of BLG and the blue line is a linear fit near zero density, which gives charge inhomogeneity to be cm 2. a) b) Conductance ( µs) 71 Resistance ( κ Ω ) n ( x /cm 2 ) Figure 3: (Color Online) For BLG device, (a) Conductance as a function of density. Blue line is a linear fit, which gives charge inhomogeneity (shaded) yellow region. (b) Resistance verses top gate voltage at V BG =0 V. Blue line shows the linear fit with equation (1). Measurement is performed at 4.2 K Figure 3 (b) shows resistance with V T G at V BG =0 V. We see that the curve is not symmetric around zero density due to the formation of p-n junction as reported earlier, 3 hence to calculate the mobility of the device, curve is fitted with equation (1) only for negative gate voltage, which gives a mobility of cm 2 V 1 s 1. The dimension of our device is L T G = 0.5 µm and w = 2 µm. c) hbn-slg2-hbn Figure 4 (a) shows conductance as a function of density, from which we calculate the charge inhomogeneity cm 2. Figure 4 (b) shows resistance as a function of top gate voltage. Fitting the curve with equation (1) gives mobility cm 2 V 1 s 1, where L T G = 1.8 µm and w = 2 µm. 4

5 s Conductance ( µs) n ( x /cm 2 ) Resistance ( k Ω) Figure 4: (Color Online) (a) Conductance as a function of density for SLG2 device. Blue line is a linear fit. The charge inhomogeneity is given by shaded yellow region. (b) Resistance as a function of top gate voltage. Blue line is fit to the curve using equation (1). Measurement is performed at 77 K. 1/f NOISE MEASUREMENTS: The Power spectral density of SLG1 and BLG were measured using using ac lock in technique. The schematic of noise measurement technique is shown in figure 5. The sample was voltage biased (100 µv) and the current fluctuation is measured with lock in amplifier using NI 6210 DAQ card. Before the signal is fed to lock (SR 830), it is amplified by a home build V ac Top hbn S Current Amplifier Graphene D bottom hbn bottom hbn SiO 2 Si Lock in Amplifier NI DAQ Card DSP V BG Power Spectral Density Figure 5: (Color Online) Schematic of the noise measurement technique. current amplifier which has gain of 10 7 with input impedence 100 Ohm. The noise figures are v n 6nV/ Hz and current noise, i n 50fA/ Hz at 10 Hz. In our measurements 5

6 the sampling rate is kept at Hz and decimated by a factor of 128, which gives the effective sampling rate of 256 Hz. The lock in time constant is kept at 1 ms with roll off of 24dB/octave and the data is recorded for 30 minutes. Next, the data is digitally anti-aliased, down sampled and the PSD was calculated using Welch s periodogram method. The main advantage of the lock in technique is the simultaneous measurement of the signal and the background. 4 Channel X of lock in gives the signal plus background and the Y channel gives background only. Hence the PSD of the signal is obtained by subtracting the Y component from the X component. (a) Background Noise To benchmark the noise measurement technique, we measure the power spectral density (PSD) of a noiseless 10 kohm metal resistor in our dip-stick, which is shown in figure 6. As can be seen from figure 6 that both X and Y channel of the lock-in measures the background noise which remains almost flat from 0.1 to 100 Hz. The measured background noise is A 2 /Hz. At low temperature the main source of background noise comes from the voltage noise of the amplifier [ i 2 n = ( vn R )2 ], which is A 2 /Hz from a 10 kohm resistor with v n 6 nv/hz. The value of the background noise depends on the resistance of the sample. For low resistance sample (0.1 to 2 kohm) i 2 n becomes large. Hence the noise of SLG2 is measured by voltage amplifier in a 4 probe geometry. We use the SR552 voltage amplifier with voltage noise of 2.1 nv/ Hz and input impedence of 100 kohm. (b) Noise amplitude and noise spectral density The noise amplitude ( A ) is calculated as 5 A = 1 N N f m S Im /Im 2 (2) m=1 where I m is the source drain current, S Im is the noise spectral density and f m are the frequencies over which noise amplitude is averaged. 6

7 Lock in X channel Lock in Y channel S I (A 2 /Hz) Frequency (Hz) Figure 6: (Color Online) Noise spectral density as a function of frequency for 20 kω resistor at 77 K. a) b) BackGround 1/f noise PD S I (A 2 /Hz) β = 1 β CD Frequency (Hz) Figure 7: (Color Online) (a) Noise spectral density of BLG as a function of frequency at V T G = 1.5 V and V BG = 25 V. (b) Value of β at PD cone and the CD cone of SLG1. Figure 7 (a) shows the typical noise spectral density of the BLG device. It can be seen that the background noise is much smaller compared to 1/f noise of the device. In our measurement, noise remains as 1/f nature with β = 1 even upto 100 Hz. This is further confirmed by looking at β close to PD and CD of SLG1 (figure 7 (b)). 7

8 (c) 2D noise in bipolar regime We have two different region in our device- one controlled only by back gate (region 1) where density, n BG = C BGV BG e and other which is controlled by both back gate and top gate (region 2), where density n T G = C T GV T G +C BG V BG. Here C e BG and C T G are the back gate and top gate capacitance respectively. Different combination of back gate and top gate voltages will lead to the formation of unipolar (n-n*-n or p-p*-p) and bipolar (n-p-n or p-n-p) region. The schematic of the generated potential, V in unipolar and bipolar regime is shown in figure 8 (a) and 8 (b) respectively. Since graphene has a linear dispersion relation E = hv F πn and all the energies are measured with respect to the Dirac point, the generated potential is given by the difference of energy in region 1 and 2 as shown schematically in figure 8. a) b) p p* p p n p E F V E F V Figure 8: (Color Online) (a) Schematic of potential generated in (a) unipolar and (b) bipolar regime. The potential generated is given by ) CBG V BG CT G V T G + C BG V BG V = hv F π (sgn(c BG V BG ) sgn(c T G V T G + C BG V BG ) e e Figure 9 (a) shows the 2D plot of noise amplitude A as a function of V BG and V T G for SLG2 at 77 K in linear scale. The generated potential is shown in figure 9 (b). 8

9 V BG A (x 10 7 ) V BG ( V ) n-p-n p-p*-p n-n*-n p-n-p ( V ) V ( mev ) Figure 9: (Color Online) (a) Noise Amplitude as a function of V BG and V T G for SLG2 device measured at 77 K. (b) Potential generated in unipolar and bipolar region. References phkh (1) Zomer, P.; Dash, S.; Tombros, N.; Van Wees, B. Applied Physics Letters 2011, 99, (2) Wang, L.; Gao, Y.; Wen, B.; Han, Z.; Taniguchi, T.; Watanabe, K.; Koshino, M.; Hone, J.; Dean, C. R. arxiv preprint arxiv: , (3) Özyilmaz, B.; Jarillo-Herrero, P.; Efetov, D.; Abanin, D. A.; Levitov, L. S.; Kim, P. Physical review letters 2007, 99, (4) Ghosh, A.; Kar, S.; Bid, A.; Raychaudhuri, A. arxiv preprint cond-mat/ , (5) Balandin, A. A. Nature nanotechnology 2013, 8,

High-Speed Scalable Silicon-MoS 2 P-N Heterojunction Photodetectors

High-Speed Scalable Silicon-MoS 2 P-N Heterojunction Photodetectors High-Speed Scalable Silicon-MoS 2 P-N Heterojunction Photodetectors Veerendra Dhyani 1, and Samaresh Das 1* 1 Centre for Applied Research in Electronics, Indian Institute of Technology Delhi, New Delhi-110016,

More information

Reconfigurable Complementary Monolayer MoTe2. Field-Effect Transistors for Integrated Circuits. Supporting Information

Reconfigurable Complementary Monolayer MoTe2. Field-Effect Transistors for Integrated Circuits. Supporting Information Reconfigurable Complementary Monolayer MoTe2 Field-Effect Transistors for Integrated Circuits Supporting Information Stefano Larentis, Babak Fallahazad, Hema C. P. Movva, Kyounghwan Kim, Amritesh Rai,

More information

Gigahertz Ambipolar Frequency Multiplier Based on Cvd Graphene

Gigahertz Ambipolar Frequency Multiplier Based on Cvd Graphene Gigahertz Ambipolar Frequency Multiplier Based on Cvd Graphene The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters. Citation As Published

More information

GRADE Graphene-based Devices and Circuits for RF Applications Collaborative Project

GRADE Graphene-based Devices and Circuits for RF Applications Collaborative Project GRADE Graphene-based Devices and Circuits for RF Applications Collaborative Project WP 6 D6.1 DC, S parameter and High Frequency Noise Characterisation of GFET devices Main Authors: Sebastien Fregonese,

More information

Supporting Information. Vertical Graphene-Base Hot-Electron Transistor

Supporting Information. Vertical Graphene-Base Hot-Electron Transistor Supporting Information Vertical Graphene-Base Hot-Electron Transistor Caifu Zeng, Emil B. Song, Minsheng Wang, Sejoon Lee, Carlos M. Torres Jr., Jianshi Tang, Bruce H. Weiller, and Kang L. Wang Department

More information

Supplementary Figure 1 Schematic illustration of fabrication procedure of MoS2/h- BN/graphene heterostructures. a, c d Supplementary Figure 2

Supplementary Figure 1 Schematic illustration of fabrication procedure of MoS2/h- BN/graphene heterostructures. a, c d Supplementary Figure 2 Supplementary Figure 1 Schematic illustration of fabrication procedure of MoS 2 /hon a 300- BN/graphene heterostructures. a, CVD-grown b, Graphene was patterned into graphene strips by oxygen monolayer

More information

Department of Electrical Engineering IIT Madras

Department of Electrical Engineering IIT Madras Department of Electrical Engineering IIT Madras Sample Questions on Semiconductor Devices EE3 applicants who are interested to pursue their research in microelectronics devices area (fabrication and/or

More information

Conductance switching in Ag 2 S devices fabricated by sulphurization

Conductance switching in Ag 2 S devices fabricated by sulphurization 3 Conductance switching in Ag S devices fabricated by sulphurization The electrical characterization and switching properties of the α-ag S thin films fabricated by sulfurization are presented in this

More information

Supplementary Materials for

Supplementary Materials for www.sciencemag.org/cgi/content/full/science.1234855/dc1 Supplementary Materials for Taxel-Addressable Matrix of Vertical-Nanowire Piezotronic Transistors for Active/Adaptive Tactile Imaging Wenzhuo Wu,

More information

MoS 2 nanosheet phototransistors with thicknessmodulated

MoS 2 nanosheet phototransistors with thicknessmodulated Supporting Information MoS 2 nanosheet phototransistors with thicknessmodulated optical energy gap Hee Sung Lee, Sung-Wook Min, Youn-Gyung Chang, Park Min Kyu, Taewook Nam, # Hyungjun Kim, # Jae Hoon Kim,

More information

Supporting Information. Single-Nanowire Electrochemical Probe Detection for Internally Optimized Mechanism of

Supporting Information. Single-Nanowire Electrochemical Probe Detection for Internally Optimized Mechanism of Supporting Information Single-Nanowire Electrochemical Probe Detection for Internally Optimized Mechanism of Porous Graphene in Electrochemical Devices Ping Hu, Mengyu Yan, Xuanpeng Wang, Chunhua Han,*

More information

INTRODUCTION: Basic operating principle of a MOSFET:

INTRODUCTION: Basic operating principle of a MOSFET: INTRODUCTION: Along with the Junction Field Effect Transistor (JFET), there is another type of Field Effect Transistor available whose Gate input is electrically insulated from the main current carrying

More information

Supplementary Figure 1. Schematics of conventional vdw stacking process. Thin layers of h-bn are used as bottom (a) and top (b) layer, respectively.

Supplementary Figure 1. Schematics of conventional vdw stacking process. Thin layers of h-bn are used as bottom (a) and top (b) layer, respectively. Supplementary Figure 1. Schematics of conventional vdw stacking process. Thin layers of h-bn are used as bottom (a) and top (b) layer, respectively. When the top layer is ultra thin, chances of having

More information

Unit III FET and its Applications. 2 Marks Questions and Answers

Unit III FET and its Applications. 2 Marks Questions and Answers Unit III FET and its Applications 2 Marks Questions and Answers 1. Why do you call FET as field effect transistor? The name field effect is derived from the fact that the current is controlled by an electric

More information

Supplementary Materials for

Supplementary Materials for advances.sciencemag.org/cgi/content/full/4/2/e1700324/dc1 Supplementary Materials for Photocarrier generation from interlayer charge-transfer transitions in WS2-graphene heterostructures Long Yuan, Ting-Fung

More information

Integrated diodes. The forward voltage drop only slightly depends on the forward current. ELEKTRONIKOS ĮTAISAI

Integrated diodes. The forward voltage drop only slightly depends on the forward current. ELEKTRONIKOS ĮTAISAI 1 Integrated diodes pn junctions of transistor structures can be used as integrated diodes. The choice of the junction is limited by the considerations of switching speed and breakdown voltage. The forward

More information

D. Impedance probe fabrication and characterization

D. Impedance probe fabrication and characterization D. Impedance probe fabrication and characterization This section summarizes the fabrication process of the MicroCard bioimpedance probes. The characterization process is also described and the main electrical

More information

Hiroshi Murata and Yasuyuki Okamura. 1. Introduction. 2. Waveguide Fabrication

Hiroshi Murata and Yasuyuki Okamura. 1. Introduction. 2. Waveguide Fabrication OptoElectronics Volume 2008, Article ID 654280, 4 pages doi:10.1155/2008/654280 Research Article Fabrication of Proton-Exchange Waveguide Using Stoichiometric itao 3 for Guided Wave Electrooptic Modulators

More information

CHAPTER 2 POLARIZATION SPLITTER- ROTATOR BASED ON A DOUBLE- ETCHED DIRECTIONAL COUPLER

CHAPTER 2 POLARIZATION SPLITTER- ROTATOR BASED ON A DOUBLE- ETCHED DIRECTIONAL COUPLER CHAPTER 2 POLARIZATION SPLITTER- ROTATOR BASED ON A DOUBLE- ETCHED DIRECTIONAL COUPLER As we discussed in chapter 1, silicon photonics has received much attention in the last decade. The main reason is

More information

Supplementary information for

Supplementary information for Supplementary information for A fast and low power microelectromechanical system based nonvolatile memory device Sang Wook Lee, Seung Joo Park, Eleanor E. B. Campbell & Yung Woo Park The supplementary

More information

Radio-frequency scanning tunneling microscopy

Radio-frequency scanning tunneling microscopy doi: 10.1038/nature06238 SUPPLEMENARY INFORMAION Radio-frequency scanning tunneling microscopy U. Kemiktarak 1,. Ndukum 2, K.C. Schwab 2, K.L. Ekinci 3 1 Department of Physics, Boston University, Boston,

More information

Transparent p-type SnO Nanowires with Unprecedented Hole Mobility among Oxide Semiconductors

Transparent p-type SnO Nanowires with Unprecedented Hole Mobility among Oxide Semiconductors Supplementary Information Transparent p-type SnO Nanowires with Unprecedented Hole Mobility among Oxide Semiconductors J. A. Caraveo-Frescas and H. N. Alshareef* Materials Science and Engineering, King

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 11/6/2007 MOSFETs Lecture 6 BJTs- Lecture 1 Reading Assignment: Chapter 10 More Scalable Device Structures Vertical Scaling is important. For example,

More information

Laboratory #5 BJT Basics and MOSFET Basics

Laboratory #5 BJT Basics and MOSFET Basics Laboratory #5 BJT Basics and MOSFET Basics I. Objectives 1. Understand the physical structure of BJTs and MOSFETs. 2. Learn to measure I-V characteristics of BJTs and MOSFETs. II. Components and Instruments

More information

Supporting Information

Supporting Information Supporting Information Fabrication and Transfer of Flexible Few-Layers MoS 2 Thin Film Transistors to any arbitrary substrate Giovanni A. Salvatore 1, *, Niko Münzenrieder 1, Clément Barraud 2, Luisa Petti

More information

Three Terminal Devices

Three Terminal Devices Three Terminal Devices - field effect transistor (FET) - bipolar junction transistor (BJT) - foundation on which modern electronics is built - active devices - devices described completely by considering

More information

Supporting information: Visualizing the motion of. graphene nanodrums

Supporting information: Visualizing the motion of. graphene nanodrums Supporting information: Visualizing the motion of graphene nanodrums Dejan Davidovikj,, Jesse J Slim, Santiago J Cartamil-Bueno, Herre S J van der Zant, Peter G Steeneken, and Warner J Venstra,, Kavli

More information

Characterization of SOI MOSFETs by means of charge-pumping

Characterization of SOI MOSFETs by means of charge-pumping Paper Characterization of SOI MOSFETs by means of charge-pumping Grzegorz Głuszko, Sławomir Szostak, Heinrich Gottlob, Max Lemme, and Lidia Łukasiak Abstract This paper presents the results of charge-pumping

More information

MSE 410/ECE 340: Electrical Properties of Materials Fall 2016 Micron School of Materials Science and Engineering Boise State University

MSE 410/ECE 340: Electrical Properties of Materials Fall 2016 Micron School of Materials Science and Engineering Boise State University MSE 410/ECE 340: Electrical Properties of Materials Fall 2016 Micron School of Materials Science and Engineering Boise State University Practice Final Exam 1 Read the questions carefully Label all figures

More information

High-Ohmic Resistors using Nanometer-Thin Pure-Boron Chemical-Vapour-Deposited Layers

High-Ohmic Resistors using Nanometer-Thin Pure-Boron Chemical-Vapour-Deposited Layers High-Ohmic Resistors using Nanometer-Thin Pure-Boron Chemical-Vapour-Deposited Layers Negin Golshani, Vahid Mohammadi, Siva Ramesh, Lis K. Nanver Delft University of Technology The Netherlands ESSDERC

More information

Explicit drain-current model of graphene field-effect transistors targeting analog and radio-frequency applications. David Jiménez and Oana Moldovan

Explicit drain-current model of graphene field-effect transistors targeting analog and radio-frequency applications. David Jiménez and Oana Moldovan Explicit drain-current model of graphene field-effect transistors targeting analog and radio-frequency applications David Jiménez and Oana Moldovan Departament d'enginyeria Electrònica, Escola d'enginyeria,

More information

AE53/AC53/AT53/AE103 ELECT. DEVICES & CIRCUITS DEC 2015

AE53/AC53/AT53/AE103 ELECT. DEVICES & CIRCUITS DEC 2015 Q.2 a. By using Norton s theorem, find the current in the load resistor R L for the circuit shown in Fig.1. (8) Fig.1 IETE 1 b. Explain Z parameters and also draw an equivalent circuit of the Z parameter

More information

Supporting Information. Air-stable surface charge transfer doping of MoS 2 by benzyl viologen

Supporting Information. Air-stable surface charge transfer doping of MoS 2 by benzyl viologen Supporting Information Air-stable surface charge transfer doping of MoS 2 by benzyl viologen Daisuke Kiriya,,ǁ, Mahmut Tosun,,ǁ, Peida Zhao,,ǁ, Jeong Seuk Kang, and Ali Javey,,ǁ,* Electrical Engineering

More information

Graphene electro-optic modulator with 30 GHz bandwidth

Graphene electro-optic modulator with 30 GHz bandwidth Graphene electro-optic modulator with 30 GHz bandwidth Christopher T. Phare 1, Yoon-Ho Daniel Lee 1, Jaime Cardenas 1, and Michal Lipson 1,2,* 1School of Electrical and Computer Engineering, Cornell University,

More information

4 Transistors. 4.1 IV Relations

4 Transistors. 4.1 IV Relations 4 Transistors Due date: Sunday, September 19 (midnight) Reading (Bipolar transistors): HH sections 2.01-2.07, (pgs. 62 77) Reading (Field effect transistors) : HH sections 3.01-3.03, 3.11-3.12 (pgs. 113

More information

EXPERIMENT # 1: REVERSE ENGINEERING OF INTEGRATED CIRCUITS Week of 1/17/05

EXPERIMENT # 1: REVERSE ENGINEERING OF INTEGRATED CIRCUITS Week of 1/17/05 EXPERIMENT # 1: REVERSE ENGINEERING OF INTEGRATED CIRCUITS Week of 1/17/5 Experiment #1: Reading: Reverse engineering of integrated circuits Jaeger 9.2: MOS transistor layout and design rules HP4145 basics:

More information

FIELD EFFECT TRANSISTOR (FET) 1. JUNCTION FIELD EFFECT TRANSISTOR (JFET)

FIELD EFFECT TRANSISTOR (FET) 1. JUNCTION FIELD EFFECT TRANSISTOR (JFET) FIELD EFFECT TRANSISTOR (FET) The field-effect transistor (FET) is a three-terminal device used for a variety of applications that match, to a large extent, those of the BJT transistor. Although there

More information

Logic circuits based on carbon nanotubes

Logic circuits based on carbon nanotubes Available online at www.sciencedirect.com Physica E 16 (23) 42 46 www.elsevier.com/locate/physe Logic circuits based on carbon nanotubes A. Bachtold a;b;, P. Hadley a, T. Nakanishi a, C. Dekker a a Department

More information

IMPROVED CURRENT MIRROR OUTPUT PERFORMANCE BY USING GRADED-CHANNEL SOI NMOSFETS

IMPROVED CURRENT MIRROR OUTPUT PERFORMANCE BY USING GRADED-CHANNEL SOI NMOSFETS IMPROVED CURRENT MIRROR OUTPUT PERFORMANCE BY USING GRADED-CHANNEL SOI NMOSFETS Marcelo Antonio Pavanello *, João Antonio Martino and Denis Flandre 1 Laboratório de Sistemas Integráveis Escola Politécnica

More information

Han Liu, Adam T. Neal, Yuchen Du and Peide D. Ye

Han Liu, Adam T. Neal, Yuchen Du and Peide D. Ye Fundamentals in MoS2 Transistors: Dielectric, Scaling and Metal Contacts Han Liu, Adam T. Neal, Yuchen Du and Peide D. Ye Department of Electrical and Computer Engineering and Birck Nanotechnology Center,

More information

Low Thermal Resistance Flip-Chip Bonding of 850nm 2-D VCSEL Arrays Capable of 10 Gbit/s/ch Operation

Low Thermal Resistance Flip-Chip Bonding of 850nm 2-D VCSEL Arrays Capable of 10 Gbit/s/ch Operation Low Thermal Resistance Flip-Chip Bonding of 85nm -D VCSEL Arrays Capable of 1 Gbit/s/ch Operation Hendrik Roscher In 3, our well established technology of flip-chip mounted -D 85 nm backside-emitting VCSEL

More information

Chapter 8: Field Effect Transistors

Chapter 8: Field Effect Transistors Chapter 8: Field Effect Transistors Transistors are different from the basic electronic elements in that they have three terminals. Consequently, we need more parameters to describe their behavior than

More information

Chapter 8: Field Effect Transistors

Chapter 8: Field Effect Transistors Chapter 8: Field Effect Transistors Transistors are different from the basic electronic elements in that they have three terminals. Consequently, we need more parameters to describe their behavior than

More information

EE C245 ME C218 Introduction to MEMS Design

EE C245 ME C218 Introduction to MEMS Design EE C45 ME C18 Introduction to MEMS Design Fall 008 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 9470 Lecture 7: Noise &

More information

Tunable Color Filters Based on Metal-Insulator-Metal Resonators

Tunable Color Filters Based on Metal-Insulator-Metal Resonators Chapter 6 Tunable Color Filters Based on Metal-Insulator-Metal Resonators 6.1 Introduction In this chapter, we discuss the culmination of Chapters 3, 4, and 5. We report a method for filtering white light

More information

MAAP Power Amplifier, 15 W GHz Rev. V1. Features. Functional Schematic. Description. Pin Configuration 2. Ordering Information

MAAP Power Amplifier, 15 W GHz Rev. V1. Features. Functional Schematic. Description. Pin Configuration 2. Ordering Information Features 15 W Power Amplifier 42 dbm Saturated Pulsed Output Power 17 db Large Signal Gain P SAT >40% Power Added Efficiency Dual Sided Bias Architecture On Chip Bias Circuit 100% On-Wafer DC, RF and Output

More information

HA-2520, HA-2522, HA-2525

HA-2520, HA-2522, HA-2525 HA-, HA-, HA- Data Sheet September 99 File Number 9. MHz, High Slew Rate, Uncompensated, High Input Impedance, Operational Amplifiers HA-// comprise a series of operational amplifiers delivering an unsurpassed

More information

ECE4902 B2015 HW Set 1

ECE4902 B2015 HW Set 1 ECE4902 B2015 HW Set 1 Due in class Tuesday November 3. To make life easier on the graders: Be sure your NAME and ECE MAILBOX NUMBER are prominently displayed on the upper right of what you hand in. When

More information

Solid State Device Fundamentals

Solid State Device Fundamentals Solid State Device Fundamentals 4.4. Field Effect Transistor (MOSFET) ENS 463 Lecture Course by Alexander M. Zaitsev alexander.zaitsev@csi.cuny.edu Tel: 718 982 2812 4N101b 1 Field-effect transistor (FET)

More information

Ultra High-Speed InGaAs Nano-HEMTs

Ultra High-Speed InGaAs Nano-HEMTs Ultra High-Speed InGaAs Nano-HEMTs 2003. 10. 14 Kwang-Seok Seo School of Electrical Eng. and Computer Sci. Seoul National Univ., Korea Contents Introduction to InGaAsNano-HEMTs Nano Patterning Process

More information

6.012 Microelectronic Devices and Circuits

6.012 Microelectronic Devices and Circuits Page 1 of 13 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Microelectronic Devices and Circuits Final Eam Closed Book: Formula sheet provided;

More information

Field Effect Transistors

Field Effect Transistors Field Effect Transistors Purpose In this experiment we introduce field effect transistors (FETs). We will measure the output characteristics of a FET, and then construct a common-source amplifier stage,

More information

photolithographic techniques (1). Molybdenum electrodes (50 nm thick) are deposited by

photolithographic techniques (1). Molybdenum electrodes (50 nm thick) are deposited by Supporting online material Materials and Methods Single-walled carbon nanotube (SWNT) devices are fabricated using standard photolithographic techniques (1). Molybdenum electrodes (50 nm thick) are deposited

More information

Long-distance propagation of short-wavelength spin waves. Liu et al.

Long-distance propagation of short-wavelength spin waves. Liu et al. Long-distance propagation of short-wavelength spin waves Liu et al. Supplementary Note 1. Characterization of the YIG thin film Supplementary fig. 1 shows the characterization of the 20-nm-thick YIG film

More information

Field-Effect Transistor

Field-Effect Transistor Philadelphia University Faculty of Engineering Communication and Electronics Engineering Field-Effect Transistor Introduction FETs (Field-Effect Transistors) are much like BJTs (Bipolar Junction Transistors).

More information

EJERCICIOS DE COMPONENTES ELECTRÓNICOS. 1 er cuatrimestre

EJERCICIOS DE COMPONENTES ELECTRÓNICOS. 1 er cuatrimestre EJECICIOS DE COMPONENTES ELECTÓNICOS. 1 er cuatrimestre 2 o Ingeniería Electrónica Industrial Juan Antonio Jiménez Tejada Índice 1. Basic concepts of Electronics 1 2. Passive components 1 3. Semiconductors.

More information

2.8 - CMOS TECHNOLOGY

2.8 - CMOS TECHNOLOGY CMOS Technology (6/7/00) Page 1 2.8 - CMOS TECHNOLOGY INTRODUCTION Objective The objective of this presentation is: 1.) Illustrate the fabrication sequence for a typical MOS transistor 2.) Show the physical

More information

EDC UNIT IV- Transistor and FET Characteristics EDC Lesson 9- ", Raj Kamal, 1

EDC UNIT IV- Transistor and FET Characteristics EDC Lesson 9- , Raj Kamal, 1 EDC UNIT IV- Transistor and FET Characteristics Lesson-9: JFET and Construction of JFET 2008 EDC Lesson 9- ", Raj Kamal, 1 1. Transistor 2008 EDC Lesson 9- ", Raj Kamal, 2 Transistor Definition The transferred-resistance

More information

Low frequency noise in GaN metal semiconductor and metal oxide semiconductor field effect transistors

Low frequency noise in GaN metal semiconductor and metal oxide semiconductor field effect transistors JOURNAL OF APPLIED PHYSICS VOLUME 90, NUMBER 1 1 JULY 001 Low frequency noise in GaN metal semiconductor and metal oxide semiconductor field effect transistors S. L. Rumyantsev, a) N. Pala, b) M. S. Shur,

More information

Analog Synaptic Behavior of a Silicon Nitride Memristor

Analog Synaptic Behavior of a Silicon Nitride Memristor Supporting Information Analog Synaptic Behavior of a Silicon Nitride Memristor Sungjun Kim, *, Hyungjin Kim, Sungmin Hwang, Min-Hwi Kim, Yao-Feng Chang,, and Byung-Gook Park *, Inter-university Semiconductor

More information

A Generalized noise study of solid-state nanopores at low frequencies

A Generalized noise study of solid-state nanopores at low frequencies Supporting Information A Generalized noise study of solid-state nanopores at low frequencies Chenyu Wen, 1, Shuangshuang Zeng, 1, Kai Arstila, 2 Timo Sajavaara, 2 Yu Zhu 3, Zhen Zhang, 1, * and Shi-Li

More information

Chapter 4. CMOS Cascode Amplifiers. 4.1 Introduction. 4.2 CMOS Cascode Amplifiers

Chapter 4. CMOS Cascode Amplifiers. 4.1 Introduction. 4.2 CMOS Cascode Amplifiers Chapter 4 CMOS Cascode Amplifiers 4.1 Introduction A single stage CMOS amplifier cannot give desired dc voltage gain, output resistance and transconductance. The voltage gain can be made to attain higher

More information

Understanding the Magnetic Resonance Spectrum of Nitrogen Vacancy Centers in an Ensemble of Randomly-Oriented Nanodiamonds, Supporting Information

Understanding the Magnetic Resonance Spectrum of Nitrogen Vacancy Centers in an Ensemble of Randomly-Oriented Nanodiamonds, Supporting Information Understanding the Magnetic Resonance Spectrum of Nitrogen Vacancy Centers in an Ensemble of Randomly-Oriented Nanodiamonds, Supporting Information Keunhong Jeong *1,2, Anna J. Parker *1,2, Ralph H. Page

More information

HA-2600, HA Features. 12MHz, High Input Impedance Operational Amplifiers. Applications. Pinouts. Ordering Information

HA-2600, HA Features. 12MHz, High Input Impedance Operational Amplifiers. Applications. Pinouts. Ordering Information HA26, HA26 September 998 File Number 292.3 2MHz, High Input Impedance Operational Amplifiers HA26/26 are internally compensated bipolar operational amplifiers that feature very high input impedance (MΩ,

More information

Si and InP Integration in the HELIOS project

Si and InP Integration in the HELIOS project Si and InP Integration in the HELIOS project J.M. Fedeli CEA-LETI, Grenoble ( France) ECOC 2009 1 Basic information about HELIOS HELIOS photonics ELectronics functional Integration on CMOS www.helios-project.eu

More information

Lecture - 18 Transistors

Lecture - 18 Transistors Electronic Materials, Devices and Fabrication Dr. S. Prarasuraman Department of Metallurgical and Materials Engineering Indian Institute of Technology, Madras Lecture - 18 Transistors Last couple of classes

More information

EIE209 Basic Electronics. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: T ransistor devices

EIE209 Basic Electronics. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: T ransistor devices EIE209 Basic Electronics Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Three-terminal device whose voltage-current relationship is controlled by a third voltage

More information

Integrated Circuits: FABRICATION & CHARACTERISTICS - 4. Riju C Issac

Integrated Circuits: FABRICATION & CHARACTERISTICS - 4. Riju C Issac Integrated Circuits: FABRICATION & CHARACTERISTICS - 4 Riju C Issac INTEGRATED RESISTORS Resistor in a monolithic IC is very often obtained by the bulk resistivity of one of the diffused areas. P-type

More information

Logic Circuits Using Solution-Processed Single-Walled Carbon. Nanotube Transistors

Logic Circuits Using Solution-Processed Single-Walled Carbon. Nanotube Transistors Logic Circuits Using Solution-Processed Single-Walled Carbon Nanotube Transistors Ryo Nouchi a), Haruo Tomita, Akio Ogura and Masashi Shiraishi Division of Materials Physics, Graduate School of Engineering

More information

In this lecture we will begin a new topic namely the Metal-Oxide-Semiconductor Field Effect Transistor.

In this lecture we will begin a new topic namely the Metal-Oxide-Semiconductor Field Effect Transistor. Solid State Devices Dr. S. Karmalkar Department of Electronics and Communication Engineering Indian Institute of Technology, Madras Lecture - 38 MOS Field Effect Transistor In this lecture we will begin

More information

Nanophotonic trapping for precise manipulation of biomolecular arrays

Nanophotonic trapping for precise manipulation of biomolecular arrays SUPPLEMENTARY INFORMATION DOI: 10.1038/NNANO.2014.79 Nanophotonic trapping for precise manipulation of biomolecular arrays Mohammad Soltani, Jun Lin, Robert A. Forties, James T. Inman, Summer N. Saraf,

More information

n-channel LDMOS WITH STI FOR BREAKDOWN VOLTAGE ENHANCEMENT AND IMPROVED R ON

n-channel LDMOS WITH STI FOR BREAKDOWN VOLTAGE ENHANCEMENT AND IMPROVED R ON n-channel LDMOS WITH STI FOR BREAKDOWN VOLTAGE ENHANCEMENT AND IMPROVED R ON 1 SUNITHA HD, 2 KESHAVENI N 1 Asstt Prof., Department of Electronics Engineering, EPCET, Bangalore 2 Prof., Department of Electronics

More information

DESIGN OF A 4-BiT PMOS PARALLEL COMPARATOR AID CONVERTER. Amel Gaddo 5th year Microelectronic Engineering Student Rochester Institute of TechnologY

DESIGN OF A 4-BiT PMOS PARALLEL COMPARATOR AID CONVERTER. Amel Gaddo 5th year Microelectronic Engineering Student Rochester Institute of TechnologY DESIGN OF A 4-BiT PMOS PARALLEL COMPARATOR AID CONVERTER Amel Gaddo 5th year Microelectronic Engineering Student Rochester Institute of TechnologY ABSTRACT INTRODUCTION This project dealt with the design

More information

EE 5611 Introduction to Microelectronic Technologies Fall Thursday, September 04, 2014 Lecture 02

EE 5611 Introduction to Microelectronic Technologies Fall Thursday, September 04, 2014 Lecture 02 EE 5611 Introduction to Microelectronic Technologies Fall 2014 Thursday, September 04, 2014 Lecture 02 1 Lecture Outline Review on semiconductor materials Review on microelectronic devices Example of microelectronic

More information

Characterization of SC CVD diamond detectors for heavy ions spectroscopy

Characterization of SC CVD diamond detectors for heavy ions spectroscopy Characterization of SC CVD diamond detectors for heavy ions spectroscopy Characterization of SC CVD diamond detectors for heavy and ions MIPsspectroscopy timing and MIPs timing Michal Pomorski and GSI

More information

Impact of Basal Plane Dislocations and Ruggedness of 10 kv 4H-SiC Transistors

Impact of Basal Plane Dislocations and Ruggedness of 10 kv 4H-SiC Transistors 11th International MOS-AK Workshop (co-located with the IEDM and CMC Meetings) Silicon Valley, December 5, 2018 Impact of Basal Plane Dislocations and Ruggedness of 10 kv 4H-SiC Transistors *, A. Kumar,

More information

NOISE IN MEMS PIEZORESISTIVE CANTILEVER

NOISE IN MEMS PIEZORESISTIVE CANTILEVER NOISE IN MEMS PIEZORESISTIVE CANTILEVER Udit Narayan Bera Mechatronics, IIITDM Jabalpur, (India) ABSTRACT Though pezoresistive cantilevers are very popular for various reasons, they are prone to noise

More information

Electric polarization properties of single bacteria measured with electrostatic force microscopy

Electric polarization properties of single bacteria measured with electrostatic force microscopy Electric polarization properties of single bacteria measured with electrostatic force microscopy Theoretical and practical studies of Dielectric constant of single bacteria and smaller elements Daniel

More information

SUPPLEMENTARY INFORMATION

SUPPLEMENTARY INFORMATION SUPPLEMENTARY INFORMATION doi:10.1038/nature11293 1. Formation of (111)B polar surface on Si(111) for selective-area growth of InGaAs nanowires on Si. Conventional III-V nanowires (NWs) tend to grow in

More information

55:041 Electronic Circuits

55:041 Electronic Circuits 55:041 Electronic Circuits MOSFETs Sections of Chapter 3 &4 A. Kruger MOSFETs, Page-1 Basic Structure of MOS Capacitor Sect. 3.1 Width = 1 10-6 m or less Thickness = 50 10-9 m or less ` MOS Metal-Oxide-Semiconductor

More information

Wu Lu Department of Electrical and Computer Engineering and Microelectronics Laboratory, University of Illinois, Urbana, Illinois 61801

Wu Lu Department of Electrical and Computer Engineering and Microelectronics Laboratory, University of Illinois, Urbana, Illinois 61801 Comparative study of self-aligned and nonself-aligned SiGe p-metal oxide semiconductor modulation-doped field effect transistors with nanometer gate lengths Wu Lu Department of Electrical and Computer

More information

Supplementary Information. The origin of discrete current fluctuations in a fresh single molecule junction

Supplementary Information. The origin of discrete current fluctuations in a fresh single molecule junction Electronic Supplementary Material (ESI) for Nanoscale. This journal is The Royal Society of Chemistry 2014 Supplementary Information The origin of discrete current fluctuations in a fresh single molecule

More information

Supporting Information

Supporting Information Solution-processed Nickel Oxide Hole Injection/Transport Layers for Efficient Solution-processed Organic Light- Emitting Diodes Supporting Information 1. C 1s high resolution X-ray Photoemission Spectroscopy

More information

HA-2520, HA MHz, High Slew Rate, Uncompensated, High Input Impedance, Operational Amplifiers. Features. Applications. Ordering Information

HA-2520, HA MHz, High Slew Rate, Uncompensated, High Input Impedance, Operational Amplifiers. Features. Applications. Ordering Information HA-22, HA-22 Data Sheet August, 2 FN2894. 2MHz, High Slew Rate, Uncompensated, High Input Impedance, Operational Amplifiers HA-22/22 comprise a series of operational amplifiers delivering an unsurpassed

More information

EXPERIMENT 5 CURRENT AND VOLTAGE CHARACTERISTICS OF BJT

EXPERIMENT 5 CURRENT AND VOLTAGE CHARACTERISTICS OF BJT EXPERIMENT 5 CURRENT AND VOLTAGE CHARACTERISTICS OF BJT 1. OBJECTIVES 1.1 To practice how to test NPN and PNP transistors using multimeter. 1.2 To demonstrate the relationship between collector current

More information

BJT Amplifier. Superposition principle (linear amplifier)

BJT Amplifier. Superposition principle (linear amplifier) BJT Amplifier Two types analysis DC analysis Applied DC voltage source AC analysis Time varying signal source Superposition principle (linear amplifier) The response of a linear amplifier circuit excited

More information

S1. Current-induced switching in the magnetic tunnel junction.

S1. Current-induced switching in the magnetic tunnel junction. S1. Current-induced switching in the magnetic tunnel junction. Current-induced switching was observed at room temperature at various external fields. The sample is prepared on the same chip as that used

More information

discovery in 1993 [1]. These molecules are interesting due to their superparamagneticlike

discovery in 1993 [1]. These molecules are interesting due to their superparamagneticlike Preliminary spectroscopy measurements of Al-Al 2 O x -Pb tunnel junctions doped with single molecule magnets J. R. Nesbitt Department of Physics, University of Florida Tunnel junctions have been fabricated

More information

ECSE 6300 IC Fabrication Laboratory Lecture 10 Device Characterization. Die Image

ECSE 6300 IC Fabrication Laboratory Lecture 10 Device Characterization. Die Image ECSE 6300 IC Fabrication Laboratory Lecture 10 Device Characterization Prof. Bldg. CII, Rooms 6229 Rensselaer Polytechnic Institute Troy, NY 12180 Tel. (518)276-2909 e-mails: luj@rpi.edu http://www.ecse.rpi.edu/courses/s18/ecse

More information

Wafer-scale 3D integration of silicon-on-insulator RF amplifiers

Wafer-scale 3D integration of silicon-on-insulator RF amplifiers Wafer-scale integration of silicon-on-insulator RF amplifiers The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters. Citation As Published

More information

Spectral phase shaping for high resolution CARS spectroscopy around 3000 cm 1

Spectral phase shaping for high resolution CARS spectroscopy around 3000 cm 1 Spectral phase shaping for high resolution CARS spectroscopy around 3 cm A.C.W. van Rhijn, S. Postma, J.P. Korterik, J.L. Herek, and H.L. Offerhaus Mesa + Research Institute for Nanotechnology, University

More information

Field-Effect Transistor

Field-Effect Transistor Module: Electronics Module Number: 610/6501- Philadelphia University Faculty of Engineering Communication and Electronics Engineering Field-Effect Transistor ntroduction FETs (Field-Effect Transistors)

More information

Theory and Applications of Frequency Domain Laser Ultrasonics

Theory and Applications of Frequency Domain Laser Ultrasonics 1st International Symposium on Laser Ultrasonics: Science, Technology and Applications July 16-18 2008, Montreal, Canada Theory and Applications of Frequency Domain Laser Ultrasonics Todd W. MURRAY 1,

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 11/01/2007 MOSFETs Lecture 5 Announcements HW7 set is due now HW8 is assigned, but will not be collected/graded. MOSFET Technology Scaling Technology

More information

UNIT-VI FIELD EFFECT TRANSISTOR. 1. Explain about the Field Effect Transistor and also mention types of FET s.

UNIT-VI FIELD EFFECT TRANSISTOR. 1. Explain about the Field Effect Transistor and also mention types of FET s. UNIT-I FIELD EFFECT TRANSISTOR 1. Explain about the Field Effect Transistor and also mention types of FET s. The Field Effect Transistor, or simply FET however, uses the voltage that is applied to their

More information

CHARACTERIZATION OF OP-AMP

CHARACTERIZATION OF OP-AMP EXPERIMENT 4 CHARACTERIZATION OF OP-AMP OBJECTIVES 1. To sketch and briefly explain an operational amplifier circuit symbol and identify all terminals. 2. To list the amplifier stages in a typical op-amp

More information

Field-Effect Transistor (FET) is one of the two major transistors; FET derives its name from its working mechanism;

Field-Effect Transistor (FET) is one of the two major transistors; FET derives its name from its working mechanism; Chapter 3 Field-Effect Transistors (FETs) 3.1 Introduction Field-Effect Transistor (FET) is one of the two major transistors; FET derives its name from its working mechanism; The concept has been known

More information

Supporting Information for Gbps terahertz external. modulator based on a composite metamaterial with a. double-channel heterostructure

Supporting Information for Gbps terahertz external. modulator based on a composite metamaterial with a. double-channel heterostructure Supporting Information for Gbps terahertz external modulator based on a composite metamaterial with a double-channel heterostructure Yaxin Zhang, Shen Qiao*, Shixiong Liang, Zhenhua Wu, Ziqiang Yang*,

More information

TRANSISTOR TRANSISTOR

TRANSISTOR TRANSISTOR It is made up of semiconductor material such as Si and Ge. Usually, it comprises of three terminals namely, base, emitter and collector for providing connection to the external circuit. Today, some transistors

More information

Semiconductor Physics and Devices

Semiconductor Physics and Devices Metal-Semiconductor and Semiconductor Heterojunctions The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is one of two major types of transistors. The MOSFET is used in digital circuit, because

More information