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1 Tunability of 1/f noise at multiple Dirac cones in hbn encapsulated graphene devices Chandan Kumar,, Manabendra Kuiri,, Jeil Jung, Tanmoy Das, and Anindya Das, Department of Physics, Indian Institute of Science, Bangalore , India, and Department of Physics, University of Seoul, Seoul , Korea FABRICATION DETAILS AND DEVICE CHARACTERIZATION: The hbn-graphene-hbn heterostructure was obtained using following steps. First hbn sheets (obtained from HQ Graphene) were mechanically exfoliated on highly p doped Si wafer with 300 nm oxide thickness, with a resistivity of Ohm-cm obtained from Nova wafers. Using dry transfer technique, 1 graphene flakes were then transferred on hbn (sitting on top of SiO 2 ). Secondly the electrical contacts were fabricated using standard electron beam lithography (EBL). The metal leads (5nm Cr/ 70 nm Au) were deposited using thermal evaporator at a base pressure of mbar. Next to put the top gate, thin hbn layer (which was mechanically exfoliated) was precisely aligned with already prepared Graphene-hBN heterostructure and transferred using the same technique discussed above. The prepared heterostructure was annealed at 300 C to have moire pattern. 2 Finally using EBL the top gate contacts was fabricated by depositing 5 nm/70 nm of Cr/Al. To whom correspondence should be addressed Department of Physics, Indian Institute of Science, Bangalore , India Department of Physics, University of Seoul, Seoul , Korea Contributed equally to this work 1
2 a) b) Figure 1: (Color Online) (a) Raman spectra of SLG1 and (b) BLG Figure 1 shows the raman spectra of SLG1 (a) and the BLG (b) measured on hbn substrate. The spectra is taken at room temperature with nm laser light. MOBILITY AND δn EXTRACTION: a) hbn-slg1-hbn Figure 2 (a) and (b) shows the conductance as a function of density, varied by the top gate at cloned Dirac (CD) and the primary Dirac (PD) respectively. Blue line is a linear fit to the data which gives the charge inhomogeneity (δn) to be cm 2, which has been shown by the shaded region. Figure 2 (c) and (d) shows the Resistance as a function of top gate voltage at the CD and the PD, respectively. As discussed in the main text the total resistance R T can be written as R T = R ch + R L where R ch is the channel resistance under the top gate and R L is the 2
3 a) b) Conductance ( µs) Conductance ( µs) n ( x /cm 2 ) n ( x /cm 2 ) c) d) Resistance ( κω) Resistance ( κω) Figure 2: (Color Online) Conductance as a function of density for (a) cloned Dirac (b) primary Dirac of SLG1 device. Blue line is a linear line fit to the curve. The shaded yellow region gives the charge inhomogeneity. Resistance as a function of top gate voltage for (c) cloned Dirac (d) primary Dirac. Blue line is a fit to the curves using equation (1). Measurement is performed at 4.2 K resistance coming from the lead (untopgated part with contacts) The R T V T G curve, of figure 2 (c) and 2 (d) is fitted with the following equation as mentioned in the manuscript. L T G R T = R L + weµ δn 2 + n 2 ch (1) From fitting we obtain mobility of 9000 and cm 2 V 1 s 1 at PD and CD, respectively. The dimension of our SLG1 device are L T G = 1.25 µm and w = 2.1 µm. 3
4 b) hbn-blg-hbn Figure 3 (a) shows the conductance as a function of density of BLG and the blue line is a linear fit near zero density, which gives charge inhomogeneity to be cm 2. a) b) Conductance ( µs) 71 Resistance ( κ Ω ) n ( x /cm 2 ) Figure 3: (Color Online) For BLG device, (a) Conductance as a function of density. Blue line is a linear fit, which gives charge inhomogeneity (shaded) yellow region. (b) Resistance verses top gate voltage at V BG =0 V. Blue line shows the linear fit with equation (1). Measurement is performed at 4.2 K Figure 3 (b) shows resistance with V T G at V BG =0 V. We see that the curve is not symmetric around zero density due to the formation of p-n junction as reported earlier, 3 hence to calculate the mobility of the device, curve is fitted with equation (1) only for negative gate voltage, which gives a mobility of cm 2 V 1 s 1. The dimension of our device is L T G = 0.5 µm and w = 2 µm. c) hbn-slg2-hbn Figure 4 (a) shows conductance as a function of density, from which we calculate the charge inhomogeneity cm 2. Figure 4 (b) shows resistance as a function of top gate voltage. Fitting the curve with equation (1) gives mobility cm 2 V 1 s 1, where L T G = 1.8 µm and w = 2 µm. 4
5 s Conductance ( µs) n ( x /cm 2 ) Resistance ( k Ω) Figure 4: (Color Online) (a) Conductance as a function of density for SLG2 device. Blue line is a linear fit. The charge inhomogeneity is given by shaded yellow region. (b) Resistance as a function of top gate voltage. Blue line is fit to the curve using equation (1). Measurement is performed at 77 K. 1/f NOISE MEASUREMENTS: The Power spectral density of SLG1 and BLG were measured using using ac lock in technique. The schematic of noise measurement technique is shown in figure 5. The sample was voltage biased (100 µv) and the current fluctuation is measured with lock in amplifier using NI 6210 DAQ card. Before the signal is fed to lock (SR 830), it is amplified by a home build V ac Top hbn S Current Amplifier Graphene D bottom hbn bottom hbn SiO 2 Si Lock in Amplifier NI DAQ Card DSP V BG Power Spectral Density Figure 5: (Color Online) Schematic of the noise measurement technique. current amplifier which has gain of 10 7 with input impedence 100 Ohm. The noise figures are v n 6nV/ Hz and current noise, i n 50fA/ Hz at 10 Hz. In our measurements 5
6 the sampling rate is kept at Hz and decimated by a factor of 128, which gives the effective sampling rate of 256 Hz. The lock in time constant is kept at 1 ms with roll off of 24dB/octave and the data is recorded for 30 minutes. Next, the data is digitally anti-aliased, down sampled and the PSD was calculated using Welch s periodogram method. The main advantage of the lock in technique is the simultaneous measurement of the signal and the background. 4 Channel X of lock in gives the signal plus background and the Y channel gives background only. Hence the PSD of the signal is obtained by subtracting the Y component from the X component. (a) Background Noise To benchmark the noise measurement technique, we measure the power spectral density (PSD) of a noiseless 10 kohm metal resistor in our dip-stick, which is shown in figure 6. As can be seen from figure 6 that both X and Y channel of the lock-in measures the background noise which remains almost flat from 0.1 to 100 Hz. The measured background noise is A 2 /Hz. At low temperature the main source of background noise comes from the voltage noise of the amplifier [ i 2 n = ( vn R )2 ], which is A 2 /Hz from a 10 kohm resistor with v n 6 nv/hz. The value of the background noise depends on the resistance of the sample. For low resistance sample (0.1 to 2 kohm) i 2 n becomes large. Hence the noise of SLG2 is measured by voltage amplifier in a 4 probe geometry. We use the SR552 voltage amplifier with voltage noise of 2.1 nv/ Hz and input impedence of 100 kohm. (b) Noise amplitude and noise spectral density The noise amplitude ( A ) is calculated as 5 A = 1 N N f m S Im /Im 2 (2) m=1 where I m is the source drain current, S Im is the noise spectral density and f m are the frequencies over which noise amplitude is averaged. 6
7 Lock in X channel Lock in Y channel S I (A 2 /Hz) Frequency (Hz) Figure 6: (Color Online) Noise spectral density as a function of frequency for 20 kω resistor at 77 K. a) b) BackGround 1/f noise PD S I (A 2 /Hz) β = 1 β CD Frequency (Hz) Figure 7: (Color Online) (a) Noise spectral density of BLG as a function of frequency at V T G = 1.5 V and V BG = 25 V. (b) Value of β at PD cone and the CD cone of SLG1. Figure 7 (a) shows the typical noise spectral density of the BLG device. It can be seen that the background noise is much smaller compared to 1/f noise of the device. In our measurement, noise remains as 1/f nature with β = 1 even upto 100 Hz. This is further confirmed by looking at β close to PD and CD of SLG1 (figure 7 (b)). 7
8 (c) 2D noise in bipolar regime We have two different region in our device- one controlled only by back gate (region 1) where density, n BG = C BGV BG e and other which is controlled by both back gate and top gate (region 2), where density n T G = C T GV T G +C BG V BG. Here C e BG and C T G are the back gate and top gate capacitance respectively. Different combination of back gate and top gate voltages will lead to the formation of unipolar (n-n*-n or p-p*-p) and bipolar (n-p-n or p-n-p) region. The schematic of the generated potential, V in unipolar and bipolar regime is shown in figure 8 (a) and 8 (b) respectively. Since graphene has a linear dispersion relation E = hv F πn and all the energies are measured with respect to the Dirac point, the generated potential is given by the difference of energy in region 1 and 2 as shown schematically in figure 8. a) b) p p* p p n p E F V E F V Figure 8: (Color Online) (a) Schematic of potential generated in (a) unipolar and (b) bipolar regime. The potential generated is given by ) CBG V BG CT G V T G + C BG V BG V = hv F π (sgn(c BG V BG ) sgn(c T G V T G + C BG V BG ) e e Figure 9 (a) shows the 2D plot of noise amplitude A as a function of V BG and V T G for SLG2 at 77 K in linear scale. The generated potential is shown in figure 9 (b). 8
9 V BG A (x 10 7 ) V BG ( V ) n-p-n p-p*-p n-n*-n p-n-p ( V ) V ( mev ) Figure 9: (Color Online) (a) Noise Amplitude as a function of V BG and V T G for SLG2 device measured at 77 K. (b) Potential generated in unipolar and bipolar region. References phkh (1) Zomer, P.; Dash, S.; Tombros, N.; Van Wees, B. Applied Physics Letters 2011, 99, (2) Wang, L.; Gao, Y.; Wen, B.; Han, Z.; Taniguchi, T.; Watanabe, K.; Koshino, M.; Hone, J.; Dean, C. R. arxiv preprint arxiv: , (3) Özyilmaz, B.; Jarillo-Herrero, P.; Efetov, D.; Abanin, D. A.; Levitov, L. S.; Kim, P. Physical review letters 2007, 99, (4) Ghosh, A.; Kar, S.; Bid, A.; Raychaudhuri, A. arxiv preprint cond-mat/ , (5) Balandin, A. A. Nature nanotechnology 2013, 8,
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