VIRTUS 32 Research Report 2014

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1 VIRTUS

2 Research Facilities and Capabilities Since its inception five years ago, VIRTUS set out to provide a strong foundation in leading-edge research and educational environments for the design of efficient integrated circuits and systems. We aim to support the increasingly large demand from Singapore electronics industry, foster innovation, entrepreneurial spirit and culture among engineers in Singapore, and ultimately demonstrate significant contributions to Singapore s future economy. With this goal in mind, we will focus on major design challenges for future cutting-edge energy-efficient ICs and systems on chips. Such advanced but low-cost and affordable systems will be the key enablers for a host of emerging technologies in various application areas such as healthcare, safety/security, energy production, automotive, mobile communication, robotic, entertainment, smart homes, industry automation and control, and will centre heavily on the Internet of Things (IoT). A multi-disciplinary research environment with a broad spectrum of knowledge and skills to develop innovative circuit techniques and system solutions will be required. This will allow for low-power low-cost integration of analog, mixed analog/digital and radio frequency circuits, combined with advanced digital signal processors and various types of sensors and sensor networks, like those that are needed for remote wireless sensor nodes (WSN). VIRTUS has skillful and experienced faculty members, researchers and graduate research students, professional management and administration, as well as a strong network with major semiconductor companies in Singapore and beyond. In this context, we warmly welcome new industry or university partners for long-term and effective research collaborations. The Centre is well equipped with state-of-the-art equipment and laboratories. High-end PCs are networked to share a wide range of Linux-based and Window-based EDA tools, e.g. Cadence, Mentor Graphics, Synopsys, Agilent, Ansys for the design and analysis of devices, circuits and systems. General test and measurement equipment such as digitising scopes, function generators, signal generators, and spectrum analysers, are also facilitated in the Centre. VIRTUS houses a High Frequency Characterisation Room that is equipped with a 12 Probe System and an Integrated Characterisation and Analysis System to facilitate on-wafer S- parameter RF/mm-wave device characterisation from DC to 325-GHz, high frequency noise measurement from 0.3-MHz to 67-GHz and flicker noise measurement up to 40-MHz. VIRTUS 35

3 Highlight of Research CMOS Opto-chemical Sensor Towards Highthroughput and Accurate DNA 1 Sequencing A dual-mode CMOS ISFET (ion-sensitive field-effect transistor) based sensor chip prototyped by Asst Prof Yu Hao s group towards highthroughput and accurate DNA sequencing can perform both optical imaging and chemical (ph) sensing capabilities that can accurately determine micro-bead location with correlated ph value reporting. This has solved the long-standing challenge in the existing DNA sequencing equipment (by IonTorrent-Life Technologies and Illumina), which has low accuracy to determine the micro-bead distribution during DNA sequencing. By integrating CMOS image sensor with microfluidics, the biological samples of interest such as tissues, cells, bacteria, or DNA strands can have a fluidic environment to be in contact with the image sensor array directly, thus making it possible for the conventional bulky microscopy based imaging to be replaced by the on-chip contact imaging. The chemical reactions that cause ion changes in the solution can also be detected by the CMOS image sensor integrated with ISFET. As such, 10x accuracy improvement can be observed with 100x speedup by the proposed dual-mode CMOS ISFET sensor. This project was sponsored by NRF-POC 12 project (S$245,000) with TSMC sponsored tapeout shuttle (S$650,000). Such a large-arrayed (1K-1M) CMOS opto-chemical sensor system can have various applications in DNA sequencing and food safety detection. 36 Research Report 2014

4 2 Direct device-to-device (D2D) for Future Communication 3 Low Power SRAM for High Temperature Applications Up To 300 C In close collaboration with Massachusetts Institute of Technology (MIT), Assoc Prof Boon Chirn Chye and his team members Dr Pilsoon Choi and Mao Mengda demonstrated a fully integrated Receiver+Transmitter+Switch Frontend for Direct device-to-device (D2D) and Dedicated Short Range Communication (DSRC). This is the first single-chip GaN RF frontend compliant with the IEEE p standard for future D2D communications. When Samsung S4 was released in 2013, its WiFi Direct D2D interface (GroupPlay) was heavily marketed as a new feature, showcasing its ability to enable audio sharing between phones in the vicinity. Within a few months, video sharing, file sharing as well as multi-player games have been released by leveraging on GroupPlay. Existing D2D communications like Samsung S4 s GroupPlay are only suited for short-range, low mobility scenarios. In our research, we demonstrate the feasibility of realizing p on phones. We see this opening up D2D communications to a much larger class of applications. With mobile devices on pedestrians, passengers are now interconnected at low latency and high bandwidth, thus enabling highly interactive mobile applications on-the-go. Also, existing WiFi Direct applications such as video sharing and multi-player gaming are now realised outdoors on pervasive smart phones. Dedicated Short Range Communication (DSRC) based on IEEE p standard is an emerging technology for vehicular communications to implement such virtual toll system. To mitigate multipath and highly mobile channel environments between cars, IEEE p specifies a double guard interval and a half guard band along with higher output power when compared with the IEEE a standard. It results in a maximum 27Mbps data rate in 10MHz bandwidth at 5.85~5.925GHz carrier frequency band with 28.8dBm maximum output power. This finding was published in the IEEE publication and a US patent has been filed. The development of ruggedised electronics such as automotive, aerospace and Logging-While-Drilling (LWD) systems has demanded more robust integrated circuit solutions with reliable operation at high temperatures (>200 C). One of the most challenging issues in circuit design for high temperature operation is leakage, which increases exponentially with temperature. Silicon-on-Insulator (SOI) technology has been preferred for high temperature applications due to the feature of lower leakage compared with bulk CMOS technology. Even though leakage is improved dramatically by the SOI technology, it still becomes substantial at the temperature of 300 C. In addition, special process technologies such as Silicon Carbide (SiC) CMOS and interconnect material of Tungsten have also been employed to enhance the reliability of the devices and interconnections at high temperatures. We have recently developed an 8-Kbit low power SRAM for high temperature (up to 300 C) applications. For a low and reliable voltage operation, we have employed a decoupled 8T SRAM cell structure. To minimise the performance variations caused by the wide operating temperate range, supply voltage is selected in the near-threshold region, and a temperature-aware bitline sensing margin enhancement technique is also proposed for mitigating the impact of significantly increased bitline leakage on bitline swing and sensing window. A temperature-tracking control circuit generates bias voltage for optimal pull-up current to realise the proposed enhancement technique. Test chips were also fabricated in a commercial 5 V, 1.0-μm SOI technology, and the measurement demonstrates successful operation down to 2 V at 300 C. The average energy of 0.94 pj was achieved at 2 V and 300 C. VIRTUS 37

5 4 Anti-VibrationTime Delay Integration Smart Image Sensor for Remote Sensing 5 Advanced Radar System on Chip Time delay integration (TDI) image sensors are widely applied in satellite imaging, military reconnaissance, document scanning and industrial conveyer belt inspection systems. In a TDI image sensor, several stages of pixels are placed in the across-track direction, and the panoramic image in the along-track direction is accompanied by the movement of the sensor. Superior to single line scanning sensors, TDI image sensors contain more than one row of pixels and are exposed to the same target many times. This enables an extension of the optical integration time, and significantly improves signal strength. However, conventional TDI image sensors can only work under the condition of having a stable direction of the object movement relative to the sensor with perfect alignment to the charge or signal accumulation on the sensor. They will produce blurred images in small remote imaging systems such as satellites and unmanned aerial vehicles (UAV), where camera movement is unstable and image restoration systems or vibration control systems are unavailable. Asst Prof Chen Shoushun s team developed a smart anti-vibration TDI image sensor equipped with a mixed analog-digital signal online, deblurring algorithm which can effectively remove the signal mixture due to crosstracker vibration and achieve improved image contrast. A prototype sensor with 8 stage 256 columns pixels was fabricated using a 0.18um CMOS process. The measurement result shows that the sensor can work under random vibrations and improves the signal-to-noise ratio of 1.9dB per TDI stage. This technology will also have great potential for usage in unmanned aerial vehicle cameras. Asst Prof Zheng Yuanjin s team, has developed a first-in-kind fully integrated Ku band Radar System on Chip. It can be widely used for precise ranging and localisation, as well as for high resolution synthetic aperture radar (SAR) imaging in civil and defense applications. By leveraging on the advanced radar system and sub-micron CMOS integrated circuit technology, the first generation of the radar chip has been implemented and attains up to 3GHz chip bandwidth with 5cm range resolution. The radar chip achieves significant size, weight and power (SWaP) reduction (size of 2.9mmX1.4mm, weight of 1g and power of 240mW) as compared to conventional radar transceiver systems. This development allows for use in micro-satellite and intelligent unmanned autonomous systems (such as UAV/UGV/USV), and has great impact on potential applications in remote sensing, urban logistics and traffics mapping, weather monitoring, security and defense, and automotive surveillance. The project is funded by DRTech and has garnered much attention from MNCs and institutes. 38 Research Report 2014