Extreme Delay Sensitivity and the Worst-Case. Farid N. Najm and Michael Y. Zhang. Urbana, IL 61801

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1 Extreme Dela Sensitivit and the Worst-Case Switching Activit in VLSI Circuits Farid N. Najm and Michael Y. Zhang ECE Dept. and Coordinated Science Lab. Universit of Illinois at Urbana-Champaign Urbana, IL 68 Abstract { We observe that the switching activit at a circuit node, also called the transition densit, can be extremel sensitive to the circuit internal delas. As a result, slight dela variations can lead to several orders of magnitude changes in the node activit. This has important implications for CAD in that, if the transition densit is estimated b simulation, then minor inaccuracies in the timing models can lead to ver large errors in the estimated activit. As a solution, we propose an ef- cient technique for estimating an upper bound on the transition densit atever node. While it is not alwas ver tight, the upper bound is robust, in the sense that it is valid irrespective of dela variations and modeling errors. We will describe the technique and present experimental results based on a prototpe implementation. I. INTRODUCTION Higher levels of integration and shrinking line widths have led to a generation of devices that have more severe power dissipation and reliabilit problems than tpical devices of a few ears ago. Excessive power dissipation ma cause run-time errors and device destruction due to overheating, while reliabilit issues ma shorten device lifespan. It is especiall useful to diagnose and correct these problems before circuits are fabricated. In the popular CMOS technolog, logic gates draw current and consume power onl when making logical transitions. As a result, power dissipation and reliabilit strongl depend on the extent of circuit switching activit. This work was supported in part b the National Science Foundation (NSF), under grant MIP-986. Circuit activit is dependent on the input patterns being applied to the circuit. For one input set the circuit ma experience no transitions, while for another it ma switch ver frequentl. During the rst input set the circuit dissipates little power and experiences little wear, but for the second its activit might cause device failure. Thus one is tempted to simulate the circuit for all possible inputs in order to measure the activit, which is highl impractical for VLSI. Recentl, some approaches have been proposed to solve this problem b using probabilities to represent tpical behavior at the circuit inputs. In [], the average number of transitions per second at a circuit node is proposed as a measure of switching activit, called the transition densit. An algorithm was also proposed to propagate specied input transition densities into the circuit to compute the densities at all the nodes. Other approaches, such as [] and [], have also been proposed to overcome the pattern dependence problem and estimate the transition densit. However, in addition to being input pattern dependent, the transition densit at a node also depends on the path delas inside the circuit. Thus, due to dierent path delas, a node in a clocked snchronous circuit ma make several transitions before settling down to its stead state value in a clock period. Indeed, as we will illustrate in the next section, the transition densit atanodecanbe extremel sensitive to the circuit internal delas. As a result, slight dela variations (due, sa, to imperfections in the manufacturing process) can lead to several orders of magnitude changes in the switching activit. Furthermore, if the transition densit is estimated b simulation, such as in [], then minor inaccuracies in the dela models can lead to large errors in the estimated activit. Likewise, both approaches [] and [] can develop accurac problems resulting from extreme sensitivit. In [], the circuit delas are not explicitl taken into account, so the error due to dela sensitivit becomes part of the overall approximation error of the technique. In [], the smbolic expressions representing the probabilit of switching depend explicitl on the circuit delas and will, therefore, have accurac problems due to dela sensitivit. To address this problem, we propose a method of estimating an upper bound on the transition densit of individual nodes within a combinational circuit (assumed to be embedded in a larger sequential circuit). The upper bound provides an estimate of the maximum transition densit at ACM/IEEE Design Automation Conference, 995.

2 a node, and is based on user-specied min-max dela intervals for each logic gate. This estimate is robust, in the sense that it is valid irrespective of dela variations and timing model inaccuracies (within the specied dela intervals). The technique uses signal uncertaint to capture the worst case behavior of the circuit. It has been implemented in a prototpe simulator, called MaDest (Maximum Densit Estimator). The rest of this paper is organized as follows. In the next section, the notion of extreme sensitivit is illustrated in more detail. Section III contains a detailed description of the upper bound computation algorithm, and experimental results are presented in section IV. Finall, a summar and conclusion are presented in section V. II. EXTREME SENSITIVITY We will illustrate the extreme sensitivit phenomenon with the help of the two circuits in Figs. and. The circuit in Fig. (Circuit A) was simulated using [] to compute the transition densit at ever node to within %, with 95% condence. All inputs were assigned a (normalized) transition densit of :5 and a probabilit of :5. This means that, on average, a primar input makes a transition ever other clock ccle, and spends half the time in the logic state. Another circuit, shown in Fig. (Circuit B) was obtained from circuit A b simpl removing the NOR gate q. This circuit was then also simulated using [] under the same conditions. As far as the output node is concerned, the onl dierence between the two circuits is the slight change in the dela of the path (,, ) due to the reduced capacitive loading when the NOR gate is removed. This slight change in one of the path delas causes the transition densit at the output node to var b a factor of :8=:5 = 76, almost three orders of magnitude, between the two circuits. Thus node is said to be extremel sensitive a d b Figure. Circuit A - node has ver low transition densit. i j o p q (D=.5) The implication for CAD is profound: if the transition densit is estimated b simulation, then minor inaccuracies in the simulation models can lead to large errors in the estimated activit. Even if circuit simulation were used to estimate switching activit, which would be prohibitivel expensive, extreme sensitivit ma still be a problem. This is because slight dela variations due to imperfections in the manufacturing process ma still lead to order of magnitude changes in the switching activit. To overcome this problem, we will propose in the next section an ecient technique for computing an upper bound on the transition densit that is valid irrespective of dela variations or modeling errors. Using this technique, the user is alerted to the possibilit of having ver high transition densit at some nodes. More detailed analsis can then be carried out on these nodes, and corrective design measures can be implemented. Before going on, however, we will make some observations regarding the cause of the extreme sensitivit. 7 6 a d b Figure. Circuit B - node has much higher transition densit. i j o p (D=.8) Circuits A and B are not unique. Indeed it turns out that a necessar condition for a node to be extremel sensitive is that it be located where two or more reconvergent paths meet, provided the paths have delas that dier b a small amount, approximatel equal to the inertial dela of the gate. Slight dela variations can then have a large impact on the transition count, because if the dierence in path delas becomes less than the inertial dela, events will cancel out and few output events will be generated. Otherwise, if the dierence in path delas is larger than the inertial dela, then multiple events ma be generated at the gate output. This condition is not sucient, however, for extreme sensitivit. The signal values and the Boolean properties of the paths pla an additional ke role in determining extreme sensitivit. For instance, two competing events at the inputs of an AND gate must be complementar, otherwise a single event will be generated irrespective of the delas. Based on this necessar condition, we have implemented a simple pre-processor that examines the circuit topolog and ags a node as potentiall extremel sensitive if it satises the necessar condition. The results indicate that a low percentage of nodes are potentiall extremel sensitive (.% for the ISCAS-85 benchmarks). Although this is a small fraction of nodes, one cannot ignore this problem because if one of these nodes is close to the primar inputs, then its densit value will aect all other nodes downstream from it, leading to large variations in the estimated circuit activit. -/5-

3 III. UPPER BOUND COMPUTATION We assume that the circuit to be analzed is a combinational block that is part of a larger snchronous sequential design, as shown in Fig.. The primar inputs to the circuit (combinational block) switch in snchron with the clock, if at all, and can make at most one transition per clock ccle. Other circuit nodes, however, can make multiple transitions per clock ccle. Let n x() denote the number of transitions at node x in one clock ccle.for a given node, the average (or expected) number of transitions per clock ccle, divided b the clock period, is the transition densit for that node [] : x x x x n D(x) = E[nx()] If ^n x() is the maximum possible number of transitions per clock ccle at node x, then ^n x()= is the maximum transition densit, so that: Input Latches D(x) ^nx() x x x x n Combinational Logic Block m Output Latches m No. t t t t t5 t6 t7 Figure. Signal uncertaint representation. The vertical axis gives the maximum number of transitions (integer valued) that a node can possibl experience in specied time intervals. Thus the waveform in Fig. indicates that this node makes at most transition between t and t, at most transitions between t and t, at most transitions between t and t 5, at most transition between t 6 and t 7, and no transitions at an other time within the clock period. Once such a waveform is available for ever circuit node, then adding the transition count associated with each interval gives the required upper bound at that node, U[n x()]. We derive the signal uncertaint waveform associated with each circuit node b propagating user-specied uncertaint waveforms from the primar inputs throughout the circuit. A primar input node can have at most one transition. Thus the corresponding waveform consists of a single interval in which the transition count is. Ideall, this interval consists of the single time point t =. However, in order to allow for clock skew or dela variations, we use a more general model in which this interval is specied as [;t] where t is under user control (or a program default), as shown in Fig. 5. Figure. A combinational circuit embedded in a snchronous sequential design. We propose a method of computing an upper bound on ^n x() that is independent of the sensitivities and dela variations. We denote this upper bound b U[n x()]. Eectivel, this leads to an upper bound on the transition densit : D(x) U[nx()] Ideall, wewould like U[n x()] to be equal to ^n x(). However, in order to maintain computational ecienc, we can not guarantee this and, in general, the will not be equal. A. Signal uncertaint representation We will represent the variet of possible waveforms at a circuit node with a single waveform that helps describe our uncertaint about the behavior of the real signal. An example of this representation is given in Fig.. t Figure 5. The signal uncertaint representation for a primar input node. B. The propagation algorithm and heuristic The propagation algorithm visits ever gate in the circuit onl once, starting at the primar inputs, and processes a gate onl when all its fan-in gates have been processed. It is assumed that the gate delas are not known exactl, but are onl known to be within user-specied intervals [t d;min;t d;max]. This allows for dela variations due to process variations, temperature, drift, and timing model inaccuracies. The dela limits, which ma be dierent for dierent gate tpes, are scaled b the fanout capacitance seen b the gate. -/5-

4 When processing a gate, the uncertaint waveforms at its inputs are examined, and a corresponding uncertaint waveform is generated at its output. Since the logic values and specic transition times at the gate inputs are not known, the onl wa toguarantee an upper bound on the output transition count is to assume that ever input transition goes through. In this case, the output transition count of a gate is simpl the sum of all its inputs' transition counts. To illustrate, consider an AND gate with inputs A and B, and output C, for which the input and output uncertaint waveforms are shown in Fig. 6. Notice that the time interval at the output node is expanded to allow for maximum and minimum propagation delas. A t B t not a transition propagates through a gate depends on the signals at the other gate inputs. Among logic gates, onl the exclusive-or (XOR) gate has no controlling input value, and thus allows more transitions to go through. All other gate tpes (NAND, AND, NOR, and OR) will block some transitions when one of their inputs is at a controlling value ( for AND and NAND, for NOR and OR). To represent this fact, it seems reasonable to compute the maximum transition count for a logic gate (other than XOR) as some fraction of the sum of its input transitions, rather than the whole sum. We have found that a fraction of / works well in practice. To see wh this factor is plausible, consider that, for a -input XOR gate, there are combinations of input transitions that produce an output transition, as illustrated b the solid lines in Fig. 7a. In contrast, onl combinations of input transitions produce an output transition in the case of an AND gate, as shown in Fig. 7b. Hence the / factor. XOR gate (, ) (, ) AND gate (, ) (, ) C t t min. dela t max. dela t Figure 6. Input and output transition characteristics. It should be clear that this simple propagation procedure is ver fast, but can lead to loose upper bounds. While this is true in general, we have found that b using two modications to the basic technique, we can achieve reasonable accurac without impairing the speed advantage of the approach. The rst modication has to do with the fact that logic gates have non-zero inertial dela. Thus the output of a logic gate cannot carr arbitraril short pulses. A pulse has to be at least as long as the inertial dela ifit is to be transmitted. Therefore, ever output node has a minimum pulse width that puts a ceiling on the number of transitions that it can have within each sub-interval. The second modication is a heuristic that we have found works well in practice, as shown in section IV, and which tries to account for the other gate inputs. One reason that the upper bound can be loose is that whether or (, ) (, ) (, ) (, ) (a) (b) Figure 7. Transition diagrams for (a) an XOR gate and (b) an AND gate. Similar analsis ields the same / factor for ever other gate tpe (other than XOR) and for an number of inputs. The experimental data presented in the next section demonstrate that this works well in practice. IV. EXPERIMENTAL RESULTS The proposed technique has been implemented in the prototpe program MaDest. The program uses a simplied gate timing model in which librar-specied propagation delas are scaled b the external capacitive loading. The gate librar also species min-max dela intervals for ever gate. We will present results for the ISCAS-85 benchmark circuits [] (after mapping to the gate librar). In order to stud the accurac, one needs the true \maximum number of transitions per clock ccle" at ever node, allowing for timing model inaccuracies, process and dela variations, clock skew, etc. Finding this would be extremel computationall expensive. Instead, we will compare the upper bound densities to the maximum observed densities obtained from ver long logic simulations, using []. It should be clear that the true maximum should be at least as high as that observed from an simulation run. Thus the maximum observed densities measured from simulation are actuall lower bounds on the true maximum. As a result, all accurac comparisons will be made between the upper bounds produced b MaDest and the lower bounds obtained from simulation. Thus the error measurements presented below will be worst case, i.e., upper -/5-

5 bounds on the true errors. We will use the following error measures to stud the accurac, where n x() is the number of transitions at node x in one clock ccle, U[n x()] is the computed upper bound, L[n x()] is the lower bound obtained from [], and N is the total number of nodes in the circuit: the execution time (SUN Sparc ELC workstation) was under / second for an one ISCAS-85 circuit. The largest circuit took onl. cpu seconds.. Relative Error(n x)= =Average Relative Error = N Table I. U[nx()], L[nx()] L[n x()] NX x= AVERAGE RELATIVE ERROR FOR THE ISCAS-85 BENCHMARK CIRCUITS. Relative Error(n x) Number of Nodes Circuits #levels #gates h c % 7.% c99 6.7%.% c %.7% c % 57.8% c %.6% c % 6.7% c % 6.% c % 6.% c %.% c % 9.% The average relative errors observed for the ISCAS-85 circuits are shown in Table I, both with ( h) and without () the heuristic. The heuristic works well and leads to considerable improvement in the upper bound. On average, the densit results are overestimated b a factor of about.5. To investigate this further, consider the histogram of the relative errors at all the nodes in c, shown in Fig. 8. While most nodes have low error values, the errors for a few of the nodes is quite high. Undoubtedl, this is due in part to the approximations that have been used, and suggests that one should tr to do better. However, in some cases the high error is simpl a result of the node sensitivities. For instance, we have veried that the three nodes with the largest error values in Fig. 8 are potentiall extremel sensitive - the satisf the necessar condition of section II. Similar trends were observed in other circuits: nodes that are potentiall extremel sensitive tpicall exhibit large relative errors. Thus, while it is not alwas so, in man cases the \error" observed is not so much an accurac problem as it is simpl an indication of the presence of extremel sensitivit nodes. It should be clear that the approach isver fast, and has a time complexit that is linear in circuit size. Indeed, Relative Error Figure 8. c transition densit relative error histogram with the heuristic. VI. SUMMARY AND CONCLUSION The average number of transitions per second at a circuit node is a measure of switching activit called the transition densit. Wehave observed that in some cases, the transition densit at a node can be extremel sensitive to the circuit internal delas. As a result, dela variations due to process imperfections can lead to order of magnitude changes in the switching activit. Furthermore, if the transition densit is estimated b simulation, then minor inaccuracies in the dela models can lead to large errors in the estimated activit. As a solution, we have proposed an ecient technique for estimating an upper bound on the transition densit at ever node. The upper bound is robust, in the sense that it is valid irrespective of dela variations. Experimental results demonstrate that the technique is fast, and that a simple heuristic can be used to signicantl improve the tightness of the bound. REFERENCES [] F. Najm, \Transition densit: A new measure of activit in digital circuits," IEEE Transactions on Computer-Aided Design, pp. {, Feb. 99. [] A. Ghosh, S. Devadas, K. Keutzer, and J. White, \Estimation of average switching activit in combinational and sequential circuits," 9th ACM/IEEE Design Automation Conference, pp. 5{59, June 8{, 99. [] M. Xakellis and F. Najm, \Statistical Estimation of the Switching Activit in Digital Circuits," st ACM/IEEE Design Automation Conference, pp. 78{7, 99. [] F. Brglez, P. Pownall, and R. Hum, \Accelerated ATPG and fault grading via testabilit analsis," IEEE International Smposium on Circuits and Sstems, pp. 695{698, June /5-