TrACS: Transceiver Architecture and Wireless Channel Simulator

Transcription

1 TrACS: Traneiver Arhiteture and Wirele Channel Simulator Chithrupa Rameh Student Doent, ECS/RAMSIS Profeor, ECS/RAMSIS Profeor, EE/Comm Theory Royal Intitute of TehnologyRoyal Intitute of TehnologyRoyal Intitute of TehnologyRoyal Intitute of Tehnology Stokholm, Sweden Stokholm, Sweden Stokholm, Sweden Stokholm, Sweden rameh@kth.e Ana Ruu ana@imit.kth.e Mohammed Imail imail@imit.kth.e Mikael Skoglund koglund@ee.kth.e ABSTRACT Thi paper preent the deign of a ytem-level imulator for radio reeiver, inluding reeiver iruit, in Matlab. The ytem level outlook offer a better haraterization of iruit deign, a the ignal proeing in the digital reeiver i aymmetri aro topologie. Alo, iruit model in the imulator make it more preie and realiti ompared to baeband model, whih aume a ingle-tep error-free down onverion. Thi interpretation i epeially relevant in the deign of energy-ontrained wirele enor network olution. The imulator reult for binary FSK in AWGN onfirm the importane of ytem level imulation. Categorie and Subjet Deriptor B.4.4 [Input/Output and Data Communiation]: Performane Analyi and Deign Aid Formal model, Simulation, Verifiation. B.7. [Integrated Ciruit]: Deign Aid Verifiation. General Term Performane, Deign, Theory, Verifiation. Keyword Wirele enor node deign, reeiver, imulator, traneiver iruit, ytem-level deign and performane verifiation. 1. INTRODUCTION Wirele enor node deign ha beome ynonymou with energy- ontrained olution, a energy in the enor node i a are reoure. The emphai on low power deign extend to both the iruit and the ignal proeing in the reeiver of the enor node [14]. Low power iruit deign i an ative area of reearh, with a few iruit arhiteture well identified for their Permiion to make digital or hard opie of all or part of thi work for peronal or laroom ue i granted without fee provided that opie are not made or ditributed for profit or ommerial advantage and that opie bear thi notie and the full itation on the firt page. To opy otherwie, or republih, to pot on erver or to reditribute to lit, require prior peifi permiion and/or a fee. SBCCI 07, September 3 6, 007, Rio de Janeiro, Brazil. Copyright 007 ACM /07/0009 $5.00. performane [5], [10]. Ciruit arhiteture down-onvert ignal reeived by the antenna and digitize it. While doing o, they orrupt ignal with additive noie and aling. In addition, iruit are non-linear, though ontrained to operate in linear mode. Some of thee impairment are ompenated after the ignal i digitized. Alo, the low power ontraint puhe more of the reeiver funtionality into the digital domain. Thee fator alone make it diffiult to haraterize the performane of the iruit in iolation. The baeband equivalent model, often ued to deribe a ommuniation link, aume that the down-onverion i a ingle tep error free proe. Ciruit-indued impairment are not inluded on the ground that they an be negleted, epeially in pread petrum ytem. Thee impairment, though mall, gain importane in the ontext of low power deign. The are energy reoure ha motivated many ro layer optimization algorithm in the digital reeiver [8], [9], [15]. Thi imulator i a ombined model of the analog iruit and the digital reeiver in Matlab, providing a platform for a ro-domain tudy of iruit deign and wirele ommuniation. The impliit aumption that the ignal proeing at uniformly aro all topologie i invetigated in thi paper. Previou work inlude [15], whih make the point that the impat of different type of hardware model i motly not onidered in uh tudie. The WINS [3] and PioRadio [1] are involved in the deign of a wirele enor node on an integrated hip. Thoonen look at a few ytem level onideration for low-power wirele network [18]. ADS Ptolemy provide a imulation of the total ommuniation ytem path, but not in Matlab [1]. Thi i a diadvantage to engineer from outide the iruit domain who tand to benefit from ro-domain tudie. TrACS (Traneiver Arhiteture and Wirele Channel Simulator) preent a unique platform to tet energy onervation heme both iruit and ignal proeing and tudy the ytem level performane.. SIMULATOR CONCEPT The imulator model the ommuniation link hown in Fig. 1. The tranmitter and reeiver iruit are modeled in Matlab along with the wirele hannel, to aount for all the ignal modifiation between the digital tranmitter and reeiver. The imulator onit of five modifiable blok, eah hoen from option baed on ontraint and the wirele enario. 18

2 Figure 1. Blok Diagram of a Communiation Link. The tranmitter and reeiver iruit are implemented through variou topologie. Thi paper preent the modeling of reeiver low-power topologie. Low-IF and Diret Converion reeiver are often the only alternative onidered, but the la of ubampling reeiver i an ative area of reearh and i inluded in the imulator. Eah of thee topologie affet the ignal in different way, whih are identified and modeled a deribed in Setion III. The digital tranmitter and reeiver along with the wirele hannel are modeled in Matlab. Only the phyial (PHY) layer i implemented thi inlude pule haping, pread petrum and modulation. The wirele hannel model inlude AWGN (Additive White Gauian Noie) and fading hannel. The digital traneiver ue the baeband model, where the omplex equivalent i ued to repreent the RF ignal. Thi amount to removing the frequeny ontent of the ignal and modeling the omplex envelope to quiken the imulation. But, iruit model are paband and need to be tranlated to the baeband. The imulator provide a oheive platform for ytem-level verifiation of RF iruit deign. Along with the iruit deign, digital reeiver algorithm for power onervation and ignal ompenation an be teted imultaneouly to determine the effet on the BER (Bit Error Rate) of the ytem. The imulator aid the iruit deigner in hooing the reeiver arhiteture given the PHY layer and the wirele enario. Finally, thi imulator ould help identify optimal olution in a tet bed for wirele enor network. 3. SIMULATOR DESIGN The deign of the imulator i overed under three etion. The baeband equivalent model i ued to repreent the ignal. 3.1 Modeling Reeiver Topologie Three widely ued topologie are modeled in the imulator. The up-onverion and down-onverion are not performed; the ignal remain in the baeband throughout the imulation. But, eah blok of the reeiver affet the ignal in a unique manner, and thi i tranlated to the baeband for the purpoe of modeling Low IF Arhiteture Thi i the uper-heterodyne arhiteture with a low IF (1-10 MHz). The low IF implifie filter deign, but the image filter requirement beome teep. Thi require the ue of a quadrature reeiver, whih permit image anellation. The blok diagram of a typial low IF reeiver i hown in Fig.. Figure. Blok Diagram of the Low IF Arhiteture. The reeived ignal i down-onverted, ampled and digitized. Thee are implied in the baeband repreentation and not done expliitly. Only the ignal impairment are modeled to imulate the topology. The ignal i amplified by the LNA (Low Noie Amplifier) gain fator. Non-linearitie in the iruit introdue inter-modulation produt, whih may aturate the iruit. Only the third order produt form a part of the filtered ignal and aue interferene. The inter-modulation ignal amplitude i alulated a 3 AIM 3 = αain A ; where, A IP3 in i the input amplitude of the deired ignal, α i the LNA Gain and A IP3 i the input IP3 of the iruit. [13]. Thi i a bandpa ignal, whih i modeled in baeband after down-onverion and low pa filtering. A j πf IM t j πf IM t j π t j ( f f t [ ] f π IM e + e e = A e IM 3 IM 3 ) (1) where, f IM i the inter-modulation produt frequeny and f i the arrier frequeny. Thu, a omplex ignal at the differene frequeny i added a the inter-modulation ignal. The loal oillator introdue ome error. Reiproal mixing refer to the mimath of the LO enter frequeny and i modeled a white noie of power S 0.ΔB. [13]. The phae angle may vary, auing a ditortion, whih i modeled by multiplying the ignal with a random phae φ. Both thee error our after the downonverion, when the ignal i at the IF frequeny. Tranlating to baeband, thi reult in a power of 4 (S 0.ΔB). The mixer aue an image frequeny to alo down-onvert to the ame IF. Though image anellation i employed, thi i never perfet beaue of imbalane in the quadrature arm. The diminihed image i modeled by adding a low-power baeband ignal to the deired ignal. Sampling jitter orrupt the ignal, and thi ditortion i modeled with white noie. The variane i taken to be P ; j = π f in A σ j where fin i the maximum frequeny of the ampled ignal (f IF ), A i the input ignal amplitude and σ j i the quare root of the variane of the ample and hold iruit. [16]. Finally, the ADC introdue a quantization error, whih lie uniformly between [- Δ/, Δ/]. Δ i the tep-ize of the quantizer. The impairment added to model the Low IF arhiteture are ummarized in Fig. 3. Figure 3. Model of the Low IF Arhiteture. 19

3 3.1. Diret Converion Arhiteture Thi i the homodyne or zero-if arhiteture where the ignal i diretly down-onverted to the bae band. Simpliity of deign and the lak of need for an image-rejet filter are ome of the advantage of thi topology. But, the ignal i it own image here, and there i interferene between the upper and lower ide band. To anel the interferene, a quadrature reeiver i required. The blok diagram for thi arhiteture i hown in Fig. 4. leaking into the LO port of the mixer from the output of the LNA. [11]. The iruit exhibit a low-frequeny noie known a fliker noie or 1/f noie. Thi i repreented a random white noie of a uerinput power level in the baeband. The ampling jitter and quantization error are modeled a before. The impairment added to model the Diret Converion arhiteture are ummarized in Fig. 5. The ignal impairment are tranlated to the baeband a before. The ignal i amplified by the LNA gain. Non-linearitie are of onern here a well, but only the eond order inter-modulation produt. The low pa filter remove the third order interferene. The inter-modulation ignal amplitude i alulated a AIM = αain A ; where, A IP in i the input amplitude of the deired ignal, α i the LNA Gain and A IP i the input IP of the iruit. [13]. Thi i a baeband ignal, appearing at the frequeny f IM. The loal oillator error are modeled a before, with the exeption that the tranlation to baeband i not required. Image anellation i imperfet due to imbalane in the quadrature branhe. Thi i modeled a Re Imag Figure 4. Blok Diagram of the DC Arhiteture. { rx} = Real{ rx} ( 1+ ε ) o( θ ) Imag{ rx} ( 1+ ε ) in( θ ) { rx} = Real{ rx} ( 1 ε ) in( θ ) + Imag{ rx} ( 1 ε ) o( θ ) al () where, ε i the imbalane in amplitude and θ i the phae differene between the two branhe. [13]. The ignal i in the baeband and tray DC offet in the iruit add to the deired ignal. DC offet from three main oure i modeled. a) Self-mixing of loal oillator ignal leaking into the RF port of the mixer and the input port of the LNA. Thi i modeled a K 1 +A.K ; where K 1 i the attenuation of the LO ignal leaking into the mixer, K i the attenuation of the LO ignal leaking into the LNA and A i the LNA gain fator. b) Selfmixing of LO ignal leaking into, radiated from and refleted bak to the antenna. Thi i modeled with a omplex inuoid at the Doppler hifted frequeny (f DS ; near baeband) of amplitude A.K 3 ; where K 3 i the attenuation of the LO ignal leaking into the antenna. ) Self-mixing of trong in-band interferer leaking into the LO port of the mixer from the output of the LNA. Thi i modeled with a omplex inuoid at the differene frequeny (between in-band interferer and arrier frequeny: f O ) of amplitude A.K 4 ; where K 4 i the attenuation of interfering ignal Figure 5. Model of the DC Arhiteture IF Sub-ampling Arhiteture The intermediate frequeny in the low IF arhiteture i ometime too high for the ADC. The ignal i bandpa and an be down-ampled. But, the redution in ampling frequeny ome at the ot of aliaing noie. The blok diagram for thi topology i hown in Fig. 6. Figure 6. Blok Diagram of the IF-SS Arhiteture. Figure 7. Model of the IF-SS Arhiteture. The error oure in thi model are the ame a for the Low-IF arhiteture, with the addition of aliaing noie due to inadequate anti-alia filtering. To model the aliaing noie, we look at down ampling in detail aume the bandpa ignal bandwidth i B, the anti-aliaing filter bandwidth i B f and the ampling frequeny i F. The unfiltered noie i ed over at the ing frequeny given by f. 130

4 f = f + B F + B ; f 4 F f + B; K F > B = 4 (3) f + B F = B ; K The total noie i the noie floor of the un-ampled ignal multiplied by the number of time the noie i ed over. Let thi number be n. n f = B f + F ( f ) + 1; n The final model i given in Fig. 7. B f B 3 + ; F > B F F = B f 1 + ; KF = B F K (4) 3. Digital Traneiver Deign The digital traneiver onit of the network oftware layer, but thi imulator implement only the PHY layer - inluding modulation heme, pule haping and pread petrum. The modulation heme implemented in the imulator are the popular option for wirele enor network. The low power ontraint neeitate imple reeiver iruit, and limit u to the bai modulation tehnique. DPSK (Differential Phae Shift Keying) and O-QPSK (Offet Quadrature Phae Shift Keying) are the format ued in the ZigBee tandard. BPSK (Binary Phae Shift Keying) and QPSK (Quadrature Phae Shift Keying) are the implet modulation heme ued in fading hannel and BFSK (Binary Frequeny Shift Keying) i a well-reearhed tehnique for low power reeiver iruit. The retangular pule hape ha been provided a a default option, along with the raied oine pule and half-ine pule. Diret Sequene pread petrum i inluded in the model. 3.3 Wirele Channel Model Wirele enor network an be ued in a taggering number of wirele enario. For the purpoe of imulation, only the implet AWGN and fading hannel are modeled. Fading hannel inlude flat and frequeny eletive fading, with Rayleigh and Riian model. Doppler fading i alo inluded a an option in the model. 4. CASE STUDY The imulation reult for BFSK in an AWGN hannel are ompared for the three topologie and the ytem level perpetive i invetigated. Thi imple ae tudy ha been provided to demontrate the ue of a ytem imulator. Figure 8. Chip Error Rate veru Eb/No. Figure 9. Symbol Error Rate veru Signal to Interferene and Noie Ratio (SINR). 131

5 4.1 Binary FSK Binary FSK ha the advantage of zero power at DC. A imple logial analyi an lead to the onluion that the Diret Converion arhiteture provide the bet reult a mot of the interferene i at DC. But, thee onluion are upported by tudie baed on iruit imulation reult alone. 4. Simulation Reult The reult an be omputed at two point in the ytem. Conventionally, iruit performane i meaured at the ADC. Thi reult in a Chip Error Rate veru Eb/No. But, the ytem performane i better etimated at the end of the digital reeiver to give a Bit Error Rate veru SINR (Signal to Interferene and Noie Ratio). A omparion of the Chip Error Rate urve for the three topologie i preented in Fig. 8. The Diret Converion topology indeed eem to perform better. A omparion of the Bit Error Rate urve for the arhiteture i preented in Figure 9. Thee urve are imilar for all three arhiteture, within reaonable limit. The interferene ignal are attenuated by the proeing gain of the pread petrum ytem. However, the proeing gain i not equal aro the topologie a the error (narrowband interferene and white Gauian noie) introdued by eah topology are not the ame. The equalization in performane an be attributed to thi. The Bit Error Rate i a ytem level performane indiator a againt the Chip Error Rate, whih i more diretly a iruit performane indiator a it meaure the SNR (Signal to Noie Ratio) at the ADC. Thu, the imulation reult at the ytem level indiate an almot equal performane for all three arhiteture. Now, digital ompenation tehnique for eah of the arhiteture an be rated againt their omputational omplexity and the optimum olution an be hoen taking the hardware or ignal proeing ontraint into aount. 5. CONCLUSION The imulator preented in thi paper provide a hared platform for iruit and ignal proeing tehnique in low power reeiver. The advantage offered to iruit deigner i ytem level performane verifiation along with digital ompenation and power-onervation algorithm. The imulator provide a novel interpretation of the ommuniation link, treating the reeiver iruit a part of the hannel. The imulator performane wa teted againt well-known reult for binary FSK. The reult mathed the previouly known onluion, while offering a new and ueful perpetive at the ytem level. 6. ACKNOWLEDGMENTS Thi work ha been funded by Wirele@KTH and Swedih Sientifi Foundation under the RaMSiS projet. 7. REFERENCES [1] ADS Ptolemy - eeof.tm.agilent.om/do/addo004a/ pdf/ptolemy.pdf [] Akyildiz, I.F, Su, W., Sankaraubramaniam, Y., and Cayiri, E. A Survey on Senor Network. IEEE Communiation Magazine, (Aug. 00). [3] Aada, G. et al. Wirele Integrated Network Senor: Low Power Sytem on a Chip. Pro. ESSCIRC 98. (1998). [4] Chong, C.Y., and Kumar, S.P. Senor Network: Evolution, Oppurtunitie and Challenge. Pro. of the IEEE, Vol. 91, No. 8 (Aug. 003), [5] Crol, J., and Stayeart, M.S.J. Low-IF topologie for high performane analog front end of fully integrated reeiver. IEEE Tranation on Ciruit and Sytem-II. Analog and Digital SignalProeing, Vol.45, No.3 (Marh 1998). [6] Enz, C.C., El-Hoiydi, A., Deotignie, J.D., and Peiri, V. WieNET: An Ultralow-Power Wirele Senor Network Solution. Computer, (Aug. 004), [7] Enz C.C., Solari, N., and Yodprait, U. Ultra Low-Power Radio Deign for Wirele Senor Network. IEEE International Workhop on Radio-Frequeny Integration Tehnology (005). [8] Goldmith, A.J., and Wiker, S.B. Deign Challenge for Energy-Contrained Ad Ho Wirele Network. IEEE Wirele Communiation. (Aug 00). [9] Karlon, G., Lindfor, S., Skoglund, M., and Oien, G. Cro-Layer Optimization in Short-Range Wirele Senor Network (CROPS). CROPS/do/Tehnial.pdf [10] Lin, T.H., Kaier, W.J., and Pottie, G.J. Integrated lowpower ommuniation ytem deign for wirele enor network. Communiation Magazine, IEEE, vol. 4, Iue 1 (De. 004), [11] Park, S.B., and Imail, M. DC Offet in diret onverion multitandard wirele reeiver: Modeling and anellation. Analog Integr. Cir. Sig. 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Sytem level onideration for Ultra-low power tranmitter-only wirele network in the indoor environment. w3.ele.tue.nl/fileadmin/ele/ics/mm /File/Lopelli/Prori_Thoonen.pdf 13