PRODUCT OVERVIEW DAC REF FLASH ADC V/+15V SUPPLY. Figure 1. ADS-CCD1202 Functional Block Diagram

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1 FEATURES Unipolar input range (0 to V) MHz sampling rate 09-to- dynamic range (.db) Low noise, 00μVrms (/ of an LSB) Outstanding differential nonlinearity error (±0.5 LSB max.) Small, -pin ceramic DDIP Low power,.5 Watts Operates from ±V or ±5V supplies Edge-triggered, no pipeline delay Low cost PRODUCT OVERVIEW The functionally complete, easy-to-use ADS- CCD is a -bit, MHz Sampling A/D Converter whose performance and production testing have been optimized for use in CCD applications. This device delivers the lowest noise (00μVrms) and the best differential linearity error (±0.5LSB maximum) of any commercially available -bit A/D in its speed class. It can respond to full scale input steps (from empty to full well) with less than a single count of error, and its input is immune to overvoltages that may occur due to blooming. Packaged in an industry-standard, -pin, ceramic DDIP, the ADS-CCD requires ±5V (or INPUT/OUTPUT CONNECTIONS PIN FUNCTION PIN FUNCTION BIT (LSB) V/ 5V SUPPLY BIT GROUND BIT V/5V SUPPLY BIT 9 V REFERENCE OUT 5 BIT 0 ANALOG INPUT BIT 9 GROUND BIT NO CONNECT BIT 5 NO CONNECT 9 BIT START CONVERT BIT 5 EOC BIT GROUND BIT (MSB) 5V SUPPLY ±V) and 5V supplies and typically consumes.5 (.5) Watts. The device is 0% production tested for all critical performance parameters and is fully specifi ed over both the 0 to 0 C and 55 to 5 C operating temperature ranges. For those applications using correlated double sampling, the ADS-CCD can be supplied without its internal sample-hold amplifi er and achieve conversion rates up to.5mhz. DATEL will also entertain discussions about including the CDS circuit internal to the ADS-CCD. Please contact us for more details. BLOCK DIAGRAM ANALOG INPUT 0 S/H DAC S S BIT (MSB) BIT V REFERENCE REF BIT 9 BIT FLASH ADC REGISTER DIGITAL CORRECTION LOGIC BIT 5 BIT BIT 5 BIT BIT 9 BIT BUFFER REGISTER BIT BIT (LSB) START CONVERT EOC 5 TIMING AND CONTROL LOGIC 5V SUPPLY, NO CONNECT V/5V SUPPLY, 9, GROUND V/ 5V SUPPLY Figure. ADS-CCD Functional Block Diagram Sep 05 MDA_ADS-CCD.B0 Page of 9

2 ABSOLUTE MAXIMUM RATINGS PARAMETERS LIMITS UNITS V/5V Supply (Pin ) 0 to Volts V/ 5V Supply (Pin ) 0 to Volts 5V Supply (Pin ) 0 to Volts Digital Input (Pin ) 0. to VDD 0. Volts Analog Input (Pin 0) 5 to Volts Lead Temp. ( seconds) 00 C PHYSICAL/ENVIRONMENTAL PARAMETERS MIN. TYP. MAX. UNITS Operating Temp. Range, Case ADS-CCDMC 0 0 C ADS-CCDMM 55 5 C Thermal Impedance θjc 5 C/Watt θca C/Watt Storage Temperature Range 5 50 C Package Type -pin, metal-sealed ceramic DDIP Weight 0. ounces ( grams) FUNCTIONAL SPECIFICATIONS (TA = 5 C, ±Vcc = ±5V (or ±V), VDD = 5V, MHz sampling rate, and a minimum minute warmup ➀ unless otherwise specifi ed.) 5 C 0 TO 0 C 55 TO 5 C ANALOG INPUT MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS Input Voltage Range 0 to 0 to 0 to Volts Input Resistance kω Input Capacitance pf DIGITAL INPUT Logic Levels Logic "" Volts Logic "0" Volts Logic Loading "" μa Logic Loading "0" μa Start Convert Positive Pulse Width ➂ ns STATIC PERFORMANCE Resolution Bits Integral Nonlinearity (fi n = khz) ±0.5 ±0.5 ± LSB Differential Nonlinearity (fi n = khz) 0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 LSB Full Scale Absolute Accuracy 0. ±0. ±0. ±0.5 ±0. ±0. %FSR Offset Error (Tech Note ) ±0.5 ±0. ±0. ±0.5 ±0.5 ±. %FSR Gain Error (Tech Note ) ±0. ±0. ±0. ±0. ±0.5 ±. % No Missing Codes (fi n = khz) Bits DYNAMIC PERFORMANCE Peak Harmonics ( 0.5dB) dc to 500kHz db 500kHz to MHz db Total Harmonic Distortion ( 0.5dB) dc to 500kHz 0 db 500kHz to MHz db Signal-to-Noise Ratio (w/o distortion, 0.5dB) dc to 500kHz db 500kHz to MHz 0 db Signal-to-Noise Ratio (& distortion, 0.5dB) dc to 500kHz db 500kHz to MHz 5 9 db Two-Tone Intermodulation Distortion (fi n = 00kHz, 500kHz, fs = MHz, 0.5dB) db Noise μvrms Input Bandwidth ( db) Small Signal ( 0dB input) MHz Large Signal( 0.5dB input) MHz Feedthrough Rejection (fi n = MHz) db Slew Rate ±00 ±00 ±00 V/μs Aperture Delay Time ±0 ±0 ±0 ns Aperture Uncertainty ps rms S/H Acquisition Time (to ±0.0%FSR, V step) ns Overvoltage Recovery Time ➄ ns A/D Conversion Rate MHz ANALOG OUTPUT Internal Reference Voltage Volts Drift ±5 ±5 ±5 ppm/ºc External Current ma Sep 05 MDA_ADS-CCD.B0 Page of 9

3 5 C 0 TO 0 C 55 TO 5 C DIGITAL OUTPUTS MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS Logic Levels Logic ""... Volts Logic "0" Volts Logic Loading "" ma Logic Loading "0" ma Delay, Falling Edge of EOC to Output Data Valid ns Output Coding Straight Binary POWER REQUIREMENTS, ±5V Power Supply Range 5V Supply Volts 5V Supply Volts 5V Supply Volts Power Supply Current 5V Supply ma 5V Supply ma 5V Supply ma Power Dissipation Watts Power Supply Rejection ±0.0 ±0.0 ±0.0 %FSR/%V POWER REQUIREMENTS, ±V Power Supply Range Power Supply Range V Supply Volts V Supply Volts 5V Supply Volts Power Supply Current V Supply ma V Supply ma 5V Supply ma Power Dissipation ±V Supplies Watts Power Dissipation ±5V Supplies Watts Power Supply Rejection ±0.0 ±0.0 ±0.0 %FSR/%V Footnotes: ➀ All power supplies must be on before applying a start convert pulse. All supplies and the clock (START CONVERT) must be present during warmup periods. ➁ Contact DATEL for availability of other input voltage ranges. ➂ A 00ns wide start convert pulse is used for all production testing. ➃ Effective bits is equal to: (SNR Distortion)..0 0 log Full Scale Amplitude Actual Input Amplitude ➄ This is the time required before the A/D output data is valid after the analog input is back within the specifi ed range. TECHNICAL NOTES. Obtaining fully specifi ed performance from the ADS-CCD requires careful attention to pc-card layout and power supply decoupling. The device s analog and digital ground systems are connected to each other internally. For optimal performance, tie all ground pins (, 9, and ) directly to a large analog ground plane beneath the package. Bypass all power supplies, as well as the REFERENCE OUTPUT (pin ), to ground with.μf tantalum capacitors in parallel with 0.μF ceramic capacitors. Locate the bypass capacitors as close to the unit as possible. If the user-installed offset and gain adjusting circuit shown in Figure is used, also locate it as close to the ADS-CCD as possible.. ADS-CCD achieves its specifi ed accuracies without external calibration. If required, the device s small initial offset and gain errors can be reduced to zero using the input circuit of Figure. When using this circuit, or any similar offset and gain-calibration hardware, make adjustments following warmup. To avoid interaction, always adjust offset before gain.. When operating the ADS-CCD from ±V supplies, do not drive external circuitry with the REFERENCE OUTPUT (pin ). The reference s accuracy and drift specifi cations may not be met, and loading the circuit may cause accuracy errors within the converter.. A passive bandpass fi lter is used at the input of the A/D for all production testing. 5. Applying a start pulse while a conversion is in progress (EOC = logic "") initiates a new and inaccurate conversion cycle. Data for the interrupted and subsequent conversions will be invalid. INPUT VOLTAGE RANGE ZERO ADJUST ½ LSB Table. Zero and Gain Adjust GAIN ADJUST FS ½ LSB 0 to V.0mV 9.99V Sep 05 MDA_ADS-CCD.B0 Page of 9

4 CALIBRATION PROCEDURE (Refer to Figures and ) Any offset and/or gain calibration procedures should not be implemented until devices are fully warmed up. To avoid interaction, offset must be adjusted before gain. The ranges of adjustment for the circuit of Figure are guaranteed to compensate for the ADS-CCD s initial accuracy errors and may not be able to compensate for additional system errors. ZERO/ OFFSET ADJUST All fi xed resistors in Figure should be metal-fi lm types, and multi-turn potentiometers should have TCR s of 0ppm/ C or less to minimize drift with temperature. In many applications, the CCD will require an offset-adjust (black balance) circuit near its output and also a gain stage, presumably with adjust capabilities, to match the output voltage of the CCD to the input range of the A/D. If one is performing a "system I/O calibration" (from light in to digital out), these circuits can be used to compensate for the relatively small initial offset and gain errors of the A/D. This would eliminate the need for the circuit shown in Figure. 5V V/ 5V 5V 5V SIGNAL INPUT.μF.μF.μF V/5V 0.μF 0k GAIN ADJUST 50 0.μF 0.μF 0.μF 0 to V.μF 9, 0 00k.9k ANALOG INPUT V REF. OUT k 5V 5V Figure. ADS-CCD Calibration Circuit ADS-CCD, NO CONNECT Figure. Typical ADS-CCD Connection Diagram To Pin 0 of ADS-CCD BIT (MSB) BIT BIT 9 BIT BIT 5 BIT BIT 5 BIT BIT 9 BIT BIT BIT (LSB) 5 EOC A/D converters are calibrated by positioning their digital outputs exactly on the transition point between two adjacent digital output codes. This can be accomplished by connecting LED s to the digital outputs and adjusting until certain LED s "fl icker" equally between on and off. Other approaches employ digital comparators or microcontrollers to detect when the outputs INPUT VOLTAGE UNIPOLAR DIGITAL OUTPUT (0 TO V) SCALE MSB LSB 9.99 FS LSB.5000 / FS / FS / FS LSB change from one code to the next. For the ADS-CCD, offset adjusting is normally accomplished at the point where all output bits are 0 s and the LSB just changes from a 0 to a. This digital output transition ideally occurs when the applied analog input is /LSB (.0mV). Gain adjusting is accomplished when all bits are s and the LSB just changes from a to a 0. This transition ideally occurs when the analog input is at full scale minus / LSB s (9.99V). Offset Adjust Procedure. Apply a train of pulses to the START CONVERT input (pin ) so the converter is continuously converting. If using LED s on the outputs, a 00kHz conversion rate will reduce fl icker.. Apply.0mV to the ANALOG INPUT (pin 0).. Adjust the offset potentiometer until the output bits are and the LSB fl ickers between 0 and. Gain Adjust Procedure. Apply 9.99V to the ANALOG INPUT (pin 0).. Adjust the gain potentiometer until all output bits are s and the LSB fl ickers between and 0. THERMAL REQUIREMENTS Table. ADS-CCD Output Coding All DATEL sampling A/D converters are fully characterized and specifi ed over operating temperature (case) ranges of 0 to 0 C and 55 to 5 C. All room-temperature (TA = 5 C) production testing is performed without the use of heat sinks or forced-air cooling. Thermal impedance fi gures for each device are listed in their respective specifi cation tables. These devices do not normally require heat sinks, however, standard precautionary design and layout procedures should be used to ensure devices do not overheat. The ground and power planes beneath the package, as well as all pcb signal runs to and from the device, should be as heavy as possible to help conduct heat away from the package. Electrically insulating, thermally conductive "pads" may be installed underneath the package. Devices should be soldered to boards rather than "socketed," and of course, minimal air fl ow over the surface can greatly help reduce the package temperature. Sep 05 MDA_ADS-CCD.B0 Page of 9

5 START CONVERT N 00ns typ. N INTERNAL S/H EOC ns typ. ns typ. Hold 0ns typ. Conversion Time 0ns ±0ns Acquisition Time 90ns typ. 0ns ±ns 5ns max. 5ns max. OUTPUT DATA DATA (N-) VALID DATA N VALID 5ns min. INVALID DATA Note: Scale is approximately 5ns per division. Figure. ADS-CCD Timing Diagram TIMING The ADS-CCD is an edge triggered device. A conversion is initiated by the rising edge of the start convert pulse and no additional external timing signals are required. The device does not employ "pipeline" delays to increase its throughput rate. It does not require multiple start convert pulses to bring valid digital data to its output pins. 5V C 5pF COG OFFSET ADJ ANALOG INPUT R 0K P C9 5V P C R 50 GAIN ADJ J5 C0 R 00K 5% OP- START CONVERT 5V R.9K 5V 0.% R K 0.% C U P R K 0.% C. MF 5V C 5V C C C R5 K.% R K 0.% C U5 AD5 J J C C C C5 C9 5V C5 U C 5V C U LS C ADS-CCD/ 5V B DGND 5 EOC ST. CONV B B B5 9 B B B 9 AGND 0 INPUT U B B9 5 B VREF 5V AGND B B B B 5 U LS 9 5V C U LS0 0 SG B A Y B SG A Y B A Y B A Y 9 B5 A Y A Y B 5 A 5 Y B A Y 9 G G 5V C U LS0 A A A A 0 Y Y Y Y A A 5 A A 9 G 9 Y Y 5 Y Y G U B B9 B B B B B J 0 MSB 9 0 P LSB 5 EOC ST.CONV. ENABLE J SG Y SEE NOTE XTAL 5V C C LS NOTES:. FOR ADS-BCCD Y IS.MHZ FOR ADS-BCCD Y IS MHZ LS Figure 5. ADS-CCD Evaluation Board Schematic Sep 05 MDA_ADS-CCD.B0 Page 5 of 9

6 0 0 Amplitude Relative to Full Scale (db) Frequency (khz) Figure. ADS-CCD FFT (fin = 95kHz, fs = MHz, Vin = 0.5dB,,09 points) Sep 05 MDA_ADS-CCD.B0 Page of 9

7 Number of Occurences This histogram represents the typical peak-to-peak noise (including quantization noise) associated with the ADS-CCD.,09 conversions were processed with the input to the ADS-CCD tied to analog ground. 0 Digital Output Code Figure. ADS-CCD Grounded Input Histogram 0. DNL (LSB's) 0 Number of Occurences Digital Output Code 0 09 Digital Output Code Figure. ADS-CCD Histogram and Differential Nonlinearity Sep 05 MDA_ADS-CCD.B0 Page of 9

8 MECHANICAL DIMENSIONS INCHES (mm). MAX. (.) 0.0 MAX. (0.) -PIN DDIP Dimension Tolerances (unless otherwise indicated): place decimal (.XX) ±0.0 (±0.5) place decimal (.XXX) ±0.005 (±0.) Lead Material: Kovar alloy Lead Finish: 50 microinches (minimum) gold plating over 0 microinches (nominal) nickel plating 0.5 MAX. (5.99).0 (.90) 0.0 TYP. (.50) 0.00 MAX. (5.00) (0.5) 0.90 MAX. (.) 0.0 ±0.00 (0.5) 0.0 (.50) 0.00 (.0) SEATING PLANE 0.05 (0.5) 0.00 ±0.0 (5.0) 0.0 (.50). MAX. (.0) 0.0 MAX. (0.) -PIN SURFACE MOUNT Dimension Tolerances (unless otherwise indicated): place decimal (.XX) ±0.0 (±0.5) place decimal (.XXX) ±0.005 (±0.) Lead Material: Kovar alloy Lead Finish: 50 microinches (minimum) gold plating over 0 microinches (nominal) nickel plating 0.90 MAX. (.) PIN INDEX 0.00 TYP. (0.50) 0.00 TYP. (.5) 0.0 TYP. (.0) 0.05 (0.) MAX. radius for any pin 0.0 TYP. (.50) 0.00 (.0) 0.0 (.50) 0.00 (0.50) 0.0 TYP. (0.5) ORDERING INFORMATION MODEL NUMBER OPERATING TEMP. RANGE ANALOG INPUT ACCESSORIES ADS-CCDMC 0 to 0 C Unipolar (0 to V) ADS-BCCD Evaluation Board (without ADS-CCD) ADS-CCDMM 55 to 5 C Unipolar (0 to V) HS- Heat Sink for all ADS-CCD models Receptacles for pc board mounting can be ordered through AMP, Inc., Part # -- (Component Lead Socket), required. Contact DATEL for availability of surface-mount packaging or high-reliability screening. Sep 05 MDA_ADS-CCD.B0 Page of 9

9 MODEL NUMBER OPERATING TEMP. RANGE ORDERING INFORMATION PACKAGE ROHS ACCESSORIES ADS-CCDMC 0 to 0 C TDIP NO ADS-BCCD Evaluation Board (without ADS-CCD) ADS-CCDMM 55 to 5 C TDIP NO HS- Heat Sink for all ADS-CCD models ADS-CCDMM-QL 55 to 5 C TDIP NO ADS-CCDMC-C 0 to 0 C TDIP YES ADS-CCDMM-C 55 to 5 C TDIP YES ADS-CCDMM-QL-C 55 to 5 C TDIP YES Receptacles for pc board mounting can be ordered through AMP, Inc., Part # -- (Component Lead Socket), required. Contact DATEL for availability of surface-mount packaging or high-reliability screening. DATEL is a registered trademark of DATEL, Inc. Cabot Boulevard, Mansfield, MA 00-5 USA ITAR and ISO 900/0 REGISTERED DATEL, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifi cations are subject to change without notice. 05 DATEL, Inc. help@datel.com Sep 05 MDA_ADS-CCD.B0 Page 9 of 9