SPT BIT, 150 MSPS, FLASH A/D CONVERTER TECHNICAL DATA

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Franklin Bruce
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1 FEATURES Metastable errors reduced to LSB Low input capacitance: 0 pf Wide input bandwidth: 0 MHz 50 MSPS conversion rate Typical power dissipation:. watts GENERAL DESCRIPTION The is a monolithic flash A/D converter capable of digitizing a two volt analog input signal into 8-bit digital words at a 50 MSPS (typ) update rate. For most applications, no external sample-and-hold is required for accurate conversion due to the device s narrow aperture time, wide bandwidth, and low input capacitance. A single standard 5. volt power supply is required for operation of the, with nominal power dissipation 8-BIT, 50 MSPS, FLASH A/D CONVERTER TECHNICAL DATA APPLICATIONS AUGUST 7, 00 Digital oscilloscopes Transient capture Radar, EW, ECM Direct RF down-conversion Medical electronics: ultrasound, CAT instrumentation of. W. A proprietary decoding scheme reduces metastable errors to the LSB level. The is available in 4-lead ceramic sidebrazed DIP, surface-mount 44-lead cerquad and 46-lead PGA packages; the cerquad and PGA packages allow access to additional reference ladder taps, an overrange bit, and a data ready output. The is available in the industrial temperature range. BLOCK DIAGRAM Analog Input (Force or Sense) LINV MINV V RTS V RTF Preamp Comparator Clock Buffer MSB D7 DRINV DREAD V R3 5 Overrange 5 D7 MSB 8 V R to 8-Bit Encoder ECL Latches and Buffers These functions are available in the PGA and cerquad packages only. V R 63 V RBF LSB D0 D0 LSB V RBS Convert Analog Input (Sense or Force)

2 ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 5 C Supply Voltages Negative Supply Voltage ( TO GND) 7.0 to 0.5 V Ground Voltage Differential to 0.5 V Input Voltage Analog Input Voltage... to 0.5 V Reference Input Voltage... to 0.5 V Digital Input Voltage... to 0.5 V Reference Current V RTF to V RBF... 5 ma Output Digital Output Current... 0 to 30 ma Temperature Operating Temperature,ambient... 5 to 85 C junction C Lead Temperature, (soldering 0 seconds) C Storage Temperature to 50 C Note:. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. ELECTRICAL SPECIFICATIONS T A = T MIN to T MAX, = 5. V, R Source =50 Ω, V RBF =.00 V, V R =.00 V, V RTF =0.00 V, ƒ =5 MHz, Duty Cycle=50%, unless otherwise specified. TEST TEST A B PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS DC Accuracy Integral Linearity Error ƒ = 00 khz VI 0.75 ± ± LSB Differential Linearity Error ƒ = 00 khz VI LSB No missing codes Guaranteed Guaranteed Analog Input Offset Error V RT VI mv Offset Error V RB VI mv Input Voltage Range VI Volts Input Capacitance Over full input range V 0 0 pf Input Resistance V 5 5 kω Input Current VI µa Input Slew Rate V,000,000 V/µs Large Signal Bandwidth =F.S. V 0 0 MHz Small Signal Bandwidth =500 mv P-P V MHz Clock Synchronous Input Currents V µa Reference Input Ladder Resistance VI Ω Reference Bandwidth V 0 0 MHz Timing Characteristics Maximum Sample Rate IV MSPS Clock to Data Delay V.4.4 ns Output Delay Tempco V ps/ C -to-data Ready Delay (t D ) V.0.0 ns Aperture Jitter V 5 5 ps Acquisition Time V.5.5 ns Dynamic Performance Signal-to-Noise Ratio ƒ IN = 3.58 MHz VI db ƒ IN = 50 MHz VI db Total Harmonic Distortion ƒ IN = 3.58 MHz VI db ƒ IN = 50 MHz VI db Signal-to-Noise and Distortion ƒ IN = 3.58 MHz VI db (SINAD) ƒ IN = 50 MHz VI db 8/7/0

3 ELECTRICAL SPECIFICATIONS T A = T MIN to T MAX, = 5. V, R Source =50 Ω, V RBF =.00 V, V R =.00 V, V RTF =0.00 V, ƒ =5 MHz, Duty Cycle=50%, unless otherwise specified. TEST TEST A B PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS Digital Inputs Digital Input High Voltage (MINV, LINV) VI Volts Digital Input Low Voltage (MINV, LINV) VI Volts Clock Low Width, t PWL VI ns Clock High Width, t PWH VI ns Digital Outputs Digital Output High Voltage 50 Ω to V VI.. Volts Digital Output Low Voltage 50 Ω to V VI.5.5 Volts Power Supply Requirements Supply Current 5 C VI ma Power Dissipation 5 C VI W TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. Unless otherwise noted, all test are pulsed tests; therefore, T J = T C = T A. LEVEL I II III IV V VI TEST PROCEDURE 00% production tested at the specified temperature. 00% production tested at T A = 5 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 00% production tested at T A = 5 C. Parameter is guaranteed over specified temperature range. 3 8/7/0

4 TYPICAL PERFORMANCE CHARACTERISTICS SNR vs Input Frequency THD vs Input Frequency ƒ S = 5 MSPS Signal-to-Noise Ratio (db) Total Harmonic Distortion (db) ƒ S = 5 MSPS Input Frequency (MHz) Input Frequency (MHz) 5 SINAD vs Input Frequency 50 SNR, THD, SINAD vs Temperature Signal-to-Noise and Distortion (db) ƒ S = 5 MSPS SNR, THD, SINAD (db) ƒ S = 5 MSPS ƒ IN = 50 MHz SNR THD SINAD Input Frequency (MHz) Temperature ( C) 4 8/7/0

5 Figure Typical Interface Circuit RT U *See below Voltage Limiter Analog Input Can Be Either Force Or Sense VRTF VIN L. µf 5. V.0 µf LINV MINV Preamp Comparator 56 Clock Buffer MSB D Typical Voltage Limiter R S ==HP, N 57 V R 8.0 µf 7 56 To 8-Bit Encoder ECL Latches And Buffers V Ref 0 V U.0 µf. Q (N907A) VRBF LSB D0 Analog Input Can Be Either Force Or Sense. µf.0 µf VIN Convert 006 V (Analog).0 µf.0 µf.0 µf 5. V V (Digital) GENERAL DESCRIPTION The is a fast monolithic 8-bit parallel flash A/D converter. The nominal conversion rate is 50 MSPS and the analog bandwidth is in excess of 00 MHz. A major advance over previous flash converters is the inclusion of 56 input preamplifiers between the reference ladder and input comparators. (See block diagram.) This not only reduces clock transient kickback to the input and reference ladder due to a low AC beta but also reduces the effect of the dynamic state of the input signal on the latching characteristics of the input comparators. The preamplifiers act as buffers and stabilize the input capacitance so that it remains constant for varying input voltages and frequencies and, therefore, makes the part easier to drive than previous flash converters. The incorporates a proprietary decoding scheme that reduces metastable errors (sparkle codes or flyers) to a maximum of LSB. The has true differential analog and digital data paths from the preamplifiers to the output buffers (Current Mode Logic) for reducing potential missing codes while rejecting common mode noise. Signature errors are also reduced by careful layout of the analog circuitry. Every comparator also has a clock buffer to reduce differential delays and to improve signal-tonoise ratio. The output drive capability of the device can provide full ECL swings into 50 Ω loads. TYPICAL INTERFACE CIRCUIT The typical interface circuit is shown in figure. The is relatively easy to apply depending on the accuracy needed in the intended application. Wire-wrap may be employed with careful point-to-point ground connections if desired, but to achieve the best operation, a 5 8/7/0

6 Figure Typical Interface Circuit (PGA and Cerquad packages only) RT U *See below Voltage Limiter VCC U VCC Q 0 W Analog Input Force L. µf 5. V.0 µf VRTF VIN LINV MINV. µf.0 µf VRTS Preamp Comparator 56 Typical Voltage Limiter R S 49.9 R 9 Clock Buffer Overrange D8 5. MSB D7 9 U 0-5 W VR3 U and U= Rail-to-Rail Op Amp =HP, N57 Q=NA Q=N907A R = kw,.% R R.0 µf 0-5 W VR U.0 µf to 8-Bit Encoder ECL Latches And Buffers 0-5 W VR U 64.0 µf 63 R LSB D0 VREF V U W VRBF.0 µf VRBS DRINV Convert 006. µf.0 µf V (Analog) Analog Input VIN (Sense).0 µf.0 µf.0 µf 5. V DREAD V V (Digital).0 µf double-sided PC board with a ground plane on the component side separated into digital and analog sections will give the best performance. The converter is bonded-out to place the digital pins on the left side of the package and the analog pins on the right side. Additionally, an RF bead connection through a single point from the analog to digital ground planes will reduce ground noise pickup. The circuit in figure (PGA and cerquad packages only) is intended to show the most elaborate method of achieving the least error by correcting for integral nonlinearity, input induced distortion, and power supply/ground noise. This is achieved by the use of external reference ladder tap connections, an input buffer, and supply decoupling. The function of each pin and external connections to other components is as follows:,, is the supply pin with as ground for the device. The power supply pins should be bypassed as close to the device as possible with at least a.0 µf ceramic capacitor. A µf tantalum should also be used for low frequency suppression. is the ground for the ECL outputs and is to be referenced to the output pulldown voltage and appropriately bypassed as shown in figure. (ANALOG INPUT) There are two analog input pins that are tied to the same point internally. Either one may be used as an analog input sense and the other for input force. This is convenient for testing the source signal to see if there is sufficient drive capability. The pins can also be tied together and driven by 6 8/7/0

7 Table I Output Coding BINARY TWOs COMPLEMENT TRUE INVERTED TRUE INVERTED MINV=LINV=0 MINV=LINV= MINV=; LINV=0 MINV=0; LINV= ANALOG INPUT VOLTAGE D8 D7 D0 D7 D0 D7 D0 D7 D0 V / LSB V V / LSB V the same source. The is superior to similar devices, due to a preamplifier stage before the comparators. This makes the device easier to drive because it has constant capacitance and induces less slew rate distortion. An optional input buffer may be used., (CLOCK INPUTS) The clock inputs are designed to be driven differentially with ECL levels. The clock may be driven single-ended since is internally biased to.3 V. (See clock input circuit.) may be left open, but a.0 µf bypass capacitor from to is recommended. NOTE: System performance may be degraded due to increased clock noise or jitter. MINV, LINV (OUTPUT LOGIC CONTROL) These are ECL-compatible digital controls for changing the output code from straight binary to two s complement, etc. For more information, see table I. Both MINV and LINV are in the logic low (0) state when they are left open. The high state can be obtained by tying to through a diode or 3.9 kω resistor. D0 TO D7 (DIGITAL OUTPUTS) The digital outputs can drive ECL levels into 50 Ω when pulled down to V. When pulled down to 5. V, the outputs can drive 50 Ω to kω loads. V RBF, V R, V RTF (REFERENCE INPUTS) There are two reference inputs and one external reference voltage tap. These are V (V RBF ), mid-tap (V R ), and (V RTF ). The reference pins can be driven as shown in figure. V R should be bypassed to for further noise suppression. V RBF, V RBS, V R, V R, V R3, V RTF, V RTS REFERENCE INPUTS (PGA AND CERQUAD PACKAGES ONLY) These are five external reference voltage taps from V (V RBF ) to (V RTF ) that can be used to control integral linearity over temperature. The taps can be driven by op amps as shown in figure. These voltage level inputs can be bypassed to for further noise suppression if so desired. V RB and V RT have force and sense pins for monitoring the top and bottom voltage references. All Not Connected pins should be tied to on the left side of the package and to on the right side of the package. DREAD DATA READY; DRINV DATA READY INVERSE (PGA AND CERQUAD PACKAGES ONLY) The data ready pin is a flag that goes high or low at the output when data is valid or ready to be received. It is essentially a delay line that accounts for the time necessary for information to be clocked through the s decoders and latches. This function is useful for interfacing with high-speed memory. Using the data ready output to latch the output data ensures minimum set-up and hold times. DRINV is a data ready inverse control pin. (See the timing diagram.) D8 OVERRANGE (PGA AND CERQUAD PACKAGES ONLY) This is an overrange function. When the is in an overrange condition, D8 goes high and all data outputs go high as well. This makes it possible to include the into higher resolution systems. 7 8/7/0

8 OPERATION The has 56 preamp/comparator pairs that are each supplied with the voltage from V RTF to V RBF divided equally by the resistive ladder as shown in the block diagram. This voltage is applied to the positive input of each preamplifier/comparator pair. An analog input voltage applied at is connected to the negative inputs of each preamplifier/comparator pair. The comparators are then clocked through each comparator s individual clock buffer. When pin is in the low state, the master or input stage of the comparators compares the analog input voltage to the respective reference voltage. When changes from low to high, the comparators are latched to the state prior to the clock transition and output logic codes in sequence from the top comparators, closest to V RTF (0 V), down to the point where the magnitude of the input signal changes sign (thermometer code). The output of each comparator is then registered into four 64-to-6 bit decoders when is changed from high to low. At the output of the decoders is a set of four 7-bit latches that are enabled (track) when changes from high to low. From here, the outputs of the latches are coded into 6 LSBs from 4 columns, and 4 columns are coded into MSBs. Next are the MINV and LINV controls for output inversions, which consist of a set of eight XOR gates. Finally, 8 ECL output latches and buffers are used to drive the external loads. The conversion takes one clock cycle from the input to the data outputs. Figure 3 Timing Diagram Analog Input N N N Clock t PW t PW0 Master Comparator Output Slave 6 Bit Latch Output Internal Timing 8 Bit Latch Output Data Output D0 D7 N N N Overrange D8 t D Data Ready Timing for PGA and Cerquad Packages Only 8 8/7/0

9 Figure 4 Subcircuit Schematics Input Circuit Output Circuit MINV, LINV Input Circuit V R 0 kw MINV LINV.3 V Data Out 6 kw Figure 5 Clock Input Figure 6 Burn-In Circuit (4-lead DIP Package only) V REF N4736 R4 R4.0 V 3 kw EVALUATION BOARDS 3 kw.3 V The EB770 evaluation board is available to aid designers in demonstrating the full performance of the. This board includes a voltage reference circuit, clock driver circuit, output data latches, and an on-board reconstruction of the digital data. An application note describing the operation of this board, as well as application tips, is also available. Contact the factory for price and delivery. R R R R = /4 Watt CC 5% R = kw /4 Watt CC 5% R 3 = 6.5 W /4 Watt CC 5% R 4 = 6.5 W / Watt CC 5% V REF =.0 Volts = 6.6 Volts R3 VRBF VRTF D0 D7 LINV MINV R R R R R R R R R.0 V 9 8/7/0

10 PACKAGE OUTLINES 4-Lead Sidebrazed DIP A 4 B C G H D E F INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A B C D.050 typ.7 E.050 typ.7 F G H I J I J 46-Lead Pin Grid Array B A Pin D E INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A B 0.00 typ.54 typ C.045 dia.055 dia.4.40 D E F.00 dia.030 dia G.050 typ.7 typ F Stand-off Pin C Diameter G 0 8/7/0

11 44-Lead Cerquad C D A B INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A typ 3.97 typ B C D 0.06 typ 0.4 typ E typ 0.0 typ F G typ 0.5 typ H A B 0 5 H E G F 8/7/0

12 PIN ASSIGNMENTS 9 D8 D0 D7 DREAD V RBS V RBF MINV V RBS V RBF 8 V R D8 D7 D0 DREADY V R MINV LINV DRINV V RTS V R V R V R LINV 30 9 DRINV V RTS 3 V RTF ORDERING INFORMATION 4 Bottom View PGA 3 Cerquad V R3 V RTF PART NUMBER LINEARITY TEMPERATURE RANGE PACKAGE TYPE AIJ 0.75 LSB 5 to 85 C 4L Ceramic S/B BIJ 0.95 LSB 5 to 85 C 4L Ceramic S/B AIG 0.75 LSB 5 to 85 C 46L PGA BIG 0.95 LSB 5 to 85 C 46L PGA AIQ 0.75 LSB 5 to 85 C 44L Cerquad BIQ 0.95 LSB 5 to 85 C 44L Cerquad BCU 0.95 LSB 5 C Die* *Please see the die specification for guaranteed electrical performance. A B C D E F G H J LINV D0 (LSB) D7 (MSB) MINV DIP V RTF V R 0 V RBF PIN FUNCTIONS Name LINV D0 D7 MINV V R V RTF V RBF Function D0 through Output Inversion Control Pin Negative Analog Supply Nominally 5. V Digital Ground Digital Data Output (LSB) Digital Data Output Digital Data Output (MSB) D7 Output Inversion Control Pin Inverse ECL Clock Input Pin ECL Clock Input Pin Analog Ground Analog Input; Can be Connected to the Input Signal or Used as a Sense Reference Voltage Tap (.0 V typ) Reference Voltage Top Reference Voltage Bottom The following pins are on PGA and cerquad packages only. DRINV DREAD Data Ready Inverse Data Ready Output Overrange Overrange Output D8 V R V R3 V RTS V RBS Reference Voltage Tap (.5 V typ) Reference Voltage Tap 3 ( 0.5 V typ) Reference Voltage Top, Sense Reference Voltage Bottom, Sense DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Copyright 00 Fairchild Semiconductor Corporation 8/7/0

CDK bit, 1 GSPS, Flash A/D Converter

CDK bit, 1 GSPS, Flash A/D Converter CDK1303 8-bit, 1 GSPS, Flash A/D Converter FEATURES n 1:2 Demuxed ECL compatible outputs n Wide input bandwidth 900MHz n Low input capacitance 15pF n Metastable errors reduced to 1 LSB n Gray code output