CALIFORNIA STATE UNIVERSITY, NORTHRIDGE DESIGN AND IMPLEMENTATION OF A DPSK TRANSMITTER USING SOFTWARE DEFINED RADIO. Yan Jin.

Transcription

1 CALIFORNIA STATE UNIVERSITY, NORTHRIDGE DESIGN AND IMPLEMENTATION OF A DPSK TRANSMITTER USING SOFTWARE DEFINED RADIO A project submitted in partial fulfillment of the requirements For the degree of Master of Science in Electrical Engineering By Yan Jin December 2014

2 The graduate project of Yan Jin is approved: Dr. Xiyi Hang Date Prof. James A Flynn Date Dr. Sharlene Katz, Chair Date California State University, Northridge ii

3 TABLE OF CONTENTS Signature Page... ii List of Figures... iv List of Tables... vi Abstract... vii Section 1: Introduction...1 Section 2: Background Information Software Defined Radio Universal Software Radio Peripheral Digital Communication System...4 Differential Binary Phase Shift Keying Synchronization...6 Section 3: Transmitter Simulink Model Pre-loading Setting Bits Generation...10 Frame Synchronization...11 Barker Code...12 Header Generation...14 Data Frame Generation DBPSK Modulation Root Raised Cosine Transmit Filter USRP Transmitter...24 Section 4: Receiver Simulink Model Timing Recovery...30 Interpolator...31 Timing Error Detector...36 Loop Filter...39 Interpolation Controller Modified Buffer...44 Section 5: Conclusions...48 References...49 Appendix A...50 Appendix B...51 iii

4 LIST OF FIGURES Figure 2. 1 System Block Diagram... 3 Figure 2. 2 Basic Communication System... 4 Figure 2. 3 Using Differential Encoder to generate DPSK Signal... 5 Figure 2. 4 DPSK Signal Generated from Data Stream... 6 Figure 2. 5 Symbol Timing Error... 7 Figure 3. 1 DBPSK Transmitter Simulink Model... 8 Figure 3. 2 Bits Generation Subsystem Figure 3. 3 Data Frame Structure Figure 3. 4 Autocorrelation function of a Barker-13 code Figure 3. 5 Constant Barker Code Block Parameters Figure 3. 6 Signal from Workspace Block Parameters Figure 3. 7 Algorithm of Scrambler [3] Figure 3. 8 Scrambler Block Parameters Figure 3. 9 Scrambler in the Simulink model of Transmitter Figure Differential Encoder [4] Figure M-DPSK Modulator Baseband Block Parameter Figure Input Waveform of the DBPSK Modulator Baseband block Figure Output Waveform of the DBPSK Modulator Baseband block Figure Raised Cosine Transmit Filter Block Parameter Figure Output Waveform of the Raise Cosine Filter Figure Output Waveform of the Raise Cosine Filter Figure Block Diagram of SDRu Transmitter implementation Figure SDRu Transmitter Block Parameter Figure Transmitter Simulink Model in Running Figure Sample Time for the Transmitter Simulink Model Figure 4. 1 Receiver Simulink Model Figure 4. 2 Data Processing Subsystem Figure 4. 3 Timing Recovery Subsystem Block Diagram Figure 4. 4 Simulink Implementation of Timing Recovery Subsystem Figure 4. 5 Rate Conversion with Continuous Time Filter Figure 4. 6 Sample Time Relations Figure 4. 7 Piecewise parabolic Farrow interpolator structure implementation in Simulink Model Figure Zero-crossing Time Error Detector Block Diagram Figure 4. 9 Kp of the zero-crossing TED as a function of excess bandwidth for the square-root raised-cosine pulse shape and binary PAM with KEavg = 1 [5] Figure An illustration of the relationship between the available matched filter output samples and the desired interpolants Figure Proportional-plus-integrator Loop Filter Figure Interpolation Controller block diagram [8] Figure Interpolation Controller Subsystem in Simulink Model iv

5 Figure Block Diagram of Simulink model of Modulo-1 decrementing counter Figure Simulink model of Modulo-1 decrementing counter Figure Simulink model of Enabled hold subsystem Figure Modified Buffer Subsystem Figure Simulink implementation of the Modified Buffer Figure Delay Line block parameter setting Figure Counter Limited Block parameter setting v

6 LIST OF TABLES Table 1 Example of the Input Sequence, Encoded Sequence and Modulated Phase... 5 Table 2 Simulink Parameter Settings... 9 Table 3 Example of the scrambler Table 4 Example of the Input and Output Waveform of the DBPSK Modulator Table 5 Farrow coefficients bl(i) for piecewise parabolic interpolator vi

7 ABSTRACT DESIGN AND IMPLEMENTATION OF A DPSK TRANSMITTER USING SOFTWARE DEFINED RADIO By Yan Jin Master of Science in Electrical Engineering The objective of this project was to create a differential phase shift keying (DPSK) transmitter using software defined radio (SDR). This transmitter was designed to work with a compatible receiver to form an over the air link. The receiver was designed as a separate M. S. project. The symbol timing recovery for the link is also described in this report. The transmitter was created using the Universal Software Radio Peripheral (USRP) with Mathworks Simulink software. The link was successfully tested. vii

8 SECTION 1: INTRODUCTION This report describes the design and implementation of a differential phase shift keying (DPSK) communications transmitter using software defined radio (SDR). This transmitter is used to send signals on an over the air link to an SDR receiver. The receiver was designed and implemented in a separate graduate project that is documented in Reference 1. This SDR based transmitter utilizes the Ettus Universal Software Radio Peripheral (USRP). The software required was created in Mathworks Simulink. SDR is an emerging technology that allows for simple modification of a communications system without modifying any hardware. Section 2 of this report describes the concept of Software Defined Radio (SDR) and introduces the open source SDR hardware platform, the USRP. It also provides basic background information on digital communication systems, including DPSK modulation theory and the three types of synchronization involved in the design of DPSK communication links. Section 3 of this report discusses the transmitter model including its various subsystems. Section 4 describes the receiver timing recovery that is required to receive this transmitted signal. Section 5 provides a summary and conclusions along with suggestions for future work. 1

9 SECTION 2: BACKGROUND INFORMATION 2.1 Software Defined Radio There are a number of forms of communications systems that we use in our daily lives. Radio is one of these. Hardware radio is the current method for implementing most broadcast radios. The traditional hardware radio is not easy to change once the devices are produced. In order to have a more flexible communications link, a new technology called Software Defined Radio (SDR) has been used. Software defined radio is a radio communication system where most of the signal processing part is controlled by using software. Thus the communication system can be modified easily by changing the software in order to meet different requirements in various applications. More details on SDR can be found in another graduate report Design and Implementation of a DPSK Receiver Using Software Defined Radio [1] In this project, the SDR development platform uses MATLAB Simulink along with the Universal Software Radio Peripheral (USRP) to create a Differential Binary Phase- Shift Keying transmitter. 2.2 Universal Software Radio Peripheral The Universal Software Radio Peripheral (USRP) developed by Ettus Research LLC is one of the most popular SDR hardware platforms. It is an open source design. The data sheet and the schematics of the USRP are freely available including reference modules. Anyone can study and modify the design or hardware based on the USRP. The USRP contains a Radio Frequency (RF)-frontend which is the circuitry for up conversion and down conversion, an Analog to Digital Converter (ADC) which samples 2

10 the analog signal and produces samples, a Digital to Analog Converter (DAC) which converts the digital signal to an analog signal, and a Field Programmable Gate Array (FPGA) which processes the data. There are different RF daughterboards available for the USRP using different frequency bands. In this project, the WBX-120 USRP TM Daughterboard is used. It supports the 50MHz to 2.2 GHz frequency ranges. Figure 2.1 illustrates how an SDR system works with the USRP and Simulink on the computer. The USRP communicates with the PC through an Ethernet cable. The host computer uses Simulink to control the USRP hardware and transmit or receive data. USRP Hardware PC XCVR2450 RF Daughterboard ADC DAC Spartan-3 FPGA Gigabit Ethernet Gigabit Ethernet Simulink Figure 2. 1 System Block Diagram When transmitting a signal, the process begins with the PC. A baseband signal, digital data in original form, is created in Simulink. The sampled signal is passed to USRP FPGA via Ethernet cable. Then the DAC converts the baseband samples to an analog signal. After that, the Daughterboard shifts the baseband signal to the carrier frequency and transmits it through the antenna. When receiving signals, the process is reversed. The RF Daughterboard shifts the receive signal down to zero. The output of the Daughterboard then sends the signal to the ADC for sampling. Then the samples are sent through the FPGA to the PC and the Simulink model via an Ethernet cable. 3

11 2.3 Digital Communication System Information is a critical part of people s live. People need to establish a communication system to exchange information instantaneously. Figure 2.2 shows a block diagram of a basic communication system. Figure 2. 2 Basic Communication System The basic digital communication system consists of a transmitter and a receiver. The digital source is transmitted from the transmitter to the receiver through a channel. The synchronization block is necessary in order to synchronize the samples in the transmitter and receiver. Differential Binary Phase Shift Keying Modulation is a process to convert source information into a proper signal waveform which is suitable for transmission through the channel. For the purpose of this project, Differential Binary Phase Shift Keying (DPSK) is used for modulation scheme. Differential Binary Phase Shift Keying (DPSK) is a digital modulation scheme that conveys data by changing the phase of a carrier signal. A method called the differential encoding for generating a DPSK signal is showed in Figure 2.3. In this figure, d n is the 4

12 message sequence that is being transmitted. It is applied to one input of the XOR logic gate. Another input to the XOR logic gate is the output of the XOR gate e n delayed by one bit. e n e n 1 d n, d n XOR e n BPSK Modulator DPSK Modulated Signal Delay T b Figure 2. 3 Using Differential Encoder to generate DPSK Signal Then the encoded message sequence passes through the BPSK modulator to generate the DPSK modulated signals. An example of the DPSK waveform is shown in Figure 2.4 and the corresponding data sequence (d n ), encoded sequence (e n ) and the corresponding carrier phase is listed in Table 1. Input Sequence d n Encoded e n Sequence Reference Bit Carrier Phase 0 π π 0 π π π 0 π π Table 1 Example of the Input Sequence, Encoded Sequence and Modulated Phase 5

13 dn en DPSK Modulated Waveform Figure 2. 4 DPSK Signal Generated from Data Stream When transmitting the message through a channel, an unknown phase shift will be introduced into the modulated signal. This will cause the constellation rotation and there will be a phase ambiguity. Standard PSK requires synchronization to detect this phase shift. The key idea of DPSK is to use the difference between two adjacent bits to avoid the problem. As illustrated in Figure 2.4, in a DBPSK system, a binary 1 can be transmitted by adding 180 o to the current phase and a binary 0 can be transmitted by adding 0 o to the current phase. 2.4 Synchronization Recall the basic communication system shown in Figure 1.2. Synchronization is necessary and important because the accuracy of the synchronization will determine the performance of the communication system. There are three types of synchronization used in this project. One is the frame synchronization, one is the carrier phase synchronization and the other is symbol timing synchronization. 6

14 For the frame synchronization, a special data frame header is added in front of each data frame on the transmitter side so the receiver can determine where the actual message begins in the receiver signals. There are two parts in carrier synchronization, one is the carrier frequency and the other is carrier phase. For the carrier frequency recovery, in this project, a sufficiently accurate frequency adjustment is made on the receiver side. That is enough because with DPSK modulation. For the phase recovery, the receiver needs to track the phase of its local carrier oscillator with that of the received signal by using a phase locked loop. In a communications link, it takes some time for the signal wave to travel from the transmitter to the receiver. The transmission delay will introduce a mismatch in symbol timing between the transmitter and the receiver. For symbol timing synchronization, the receiver needs to figure out when to sample the output of the matched filter in order to align the symbol timing at transmitter side and minimize the symbol timing error. Figure 2.5 illustrated the symbol timing error influence on the receiver. If the sampling clock of the receiver is slightly different than the transmitter, the windows drift. Symbol timing error will be introduced to the received signal. S1 S2 S3 S4 Poor Synchronization: S1 and S2 interfere Transmitted Symbol Matched Filter Figure 2. 5 Symbol Timing Error 7

15 SECTION 3: TRANSMITTER SIMULINK MODEL The transmitter in this DPSK system consists of a Simulink model and USRP hardware. A message of Hello ###, will be transmitted where ### is a repeating sequence of values from zero to nine. Simulink provides a graphical user interface (GUI) environment for people to simulate and analyze dynamic systems. Simulink includes a comprehensive block library of tool boxes for many types of analyses. In the transmitter Simulink model, a Bits Generation subsystem, an M-DPSK modulator Baseband block, a Raised Cosine Transmit Filter block and an SDRu Transmitter block is used. Figure 3.1 shows the Simulink model of the DBPSK transmitter implemented in this project. The Bits Generation Subsystem creates the data frame. The DBPSK modulator block and the Raised Cosine Transmit Filter convert the data message to a proper DPSK signal which can be transmitted over the channel. The SDRu Transmitter block sets up a link between the transmitter Simulink model and the USRP hardware. The subsystems and block details are described later. Figure 3. 1 DBPSK Transmitter Simulink Model 8

16 3.1 Pre-loading Setting Before running the Simulink model, the test message and parameters will be loaded into the workspace by running two files in the MATLAB command window. These parameters will regulate how the Simulink blocks perform while the Simulink model is running. A test message is saved in sdrudpsk_sbits_100.mat and the initial parameters are set in the m-file named sdrudpsk_init. The parameters being set are all listed in the TABLE 2. The details of the parameter settings will be discussed later in the related sections. General simulation Parameters Name of the parameter Setting value comments M 2 M-PSK alphabet size Upsampling 16 Upsampling factor Downsampling 8 Downsampling factor Fs 2e5 Sample rate in Hertz Ts 1/ Fs Sample time in sec FrameSize 100 BarkerLength 13 Number of Barker code symbols DataLength 87 FrameSize-BarkerLength ScramblerBase 2 ScramblerPolynomial [ ] ScramblerInitialConditions [ ] sbit sbit Payload bits RaisedCosineGroupDelay 5 Table 2 Simulink Parameter Settings 9

17 3.2 Bits Generation Figure 3. 2 Bits Generation Subsystem Figure 3.2 shows the Simulink model of the Bits Generation subsystem. This subsystem generates a data stream formed with 100 bits per frame. The unipolar Barker Code block generates a 13-bit barker code header. The signal from workspace block imports the message from the MATLAB workspace and then converts the message sequence to sample based with the Frame Conversion block. The scrambler block is used to keep the balance of zeros and ones in the message sample in order to avoid repetition with the header pattern and make synchronization easier in the receiver. The Matrix Concatenate block is used to attach the header with the message sample to form the data frame. Each frame contains a 13-bit barker code header and 87 payload bits. The test message is generated by loading sdrudpsk_sbits_100.mat. This file contains a vector sbit with size of 870 by 1. It consists of 10 payloads. Each of the payload includes two parts, the message part and the additional zero part. The message contains a string ('Hello ###'). Each test message consists of 9 characters. Each of the characters is 10

18 represented by a 7 bit ASCII binary code. Thus, the length of the test message is 63 bits. For the additional zero part, 24 zeros needs to be added to the payload to ensure the payload has 87 bits. A payload size of 87 bits was selected. A data frame will be formed in the Bits Generation Subsystem. It will add a Barker Code, 13 bits, to make the frame size 100 bits. (Note: the payload length has to be greater than or equal to the message length.) Figure 3.3 shows the data structure. Header (13 bits) Message (63 bits) Additional Zero (24 bits) Payload (87 bits) Frame (100 bits) Figure 3. 3 Data Frame Structure Frame Synchronization The reason for including the Barker code is to provide frame synchronization in the transmission system. The transmitter and the receiver run on two different computers, so they have different clock time. When transmitting a message, the receiver will not receive the exact signal being transmitted at that time. The purpose of frame synchronization is to align the time slot at the receiving end with the corresponding time slot at the transmission end. The process of doing frame synchronization is further clarified in the following steps. First, on the transmitter side, a fixed length symbol pattern, named header, is added to the beginning of each data frame to form a packet. Then the entire packet is converted to a waveform and transmitted through the channel. Later on, the receiver side needs to 11

19 determine where messages begin by searching for that specified header. Then the receiver will remove the header and recover the information message. The most important steps in frame synchronization is to find the header. A good way to do this is to use cross-correlation. Cross-correlation allows two sequences to be compared and find where in time they are most similar. Autocorrelation is the cross correlation of a sequence with itself. So an ideal sequence would have an autocorrelation containing one obvious peak Barker Code The header in the data frame helps the receiver figure out where the actual message begins. In this model, a Barker code is employed as the header because Barker codes have a length of at most 13 and possess low correlation sidelobes. A Barker code is a sequence of N values of +1 and -1 [2] : a j for j = 1,2,, N Such that all Barker codes satisfied the following equation: N v a j a j+v 1, for all 1 v < N. j=1 The equation above can be used to test whether a sequence is a Barker Code or not. For example, the Barker code for N= 3 is given by +1, +1, -1, or: a 1 = 1, a 2 = 1, a 3 = 1 ; 12

20 3 1 2 for v = 1, a j a j+1 = a j a j+1 = a 1 a 2 + a 2 a 3 = ( 1) = 0 1 j=1 j= for v = 2, a j a j+2 = a j a j+2 = a 1 a 3 = 1 ( 1) = 1 1 j=1 j=1 These satisfy the definition equation given above. The autocorrelation function of a Barker code is generated in a MATLAB program to show the low correlation sidelobes property of the Barker Code. Figure 3. 4 Autocorrelation function of a Barker-13 code From the Figure 3. 4, it is obvious that a Barker code is an appropriate sequence to choose because it has an autocorrelation containing one obvious peak way above everything else. So on the receiver side, when doing the autocorrelation with the receiver signals, the header will be found clearly. 13

21 3.2.3 Header Generation The 13-bit length Barker Code is [2]. The original message is ASCII binary code which contains zeros and ones only. In order to generate the data frame containing the Barker Code header and the message, the Barker Code needs to be changed into unipolar form to match with the data message. A Constant block in the Simulink model is used to generate the 13-bit length barker code in unipolar form. The output of the Constant Barker Code block is the 13-bit header The block parameter settings for the unipolar Barker Code is shown in Figure Figure 3. 5 Constant Barker Code Block Parameters 14

22 3.2.4 Data Frame Generation A MATLAB program, sdrudpsk_char2bit.m is run to generate the source bit stream. This is saved as sdrudpsk_sbits_100.mat. The file sdrudpsk_sbits_100.mat is loaded into the MATLAB workspace. The source bit stream is saved in variable called sbit. sbit is used as a source signal through the Signal from Workspace block. The block parameter settings are shown in Figure 3.6. Recall that in the Pre-loading setting, the sample time is set to be 5μs, and the frame size is set to be 100 in the Bits Generation Subsystem. So the samples per frame of the Signal from Workspace block is the frame size minus the Barker Code length. Datalength = = 87 In the Simulink transmitter model, the data frame is up sampled by a Raised Cosine Transmitter Filter which means that each of samples entering in the Raised cosine transmitter filter block results in 16 samples being output. Hence, the frame size of 100 at the Raised cosine transmitter filter block input becomes = 1600 samples at the block output. A frame time is the time the transmitter needs to transmit one frame of data. It is equal to the product of the frame size and sample time: FrameTime = T s FrameSize Upsampling = = 8ms It is calculated in the call back function of transmitter Simulink model. So the sample time of the Signal from Workspace block is: 15

23 Sample time = FrameTime Datalength = 8ms 87 This will allow the header and the data to arrive at the concatenate block in Figure 2.2 at the same time. Figure 3. 6 Signal from Workspace Block Parameters The scrambler is the 4 th block in Figure 3.2. It is used to break up redundancy in the input data which helps to guarantee a balanced distribution of zeros and ones. Figure 16

24 3.7 illustrates the algorithm of the scrambler block. There are M shift registers in Figure 3.7 and all the adders in the figure perform modulo 2 operation. Figure 3. 7 Algorithm of Scrambler [3] P m is the scrambler polynomial parameter which defines whether each of the switches in the scrambler is on or off. Figure 3. 8 Scrambler Block Parameters 17

25 Figure 3.8 shows the parameter settings of the scrambler block. The Calculation base is set to be 2 which indicate the input and output of this block are integers in the range [0, 2-1]. The Scrambler polynomial is [ ] which creates a polynomial: p(z 1 ) = 1 + z 1 + z 2 + z 4 The initial states parameter sets all of the scrambler s shift registers is 0 when the simulation starts. The actual Scrambler algorithm for the specified Scrambler polynomial is shown in Figure 3.9. Figure 3. 9 Scrambler in the Simulink model of Transmitter For example if the input signal is the scrambler operation process is shown in the following table. The values in the shift registers at the specific time are also shown. Note that the input has a single one and seven zeros. However, the output has four of each. Time Input Output Table 3 Example of the scrambler 18

26 A Matrix Concatenate is the last block of the Bits Generation subsystem. It was used to attach the barker code to the beginning of each frame to form a header and frame pair. 3.3 DBPSK Modulation The Simulink DBPSK block is used to differentially encode and modulate the input binary sequence. The output of this block is a baseband representation of the modulated signal. Figure 3.10 illustrates how differential encoding is realized. Figure Differential Encoder [4] d n Incoming data bits e n n Encoding bits e e d, n 1 As mentioned in the background, d n is the message sequence that is being transmitted. It is applied to one input of the XOR logic gate. Another input to the XOR logic gate is the output of the XOR gate e n delayed by one bit. n A Binary Differential Phase Shift Key (DPSK) modulation scheme is implemented in the transmitter. Figure 3.11 shows the parameters setting for the M-DPSK Modulator Baseband block in the Simulink model. The M-ary number is set to be 2 and the input type is set to bit. The Constellation order is set to be Gray coded. 19

27 Figure M-DPSK Modulator Baseband Block Parameter Table 4 lists the input sequence, the encoded sequence and the output sequence. The input waveform in the Simulink model is shown in Figure 3.12 Input d n Sequence Encoded e n Sequence Reference Bit Output Sequence Table 4 Example of the Input and Output Waveform of the DBPSK Modulator 20

28 Figure Input Waveform of the DBPSK Modulator Baseband block The output waveform from the DBPSK Modulator Block is shown in Figure Figure Output Waveform of the DBPSK Modulator Baseband block 21

29 3.4 Root Raised Cosine Transmit Filter Raised cosine filters are used for pulse shaping. Additionally, this block upsamples the symbol. The reason for using Pulse Shaping is that Intersymbol Interference (ISI) can be minimized by decreasing the signal bandwidth. In other words, the Nyquist criterion for ISI cancellation states that at every sampling time if the response due to all symbols except the current symbol is made to equal zero, the ISI can be canceled out. The main parameter of a raised cosine filter is its roll off factor β, which indirectly specifies the bandwidth of the filter. The excess bandwidth BW is β/2t, where T is the symbol period. Figure Raised Cosine Transmit Filter Block Parameter 22

30 In this project, the transmitter and receiver both use a square root raised cosine filters. The combination of these two filters form a raised cosine filter, so ISI can be minimized. Figure 3.14 shows the parameter setting of the Raised Cosine Transmitter Filter Block. The Filter type is set to be Square root. The upsampling factor is 16, the roll off factor is 0.5, and the group delay is 5. The resulting waveform after raised cosine pulse shaping is shown in Figure Output Waveform of the Raise Cosine Filter In order to verify that this waveform represents the output sequence formed in Table 3, MATLAB code, attached in Appendix A, was created. The code generates the output sequence and the root raised cosine transmitter filter response and match the two signals. The result was shown in Figure

31 1.5 1 Transmitted Data Sqrt. Raised Cosine 0.5 Amplitude Time(ms) Figure Output Waveform of the Raise Cosine Filter 3.5 USRP Transmitter The SDRu Transmitter block builds a communication link between Simulink and a Universal Software Radio Peripheral (USRP) on an Ethernet subnetwork. This block takes the data stream from the Simulink transmitter model and sends it to a USRP board. The following diagram shows how Simulink, SDRu transmitter and USRP hardware communicates. Figure Block Diagram of SDRu Transmitter implementation 24

32 Figure SDRu Transmitter Block Parameter Figure 3.18 shows the detailed parameters of the SDRu Transmitter block. The center frequency of the signal out of the USRP hardware RF front end is set at 432MHz. The input sampling frequency of the USRP daughter board must be 100Ms/s, so the product of the sampling frequency, f s, coming out from the Simulink model and the interpolation factor should be 100Ms/s. f s interpolation factor = 100Ms/s The maximum interpolation factor the USRP can provide is 512. In order to have the data processing required by the PC to be as slow as possible, 500 is chosen to be interpolation factor. The corresponding sampling frequency for the Simulink model is 200Kbps. Simulink can show the sample time of the model by choosing display sample time function. Figure 3.20 shows the sample time of the transmitter model when it is running, 25

33 the color red indicate what the sample time is on each of the connection between blocks. Because frames are used, the sample time shown in the Sample Time Legend is actually the frame time. Figure Transmitter Simulink Model in Running Figure Sample Time for the Transmitter Simulink Model The sample time Ts of the Simulink model is the reciprocal of the sampling frequency which is T s = 1 200K = seconds 26

34 Recall for this transmitter, the Simulink model samples are generated in frames of size 1600 after the raised cosine transmitter filter. 1 frame = 1600 samples = 1600 T s = = seconds This is the sample time indicate in the Sample Time Legend. 27

35 SECTION 4: RECEIVER SIMULINK MODEL The purpose of the receiver in this project was to receive the transmitted message Hello ### using a Simulink model associated with the USRP hardware. Figure 4.1 shows the Simulink model of the DBPSK receiver implemented in this project. Figure 4. 1 Receiver Simulink Model The Receiver Simulink model includes a Center Frequency Setting Subsystem, an SDRu Receiver block and a Data Processing Subsystem. The Center Frequency Setting Subsystem allows the received frequency to be manually adjusted in order to match the transmitter frequency. The SDRu Receiver block sets up a link between the Receiver Simulink model and the USRP hardware. The Data Decoding Subsystem processes all of the received data and converts the data to its original form which is the message Hello ###. 28

36 Figure 4.2 shows the detailed Simulink model of the Data Processing Subsystem. It includes, in order, a Matched Filter, a Phase Error Correction Subsystem, a Timing Recovery Subsystem and a Data Decoding subsystem. Figure 4. 2 Data Processing Subsystem When the SDRu Receiver block receives messages from the USRP hardware a Root Raised Cosine Filter plays the role of the matched filter and downsamples the received messages to 2 samples/symbol. The Phase Error Correction Subsystem is then used to track the phase shift in the received messages. After correcting the phase shift in the received message, the Timing Recovery Subsystem is used to recover the symbol timing difference between the transmitted samples and the received samples. When the symbol timing has been corrected, the Data Decoding Subsystem is used to decode the received samples to its original message Hello ###. This report discusses the details of the Timing Recovery Subsystem in the Receiver Simulink model. Other detailed information about the Matched Filter, Phase Error Correction and Data decoding can be found in reference 1. 29

37 4.1 Timing Recovery The Timing Recovery subsystem is designed following the methodology of designing a discrete-time Phase Locked Loop (PLL). The timing recovery PLL is used in order to match the symbol timing at the output of the matched filter on the receiver side to the symbol timing at the transmitter side. There are four subsystems included in the Timing Recovery Subsystem: an Interpolator, a Time Error Detector (TED), a Loop Filter and an Interpolation Controller. The Interpolator and the TED play the role of the Phase Error Detector in the PLL. The Interpolation Controller plays the role of the Direct Digital Synthesizer (DDS) in the PLL. A block diagram of the Timing Recovery Subsystem is showed in Figure 4.3. Matched Filter Output x(nt) Interpolator Data Decoding Time Error Detector Loop Filter Interpolation Controller PLL Figure 4. 3 Timing Recovery Subsystem Block Diagram The timing recovery process works by first using the Interpolator Filter to generate the desired samples, called the Interpolants. Then the Time Error Detector (TED) estimates the timing error in the received interpolants. The timing error is filtered by a Loop Filter to produce a control signal and is then fed into an Interpolation Controller. The Controller 30

38 uses timing error information to control the Interpolator filter to generate the right interpolants from received samples. In this project the Timing Recovery Subsystem is designed based on the reference book Digital Communications -A Discrete- Time Approach [5]. Figure 4.4 shows the Simulink implementation of the timing recovery in this project. Figure 4. 4 Simulink Implementation of Timing Recovery Subsystem Interpolator Interpolation Theory Rate conversion using continuous-time processing can be used to illustrate the interpolation process. It is shown in Figure 4.5 below. x(mt in ) x(t) x(kt o ) DAC Continuoustime filter h I (t) t = kt o Figure 4. 5 Rate Conversion with Continuous Time Filter 31

39 In Figure 4.5, let T in be the sample time at the input of the Interpolator, and T o be the sample time at the output of the Interpolator. The input samples are converted to an impulse train by the digital to analog converter (DAC) and then filtered by a continuoustime interpolating filter with impulse response h I (t). The continuous time output x(t) is + x(t) = x(mt in )h I (t mt in ) m= Where m is the index of the input sample. Let k be the index of the interpolants. The k-th interpolant can be obtained by evaluating x(t) at t = kt o, + x(kt o ) = x(mt in )h I (kt o mt in ) m= Some terms in the above equation are rewritten as follows: h I (kt o mt in ) = h I (( kt o T in m) T in ). Let i be the filter index, i = kt o T in m = m(k) m Where, m(k) = kt o T in is known as the k-th basepoint index [5] which is the sample right before the k-th interpolant. 32

40 Then h I (kt o mt in ), can be rewritten as h I ((i + μ(k))t in ), Where, μ(k) = kt o T in m(k) is the fractional interval which is the time offset between the sample and k-th interpolant and x(mt in ) = x(m(k) i) T in The final result is as follows. The output of the interpolator, k-th interpolant, can be expressed as x(kt o ) = x((m(k) i)t in )h I ((i + μ(k)t in )) i Figure 4.6 shows the relationships between the sample time T in and the interpolation time T o. Figure 4. 6 Sample Time Relations Interpolation Filter In an earlier portion of this section, the mathematical derivation of the k-th Interpolant based on the model shown in Figure 4.5 is discussed. In the Simulink model, 33

41 an interpolation Filter is established to calculate the interpolants. This filter helps adjust the sampling time of the signal without changing the receiver sampling clock. The interpolation filter in this project is designed by using the polynomial method and the piecewise parabolic interpolator [5] is chosen. Recall in Figure 4.5, the continuous-time filter is a polynomial in t. The waveform x(t) is approximated by a second order polynomial (parabolic), x(t) c 2 t 2 + c 1 t + c 0 [5] The desired interpolant requires three input samples to calculate, x(kt o ) = c 2 (kt o ) 2 + c 1 (kt o ) + c 0 A four point interpolating filter was proposed by Mr. Erup with piecewise parabolic impulse response [6]. The filter coefficients equations are: h I ( 2) = αμ(k) 2 αμ(k) h I ( 1) = αμ(k) 2 + (1 + α)μ(k) h I (0) = αμ(k) 2 (1 α)μ(k) + 1 h I (1) = αμ(k) 2 αμ(k) In the above equations, α is the parameter used to control the performance of the piecewise parabolic function. The filter coefficients are listed later in Table 5. i b 2 (i) b 1 (i) b 0 (i) -2 α - α 0-1 -α 1+ α 0 0 -α α α - α 0 Table 5 Farrow coefficients b l (i) for piecewise parabolic interpolator 34

42 The filter output can be expressed as: 1 x(kt o ) = x((m(k) i)t in )h I ((i + μ(k)t in )) i= 2 The piecewise parabolic interpolation filter operates on x((m(k) + 2)T), x((m(k) + 1)T), x(m(k)t), x((m(k) 1)T) to generate an interpolant between x((m(k) + 1)T) and x(m(k)t). But in this project, a causal operation is required. The interpolation filter can operate as a causal filter with a two sample delay. So the interpolation filter operates on x(m(k)t), x((m(k) 1)T), x((m(k) 2)T), x((m(k) 3)T) and generates an interpolant between x((m(k) 1)T) and x((m(k) 2)T). α = 0.5 is chosen in this filter because it significantly reduces the hardware complexity. A special filter structure, namely the Farrow structure, allows simple handling of filter coefficients and efficient hardware implementation [7]. This structure is chosen in the timing recovery subsystem design. A block diagram can be found in reference 5. The actual Simulink model used for the purpose of the interpolator filter is shown in Figure

43 Figure 4. 7 Piecewise parabolic Farrow interpolator structure implementation in Simulink Model Timing Error Detector Zero Crossing Time Error Detector A zero-crossing timing error detector operating at 2 samples/symbol is applied to find the timing error from the input interpolants. The timing error signal is updated at 1 sample/symbol. Assume τ is the unknown timing delay, τ is the estimated timing delay, andτ e = τ τ, is the timing error. When the estimated timing delay τ is earlier than τ, the timing error τ e is positive: τ e > 0 When the estimated timing delay τ is later than τ, the timing error τ e is negative: τ e < 0 The output of the TED is the timing error signal e(k) which is a function of interpolated filter outputs. The following equations are obtain from reference 5. 36

44 e(k) = x ((k 1 2 ) T o + τ ) [a (k 1) a (k)] Where, a (k 1) = sgn{x((k 1)T o + τ )} a (k) = sgn{x(kt o + τ )} A block diagram shown in Figure 4.8 is used to illustrate the Zero-Crossing TED. x(kt o + τ ) x((k 1 2 ) T o + τ ) z -1 z -1 x((k 1) T o + τ ) Error Sign Sign Figure Zero-crossing Time Error Detector Block Diagram Notice that the loop filter and the interpolation controller operate at 2 samples/symbol, but the ZCTED generates a timing error signal of 1 sample/symbol. Thus, an enabled version of the TED is necessary in order to update the proper time error. A strobe signal generated by interpolation controller is used to control the TED. When the strobe is high, the TED output is e(k). When the strobe signal is low, the TED output is 0. The gain of the TED noted as K p, is a function of the excess bandwidth of the matched filter. Figure 4.9 shows the relationship between the TED gain and the excess bandwidth of the Root Raised Cosine Filter. In this project the Root Raised Cosine Filter 37

45 is employed as the matched filter and the excess bandwidth of the Root Raised Cosine Filter is set to be 0.5. So It can be inferred from the figure that K p 2.7 for the Zerocrossing TED in the design when the excess bandwidth is 0.5. Figure 4. 9 K p of the zero-crossing TED as a function of excess bandwidth for the squareroot raised-cosine pulse shape and binary PAM with KE avg = 1 [5] Bit Stuffing When the sample clock has a frequency offset a bit stuffing problem will occur. T > T s 2, where T is sample clock and T s is symbol clock. The phenomenon of bit stuffing is illustrated as follow: The Interpolation Filter generates a desired interpolant at 2 samples/symbol. Because T > T s, a residual timing error accumulates and the fractional interval μ(k) 2 38

46 decreases. Eventually, the accumulated residual timing error exceeds a sample period and the μ(k) decreases to 0 and wraps around to 1. When this occurs, one of the interpolants needed by the ZCTED is never produced by the interpolation filter. This missing interpolant must be inserted into the ZCTED registers manually to ensure proper operation. Figrue 4.10 illustrated the bit stuffing problem. Desired matched filter output Available samples These interpolants are never produced. The TED needs this interpolant, so call it zero and stuff it in Figure An illustration of the relationship between the available matched filter output samples and the desired interpolants In this project this section is realized by generating a MATLAB function in the Simulink Model [9]. The script can be found in the Appendix B of this report Loop Filter A Loop Filter is designed to filter the error signal generated by TED and is fed into the Interpolation Controller. It follows the same approach as the design of the Loop Filter in the PLL. The block diagram of a proportional-plus-integrator Loop Filter is shown in Figure

47 Figure Proportional-plus-integrator Loop Filter The loop constants K 1 and K 2 are given by the equations list below. The detail loop constant derivation can be found in Phase Error Correction Subsystem in reference 1. K p K 0 K 1 = 4ζ ( B nt ζ + 1 ) 4ζ ζ ( B nt ζ + 1 ) + ( B nt 4ζ ζ + 1 ) 4ζ K p K 0 K 2 = 2 4 ( B nt ζ + 1 ) 4ζ ζ ( B nt ζ + 1 ) + ( B nt 4ζ ζ + 1 ) 4ζ In the above equations, B n T is the loop bandwidth, ζ is the damping factor, K p is the gain of the TED and K 0 is the gain of the Interpolation Controller. In this design, the loop bandwidth B n T is set to be 0.01 and the damping filter is set to be 1. According to the TED and Interpolation Controller design respectively, K p = 40

48 2.7 and K 0 = 1. The loop filter design parameters K 1 and K 2 can be obtained by solving the loop constant equations above Interpolation Controller (2.7) ( 1) K 1 = (2.7) ( 1) K 2 = 4 ( ) ( , 1.25 ) + ( ) K 1 = ( ) ( , 1.25 ) + ( ) K 2 = The Interpolation Controller is used to provide the Interpolator Filter with the fractional interval and provide the TED a strobe signal for calculating the proper timing errors. When the Timing Recovery Subsystem PLL is in lock, the interpolants are desired once per symbol. In this project, the Interpolation Control (illustrated within the red box in figure 4.12) is designed by using a decrementing modulo-1 counter and an enable hold. The block diagram and Simulink model are shown in Figure 4.12 and Figure The interpolation controller acts like the DDS in the general PLL. The gain of the interpolation controller is K 0 = 1 because of the decrementing counter. 41

49 Matched Filter Output x(nt) Interpolator Data Decoding Time Error Detector Loop Filter Hold Scale z -1 Mod 1 Counter Interpolation Control Figure Interpolation Controller block diagram [8] Figure Interpolation Controller Subsystem in Simulink Model Modulo-1 Counter The modulo 1 counter in this project has two outputs, one is the strobe signal which controls the TED, Enable Hold and the Modified Buffer, and the other is the fractional interval μ(k) which controls the Interpolation Filter. 42

50 The block diagram is shown in Figure μ(k) Strobe 1/N Mod 1 z -1 + Loop filter output N=2 Figure Block Diagram of Simulink model of Modulo-1 decrementing counter The Modulo 1 Counter is designed to underflow every 2 samples. That is because the receiver matched filter down samples the signal to 2 samples/ symbol and the interpolants are required for every 2 samples. The underflow is the strobe signal which used to control the enable hold subsystem, the TED and the Modified Buffer. When the counter shows an underflow, the TED will receive a strobe signal to produce a timing error and the Enable Hold Subsystem will be activated. Meanwhile the contents of modulo-1 counter, which is the fractional interval μ(k), will be pass through the Enable Hold to the Interpolation Filter. The actual designed Simulink model is shown in Figure Figure Simulink model of Modulo-1 decrementing counter 43

51 Enable Hold The enable hold subsystem is necessary for the interpolation controller because the mod-1 counter updates its contents, the fractional interval, every input sample, but the interpolator operates at 2 samples/symbol. In order to control the interpolator using the proper value for the fractional interval, the Enabled Hold Subsystem recognizes the following regulations: When the strobe signal is high, it passes the input to the output directly. When the strobe signal is low, the Enabled Hold subsystem outputs the previous value. The actual enable hold subsystem generated in this project is shown in Figure Figure Simulink model of Enabled hold subsystem 4.2 Modified Buffer A Modified Buffer Subsystem produces a valid output buffer whenever its buffer is full and sets its DataValid flag to be 1. Otherwise, the output data is not valid and its DataValid flag is set to be 0. In this project, the Modified Buffer Subsystem is used to ensure that the Data Decoding subsystem receives a data frame containing 100 samples corresponding to the transmitter side everytime. 44

52 Figure 4.17 shows the modified buffer subsystem. It includes a Modified Buffer, a sample converter and an AND Logical Operator. The Modified Buffer accumulates 100 samples for each data output, and the AND Logical Operator helps to allow the Data Decoding Subsystem notice that a frame of data needs to be processed when the DataValid flag and the clock are both high. Figure Modified Buffer Subsystem Figure 4.18 shows the Simulink implementation of the Modified Buffer in the Modified Buffer Subsystem. It contains a Delay Line block, a Counter Limited block and a Compare to Constant block. The Delay Line block acts as a buffer. The buffer size is set to be exactly the same as the data frame size which is 100. The Counter Limited Block is used as the counter to count the number of samples in the buffer. As each sample is added to the delay line, the counter increments the number of samples in the line. The Counter Limited Block is initialized to zero and the upper limit of this block is set to be 99. Everytime the buffer accumulated 100 data, the DataValid Flag is set to be 1 by using the Compare to Constant Block and so the Delay Line outputs a frame of size 100 samples to the Data Out port. 45

53 Figure Simulink implementation of the Modified Buffer Figure 4.19 shows the Delay Line block parameter settings. Figure Delay Line block parameter setting. 46

54 Figure 4.20 shows the Counter Limited Block parameter settings. Figure Counter Limited Block parameter setting. 47

55 SECTION 5: CONCLUSIONS This report describes a DPSK transmitter that has been implemented to operate as part of a communication link. Software defined radio, an emerging technology which have the ability to modify a communication system without difficulty, was used in the implementation of this project. The report provides background information on Software Defined Radio, the Universal Software Radio Peripheral and a basic Digital Communication system using Differential Phase Shift Keying. Three types of synchronization are involved in designing the DPSK communication link. The report describes the procedures for preparing a text message for transmitter over the air by using the Universal Software Radio Peripheral and MATLAB Simulink. The main stages contained in the transmitter were Bits Generation which creates the data frame, DPSK Modulation which applies differential encoding to the BPSK modulated the data, and a Root Raised Cosine Transmit Filter which upsamples and shapes the transmitted waveform. As mentioned in the background information, the three types of synchronization used in this communication links design were Frame Synchronization, Carrier Phase and Symbol timing Synchronization. The Frame Synchronization details were explained in the Bits Generation Subsystem of the Transmitter Simulink Model. Section 4 of this report briefly introduced the Receiver Simulink model and a detailed discussed of the Symbol Timing PLL. The special Farrow structure Interpolation Filter was introduced. The Zero Crossing Timing Error Detector, The Loop Filter and the Interpolation Controller were explained as well. In order to test the DPSK communication links, A test message Hello ###, was transmitted and successfully received through this communication link. 48

56 REFERENCES 1. M.S. project Design and Implementation of a DPSK Receiver using Software Defined Radio 2. Barker Code, 3. Scrambler Algorithm, The MathWorks, Inc/Help/Scrambler 4. Differential Encoder, HO3.pdf 5. Michael Rice, Digital Communications -A Discrete- Time Approach, Chapter 8, ISBN L. Erup, F. Gardner, and R. Harris, Interpolation in digital modems. II. Implementation and performance, IEEE Transactions on Communications 7. C. W. Farrow, A continuously variable digital delay element. in IEEE International Symposium on Circuits and Systems 8. EECS 700: Symbol Timing Recovery for Binary PAM 9. MATLAB Example, QPSK Transmitter and Recevier, MathWorks, Inc 49

57 APPENDIX A: MATLAB Code for Square Root Raised Cosine Filter Sample Match %Square Root Raised cosine filter Sample Match for first frame close all; %design the SRRC filter according to simulink model alpha=0.5;%acess bandwidth filterspan=10; sampspersym=16;%upsample factor R=125000;%sample rate; frame time R=1/frame time Fs=R*sampsPerSym; DataLength=100; rcosflt=comm.raisedcosinetransmitfilter('shape','normal','rollofffactor ',alpha,'filterspaninsymbols',filterspan,'outputsamplespersymbol',samps PerSym) %get transmitted sample x=yout(1:100);%get from simulink model tx=10000*(0:datalength-1)/r; %Filter yo=step(rcosflt, [x; zeros(filterspan/2,1)]); %Filter group delay fltdelay=filterspan/(2*r); yo=yo(fltdelay*fs+1:end); to=10000*(0:datalength*sampspersym - 1)/R/16 ; %plot data figure; stem(tx,x,'ko');hold on;%plot sample point plot(to,yo,'r'); %plot shaped pulse xlabel('time(ms)'),ylabel('amplitude'); axis([ ]); legend('transmitted Data', 'Sqrt. Raised Cosine') 50