CALIFORNIA STATE UNIVERSITY, NORTHRIDGE DESIGN AND IMPLEMENTATION OF A DPSK RECEIVER USING SOFTWARE DEFINED RADIO

Transcription

1 CALIFORNIA STATE UNIVERSITY, NORTHRIDGE DESIGN AND IMPLEMENTATION OF A DPSK RECEIVER USING SOFTWARE DEFINED RADIO A graduate project submitted in partial fulfillment of the requirements For the degree of Master of Science in Electrical Engineering By Siqin Cai December 24 Signature Page

2 The graduate project of Siqin Cai is approved: Prof. James Flynn Date Dr. Xiyi Hang Date Dr. Sharlene Katz,Chair Date California State University, Northridge ii

3 Table of Contents Signature Page... i List of Figures...v List of Tables... vii Abstract... viii Chapter : Introduction... Chapter 2: Background... 2 Software Defined Radio... 2 Universal Software Radio Peripheral... 3 Differential Binary Phase Shift Keying... 4 DPSK Encoding... 4 DPSK Decoding... 5 DPSK Coding Example... 6 Frame Synchronization... 7 Chapter 3: DBPSK Receiver... 8 Pre-loading Setting... 8 USRP Simulink Receiver Implementation... Data Processing... 4 Matched Filter... 4 Matched Filter... 6 Downsampling... 8 Square Root Raised Cosine Receive Filter Example... 2 Phase Error Correction... 2 Phase Error Detector Loop Filter Direct Digital Synthesizer Timing Recovery Data Decoding Frame Synchronization Reference Generation... 3 Delay Calculation (MATLAB Function)... 3 iii

4 RX Buffer Data Alignment (MATLAB Function) Phase Ambiguity Correction Phase Offset Estimation (MATLAB Function) Phase Correction DPSK Demodulation... 4 Text Message Decoding Payload Selector Descrambler Payload Selector Chapter 4: Conclusion References Appendix A MATLAB Function sdrudpsk Initialization Appendix B MATLAB Function for Delay Computation Appendix C MATLAB Function for Data Alignment Appendix D MATLAB Function for Phase Offset Estimation Appendix E MATLAB Function for Phase Mapping Appendix F MATLAB Function for Bits to Char Conversion iv

5 List of Figures Figure. Basic Structure of a SDR system... 3 Figure. 2 Differential Encoder for DPSK... 4 Figure. 3 Differential decoder for DPSK... 5 Figure 2. DBPSK Receiver Simulink Model... 8 Figure 2. 2 Block Diagram of the USRP DPSK Receiver... Figure 2. 3 Block Diagram of Simulink, the SDRu Receiver blocks and the USRP hardware interface... Figure 2. 4 SDRu Receiver Parameter Settings... Figure 2. 5 Center Frequency setting Subsystem... 2 Figure 2. 6 Simple Transmitter for Frequency Synchronization... 2 Figure 2. 7 Simple Receiver for Frequency Synchronization... 3 Figure 2. 8 Data Processing Subsystem... 4 Figure 2. 9 Matched Filter subsystem... 5 Figure 2. Parameter Settings of Raised Cosine Receiver Filter... 6 Figure 2. Square root Raised cosine spectra and corresponding time-domain pulses for various values of... 8 Figure 2. 2 Down-sampling operation in the time domain... 9 Figure 2. 3 Comparison between the Transmitted data, Received waveform and Square Root Raised Cosine Filter Output... 2 Figure 2. 4 Phase Error Correction subsystem... 2 Figure 2. 5 Basic structure of the discrete-time PLL Figure 2. 6 Phase Error Detector subsystem Figure 2. 7 Loop Filter subsystem [6] Figure 2. 8 Function Block Parameters: Loop Filter Figure 2. 9 DDS subsystem [6] Figure 2. 2 Simulink Model for the Data Decoding Subsystem Figure 2. 2 Frame Synchronization Subsystem... 3 Figure Reference Generation subsystem... 3 Figure Modulation of the header... 3 Figure Plot h(k) and s(k) Figure Cross-correction Rhs of h(k) and s(k) corresponding to lag time j Figure Use twice of the frame length as the RX buffer length of the received data 35 Figure Parameter setting of the RX Buffer block Figure Extract Integrated Frame from the RX Buffer Figure Phase Ambiguity Correction subsystem Figure 2. 3 Phase Offset Estimation Subsystem Figure 2. 3 Phase Offset Estimation Block Diagram Figure Phase Correction Subsystem v

6 Figure DBPSK Demodulator... 4 Figure Parameter Setting of M-DPSK Demodulator... 4 Figure Received Waveform of the DBPSK Demodulator Baseband block Figure Receiver Output Waveform of the DBPSK Demodulator Baseband block. 42 Figure Received Waveform of the DBPSK Demodulator Baseband block with Marked Points Figure Receiver Output Waveform of the DBPSK Demodulator Baseband block with Marked Points Figure Text Message Decoding Subsystem Figure 2. 4 Single Frame Structure Figure 2. 4 Parameter Setting of the Payload Selector block Figure Descrambler in the Simulink model of the Receiver Figure Parameter Setting of the Descrambler Figure Parameter Setting of the Message Selector block... 5 Figure Display the decoded data in MATLAB command window... 5 vi

7 List of Tables Table Differential encoding and decoding... 6 Table 2 Simulink Parameter Initialization Setting... 9 Table 3 Phase Mapping Table Table 4 DBPSK decoding Table 5 Example of the descrambler vii

8 Abstract DESIGN AND IMPLEMENTATION OF A DPSK RECEIVER USING SOFTWARE DEFINED RADIO By Siqin Cai Master of Science in Electrical Engineering The objective of this project is to design and implement a differential phase shift keying (DPSK) communications receiver using software defined radio (SDR). This receiver is part of an over the air DPSK communications link. The transmitter is discussed in a separate project report. The receiver system consists of a Matched Filter, a Phase Error Correction subsystem, a Timing Recovery subsystem and a Data Decoding subsystem. Concise description and implementation details are expressed in the text. For this project, communications models have been employed using MATLAB Simulink. viii

9 Chapter : Introduction The goal of this project is to design and implement a differential phase shift keying (DPSK) communications receiver using software defined radio (SDR). This receiver is part of an over the air DPSK communications link. The transmitter for this link was designed and implemented in another graduate project and is documented in Reference. The receiver has been implemented using Mathworks Simulink in conjunction with the Ettus Universal Software Radio Peripheral (USRP). This approach to the implementation of a SDR receiver allows for flexibility and provides a mechanism to modify or update the receiver without modifying any hardware. The receiver includes subsystems that provide the necessary synchronization with the transmitter. Chapter 2 of this report presents some background information on Software Defined Radio (SDR), the Universal software Radio Peripheral (USRP), Differential Binary Phase shift Keying (DBPSK) and Frame Synchronization. Chapter 3 presents the receiver design in terms of its five subsystems. Chapter 4 includes the summary and conclusions for this project and suggestions for future work.

10 Chapter 2: Background Software Defined Radio Software defined radio (SDR) is a new technology for implementing radio communication system, where components that have been typically implemented in hardware (e.g. mixer, filters, amplifiers, modulators/demodulators, detectors, etc.), are instead implemented by means of software on a personal computer or embedded system.[3] It is different from the traditional hardware radio. Most of the signal processing including modulation are done in software. Thus, the hardware can be eliminated and the software can be moved as close to the antenna as possible. This new technology encompasses many areas of electrical engineering, such as communication, signal processing antennas, digital design, radio frequency (RF), etc. In today s fast paced technology world, implementing new technology occurs quite often. Because of this, Software Defined Radio (SDR) technology emerged. A basic SDR system may consist of a personal computer (PC) equipped with a sound card which supports a speaker, an analog-to-digital converter (ADC) which changes the signal to a digital form that can be understood by the PC, preceded by a RF front end which receives the signal. Significant amounts of signal processing can be modified by changing the software in the PC. However, the hardware remains the same. A visual representation of the basic structure of a SDR system is shown in Figure.. 2

11 PC ADC Figure. Basic Structure of a SDR system Software Defined Radio Systems are advantageous because they make communication systems reconfigurable in a sense that allows flexibility. This flexibility is due to the use of software for large portion of the signal processing. SDR is also upgradable and modifiable, making it suitable to make alterations without altering the hardware in any way. Universal Software Radio Peripheral The Universal Software Radio Peripheral (USRP) [4] is a range of softwaredefined radios designed and sold by Ettus Research and its parent company, National Instruments. Most USRPs connect to a host computer through a high-speed link, which the host-based software uses to control the USRP hardware and transmit/receive data. The Ettus Research USRP N2 and N2 are the highest performing class of hardware of the USRP family of products, which enables engineers to rapidly design and implement powerful, flexible software radio systems. The N2 and N2 hardware is ideally suited for applications requiring high RF performance and great bandwidth. [5] For more details on the USRP, see reference. 3

12 Differential Binary Phase Shift Keying Differential phase shift keying (DPSK) is a common form of phase modulation. It may be viewed as the non-coherent version of Phase Shift Keying (PSK). DPSK does not require a coherent reference signal at the receiver by combining two basic operations at the transmitter. The key idea is to transmit the difference between two adjacent sequences, not the sequences themselves. DPSK Encoding A differential encoder can be constructed with a modulo2 adder (XOR) and a delay (see Figure.2). In DPSK, the sequences are modulated onto the phase change of the carrier. A phase change of π between adjacent symbol intervals represents the bit value while no phase change across adjacent symbol intervals represents the bit value. dn XOR symbol delay Z- an Figure. 2 Differential Encoder for DPSK d n Incoming data bits a n Encoded data bits d a k a k a k a k d k, k d k a k a k 4

13 DPSK Decoding A differential decoder can be constructed with a modulo2 adder (XOR) and a delay (see Figure.3). The bit value represents the phase change is π between the two adjacent symbols while the bit value represents no phase change between the two adjacent symbols. XOR an dn symbol delay Z- Figure. 3 Differential decoder for DPSK a n Incoming data bits d n Pre-processed bits a dˆk a k dˆk a k a k, k a k dˆk a k 5

14 DPSK Coding Example Note that the encoded sequence a k and the output sequence are matched to each other. The difference is that the encoded sequence is using unipolar encoding, while the output sequence is using bipolar encoding. A Differential coding example is shown in Table. Input Sequence dk Encoded Sequence ak DPSK Encoding DPSK Decoding Decoding with correct channel polarity Received Sequence - - Input Sequence a k Decoded Sequence Reference bit Output Sequence - - d k Table Differential encoding and decoding d k Decoding with incorrect channel polarity Received Sequence - Input Sequence a k Decoded Sequence 6

15 Frame Synchronization In telecommunications, frame synchronization is necessary in order to receive a signal. In a stream of framed data, frame alignment signals are used to identify the data bits within the frame which must be extracted for decoding or retransmission. All digital data streams have some sort of frame structure. The data stream is generally organized into uniformly sized groups of bits. Frame synchronization is usually accomplished by the transmitter. A simple frame synchronization aid is to add a short pattern of bits to the data stream. This short pattern of bits can appear at the beginning of the data stream which will make it a header, or at the end of the data stream which will make it a trailer. When a receiver receives the incoming data, it will synchronize the data stream using the header or trailer. A simple example is managing telephone numbers. If all the digits of the telephone numbers come together, such as , it is extremely hard to tell where the telephone number starts and ends. However, if it implements a frame to modify this stream of data, such as (88) , (88) 32698, (88) , the (88) can be treated as the frame header, while the comma can be used as the trailer. 7

16 Chapter 3: DBPSK Receiver The DBPSK Receiver implemented in this project and shown in Figure 2. receives and processes the signals transmitted from the DBPSK Transmitter. It includes two parts, the SDRu receiver block and Data Processing subsystem. Figure 2. DBPSK Receiver Simulink Model Pre-loading Setting Before running the Simulink model, the parameters will be loaded into the workspace by running the following file in the MATLAB command window. All the initial parameters are set in the m file named sdrudpsk_init. The MATLAB function script is shown in the Appendix A. The parameters are all listed in the Table 2. 8

17 Name of the parameter M Upsampling Downsampling Fs Ts FrameSize BarkerLength DataLength ScramblerBase ScramblerPolynomial ScramblerInitial Conditions sbit RxBufferedFrames RaisedCosineFilterSpan RaisedCosine GroupDelay K A PhaseError DetectorGain PhaseRecoveryGain TimingError DetectorGain TimingRecoveryGain General simulation Parameters Setting value Comments 2 M-PSK alphabet size 6 Upsampling factor 8 Downsampling factor 25 Sample rate in Hertz Sample time in sec sdrudpsk.fs Number of modulated symbols per frame Transmitter Parameters 3 Number of Barker code symbols FrameSizeNumber of data payload bits per frame BarkerLength 2 [ ] [ ] sbit Payload bits Receiver Parameters Received buffer length (in frames) 5 Group delay of Raised Cosine Tx/Rx filters (in symbols) 2 2*K*A2 Kp for Fine Frequency Compensation PLL, determined by 2KA^2 K for Fine Frequency Compensation PLL Kp for Timing Recovery PLL, determined by 2KA^2*2.7, 2.7 is for raised cosine filter with roll-off factor.5 2.7*2*K*A2 - K for Timing Recovery PLL, fixed due to modulo- counter structure MessageLength 63 Table 2 Simulink Parameter Initialization Setting 9

18 USRP Simulink Receiver Implementation SDRu Receiver Matched Filter Phase Error Correction Timing Recovery Data Decoding Data Processing Figure 2. 2 Block Diagram of the USRP DPSK Receiver The SDRu Receiver block (highlighted in Figure 2.2) is also shown in Figure 2.3 builds a communication link between Simulink and the Universal Software Radio Peripheral (USRP) via Ethernet. This block receives signal and controls data from a USRP board using the Universal Hardware Driver (UHD) from Ettus ResearchTM. The SDRu Receiver [2] block is a Simulink source that receives data from the USRP board and outputs a column vector signal of fixed length. The following block diagram illustrates how Simulink, the SDRu Receiver blocks and the USRP hardware interface. Receive Antenna USRP Receiver Hardware SDRu Receiver Block Simulink Model Figure 2. 3 Block Diagram of Simulink, the SDRu Receiver blocks and the USRP hardware interface

19 Figure 2. 4 SDRu Receiver Parameter Settings Figure 2.4 shows the detailed parameters of the SDRu Receiver block. The center frequency source is set to Input port. It takes the output of the Center Frequency Setting subsystem as seen in Figure 2.5 to set the frequency of the USRP. Before running the DBPSK Receiver, the frequency offset needs to be found to achieve frequency synchronization. This is accomplished by setting up a simple transmitter (see Figure 2.6) and a simple receiver (see Figure 2.7). Using the transmitter to transmit a sine wave, (i.e.

20 sin [2π ()t]). The receiver frequency can be adjusted by checking the Spectrum Scope and adjust by the Slider Gain until the scope frequency matches Hz. Figure 2. 5 Center Frequency setting Subsystem Figure 2. 6 Simple Transmitter for Frequency Synchronization 2

21 Enabled Subsystem Figure 2. 7 Simple Receiver for Frequency Synchronization The center frequency is set to be 432 MHz, and the frequency offset is set to be the same as the one found in the frequency synchronization procedure above. The decimation is set to be 5 to match the SDRu transmitter. The sample time is set to be 5/6. The user Frame length is set to be five times the product of the FrameSize ( symbol/frame) and the Upsampling rate (6 samples/symbol), which is *6=6 samples/frame. This is long enough to include at least two full frames. 3

22 Data Processing The Data Processing subsystem as shown in Figure 2.8 includes four main subsystems. The Matched Filter uses a Square root Raised Cosine Receive Filter with a rolloff factor of.5 and downsampling by a factor of eight; the Phase Error Correction uses a Phase Locked Loop (PLL) to correct the phase error; the Timing Recovery downsamples the input signal and makes the symbol decisions at the optimum sampling time; and the Data Decoding synchronizes the frame, fixes the phase ambiguity caused by the Phase Error Correction subsystem, demodulates the data, and decodes the text message. These subsystems will each be discussed below. Figure 2. 8 Data Processing Subsystem Matched Filter SDRu Receiver Matched Filter Phase Error Correction Timing Recovery Data Processing Figure 2. 2 Block Diagram of the USRP DPSK Receiver 4 Data Decoding

23 In signal processing, a matched filter (highlighted in Figure 2.2) is achieved by correlating an identified signal with an unidentified signal to distinguish the presence of the pattern in the unidentified signal. The Matched Filter subsystem as shown in Figure 2.9 includes two elements which are the Frame Conversion block and the Raised Cosine Receive Filter block. The Frame Conversion block converts the data type from sample based to frame based. The Square root Raised Cosine Receive Filter as shown in Figure 2.9 provides the matched filter for the received waveform. Figure 2. 9 Matched Filter subsystem The parameter settings are given in Figure 2.. It involves two signal-processing of the received data: matched filter and down-sampling. 5

24 Figure 2. Parameter Settings of Raised Cosine Receiver Filter Matched Filter The matched filter is a linear filter that is designed to detect the presence of a waveform of known structure buried in additive noise. The square root raised cosine 6

25 pulse shaping p(t ) is implemented in the transmitted waveform. The received waveform is then expressed as: v(t ) Ap (t t ) n(t ) where t is the propagation time delay, A is an amplitude scaling factor and n(t ) is additive noise. In order to detect the received signal, a square root raised cosine receiver filter is used as a matched filter. The square root raised cosine p(t ) and its Fourier transform P( f ) are given by: t sin Ts t cos t Ts 4 Ts 2 p(t ) 2 Ts t 4 Ts Ts T T P( f ) s cos s f 2Ts 2 2Ts f 2Ts 2Ts f 2Ts f where is the rolloff factor in the interval, Ts is the symbol time. 7

26 Figure 2. Square root Raised cosine spectra and corresponding time-domain pulses for various values of Downsampling Downsampling is a process of decreasing the sampling rate by N of a sequence. This process is illustrated in Figure 2.2 8

27 Original Signal x(m) x(mn), Where N = x(mn), Where N = Figure 2. 2 Down-sampling operation in the time domain Since the transmitter increased the sampling rate by 6, the receiver needs to decrease the sampling rate by 6 to determine the original signal or sample per symbol. The downsampling process is split into two parts in this system. The input of the Timing Recovery subsystem (see Chapter 3 Section 3 Timing Recovery) requires that its input be oversampled by two in order to process the timing correction. Thus, the downsampling rate of the Square root Raised Cosine Receive Filter will be set to 8. The remaining downsampling (factor of 2) will be handled in the timing Recovery subsystem. Thus the total downsampling rate will be 6 (2*8) which matches the upsampling rate of the transmitter. 9

28 Square Root Raised Cosine Receive Filter Example Figure 2.3 provides a view of the transmitted waveform and its relationship to the data. The black stars are the bipolar data values. The square root raised cosine receiver filter output is shown as the blue waveform and the square root raised cosine transmit filter output is the pink wave form. Note that the data values lie on the waveform representing the receiver filter s output. Transmitted Data Rcv Filter Output Sqrt.Root Raised Cosine Filter Output 2.5 Amplitude Time (ms) Figure 2. 3 Comparison between the Transmitted data, Received waveform and Square Root Raised Cosine Filter Output 2

29 Phase Error Correction SDRu Receiver Matched Filter Phase Error Correction Timing Recovery Data Decoding Data Processing Figure 2. 2 Block Diagram of the USRP DPSK Receiver The Phase Error Correction subsystem (highlighted in Figure 2.2) is shown in greater detail in Figure 2.4. The PLL has three main parts, observed from the right of the figure towards the left, the Phase Error Detector (PED), the loop filter and the Direct Digital Synthesizer (DDS). This figure shows a very common design of the Phase Error Correction Subsystem. For the purpose of this project Figure 2.4 was derived from Digital Communications A Discrete-Time Approach [6] Appendix A. Figure 2. 4 Phase Error Correction subsystem 2

30 The Phase Error Correction Subsystem tracks the phase shift of the input signal with a phase-locked loop (PLL). [6] The basic structure of a PLL is shown in Figure 2.5. The Phase Error Detector (PED) computes a function of the phase difference between the input and the output of the DDS. The phase error is filtered by the loop filter and is fed to the input of the DDS. The DDS is a discrete-time version of the voltage control oscillator (VCO) since this system is doing digital signal processing. Phase Detector Loop Filter v(nt ) Direct Digital Synthesizer Figure 2. 5 Basic structure of the discrete-time PLL Phase Error Detector The PED subsystem as shown in Figure 2.6 outputs the phase difference between the two input data. Assuming that input data is referred to as In, the phase error e [6] is expressed as: e sign(real ( In)) imag ( In) sign(imag ( In)) real ( In) 22

31 Figure 2. 6 Phase Error Detector subsystem Loop Filter The Loop Filter subsystem is shown in Figure 2.7. It uses a tunable proportionalplus-integral loop filter. It filters the error signal and feeds it into the DDS. Figure 2. 7 Loop Filter subsystem [6] The expression of the loop filter transfer function is expressed as: 23

32 F( z ) K K2 z The parameters setting as shown in Figure 2.8 has five parameters for the loop filter. Figure 2. 8 Function Block Parameters: Loop Filter The Loop Bandwidth BnTs (normalized by the sample rate) and the Loop Damping Factor are tunable for the Loop Filter. The default value for the normalized loop bandwidth is set to. and the default value for the damping factor is set to unity (critical damping) so that the PLL quickly locks to the intended phase while introducing 24

33 little phase noise. Kp is the gain of the phase detector, K is the gain of DDS. The values are given during the initialization (see Table 2). The loop transfer function for the proportional-plus-integrator loop filter [6] is expressed as: H a ( s) 2 n s n 2 s 2 2 n s n 2 where n is the natural frequency H d ( s) K p K ( K K 2 ) z K p K K z 2 2 K p K ( K K 2 ) z K p K K z 2 2 Applying Tustin s equation: T z s 2 z 2 n n2 n2 n n2 2 z z z 2 n n 2 n n 2 n n H a 2 n 2 n n2 2 T z 2 z z 2 n n2 2 n n2 Where n nt 2 Solving the loop constants gives 25

34 K p K K K p K K2 4 n 2 n n2 4 n2 2 n n2 The expression for the loop constants are a function of the damping factor, the loop bandwidth BnTs and the number of samples per symbol N n B n Ts N 4 Solving for K and K2 4 B n Ts N 4 K K p K B n Ts 2 B n Ts N N B n Ts 4 2 N 4 K2 K p K B n Ts 2 B n Ts N N We obtain K.79, K for the filter. 26

35 Direct Digital Synthesizer The Direct Digital Synthesizer subsystem is shown in Figure 2.9. The DDS output is A cos n (nt ), where (nt ) is related to the input v(nt ) via the phase relationship as: (nt ) K n v(kt ) k Figure 2. 9 DDS subsystem [6] The transfer function of DDS is expressed as: H DDS ( z ) K 27 z z

36 Timing Recovery SDRu Receiver Matched Filter Phase Error Correction Timing Recovery Data Decoding Data Processing Figure 2. 2 Block Diagram of the USRP DPSK Receiver The Timing Recovery subsystem (highlighted in figure 2.2) corrects the timing error in the received signal. The input of the Timing Recovery subsystem is the output of the Phase Error Correction subsystem, which has the same sampling rate (oversampled by two) as the output of the Matched Filter subsystem. The Timing Recovery subsystem generates one output sample for every two input samples. For a complete description of the Timing Recovery subsystem, see Reference. 28

37 Data Decoding Matched Filter SDRu Receiver Phase Error Correction Timing Recovery Data Decoding Data Processing Figure 2. 2 Block Diagram of the USRP DPSK Receiver The Data Decoding subsystem as shown in Figure 2.2 performs frame synchronization, phase ambiguity correction, phase mapping, DPSK demodulation and the text message decoding. Header Payload Figure 2. 2 Simulink Model for the Data Decoding Subsystem Frame Synchronization The purpose of the Frame synchronization subsystem is to detect the alignment symbol. The Frame synchronization subsystem as shown in Figure 2.2 includes Reference Generation, Delay Calculation and Data Alignment. 29

38 Figure 2. 2 Frame Synchronization Subsystem Reference Generation The Reference Generation subsystem (see Figure 2.22) regenerates a DPSKmodulated unipolar Barker code sequence. Figure Reference Generation subsystem It uses the same Barker code that was used to create the transmitted frame header. The output of this subsystem is referred to as the Modulated Frame Header. This 3

39 Modulated Frame Header (see Figure 2.23) will be compared to the received data to find the delay caused by the system. DBPSK Modulator Barker Code Modulated Frame Header 3 bits 3 bits Figure Modulation of the header Delay Calculation (MATLAB Function) The Delay Calculation function block shown in Figure 2.2 is a MATLAB Function. It finds the correlation between the received data and the DPSK modulated frame header (output of the Reference Generation subsystem). The Delay Calculation MATLAB function script is shown in the Appendix B. A cross-correlation function is used to measure the similarity between two input signals. One application of the cross-correlation function is to find the time shift between two signals, this is the delay that is experienced between the transmitter and the receiver. If h (t) is the N bits of the modulated frame header and s (t) is the M bits of the received signal denoted as: h(t)=[h-,,h,h,,hk,,hn] s(t)=[s-,,s,s,,sk,,sm] 3

40 For discrete functions, the cross-correlation [7] is defined as: R hs j h k sk j k The time lag j at the maximum value of the cross-correlation R hs j is equal to the time shift caused by the system. The index of the peak amplitude is used in the delay function. The calculation of the delay is the following: Delay j An example of this calculation is shown here. Assume that the header size is 7 bits and the frame size is 2 bits as shown below. The goal is to find where the header is in the buffer and what the delay is. Header (7 bits) [- - - ] Buffer (2 bits) [ ] 32

41 Header h(k) k Buffer k s(k) Figure Plot h(k) and s(k) The Plotted h (k) and s (k) are shown in Figure If these two sequences are applied to the cross-correlation function, the output is shown in Figure

42 Cross-correlation of the Header h(k) and Buffer s(k) 8 j = -4 Rhs = 7 6 R hs j Figure Cross-correction Rhs of h(k) and s(k) corresponding to lag time j Figure 2.25 shows the maximum value of the cross-correlation R hs max is 7 and the time lag j at R hs max is -4: Recall the header and buffer Delay= 4 Header Thus, the header is correctly identified as having a delay of

43 RX Buffer The RX Buffer shown in Figure 2.2 stores two frames. This is required so that a complete header and payload are in the buffer at any time as shown in Figure 2.26 in case that contiguous data across two adjacent frames. This guarantees that a complete frame is somewhere in the buffer. Header Payload Frame length bits Header Payload Header Payload Header Payload RX Buffer length=2*frame length 2 bits Figure Use twice of the frame length as the RX buffer length of the received data Figure Parameter setting of the RX Buffer block Figure 2.27 shows the parameter settings of the RX Buffer block. In this example, the frame length is, this value is contained in the variable sdrudpsk.framesize. RX Buffer length = sdrudpsk.framesize*2 = *2 = 2 35

44 Data Alignment (MATLAB Function) The Data Alignment Function block shown in Figure 2.2 takes the data from the RX Buffer, and uses the computed delay to find the frame header. Figure 2.28 shows how the frames appear in the RX Buffer. The output data is a complete frame with the barker code as the frame header. The Data Alignment MATLAB function script is shown in Appendix C. Computed Delay Header Payload Header Payload Complete Frame Header Payload Header Payload RX Buffer length Figure Extract Integrated Frame from the RX Buffer Phase Ambiguity Correction Figure Phase Ambiguity Correction subsystem The Phase Ambiguity Correction subsystem as shown in Figure 2.29 performs Phase Offset Estimation and Phase Correction. 36

45 Phase Offset Estimation (MATLAB Function) The Phase Error Correction subsystem (see Chapter 3 Section3 Phase Error Correction) as shown in Figure 2.4 includes a phase PLL which locks to the received data with a phase shift of or 8 degrees. This can result in the problem of the phase ambiguity. The phase offset estimation subsystem as shown in Figure 2.3 resolves the problem of the phase ambiguity by estimating the phase shift of the received data and making a phase offset decision. Figure 2. 3 Phase Offset Estimation Subsystem Figure 2.3 illustrates the algorithm for the phase offset estimating and the phase offset mapping. The system selects the 3 header bits of the received frame, and the conjugate of the modulated frame header (see Chapter 3 Section 3 Reference Generation), and calculates the product of these two sequences. The non-biased estimation is used to get the estimated phase offset. The MATLAB function script is shown in the Appendix D. 37

46 Modulated Frame Header x(t) Conjugation x*(t) z(t) Received Frame ( bits) Select 3 Header bits E(ejφ) Mean Phase φ Mappin y(t) Figure 2. 3 Phase Offset Estimation Block Diagram Assume that the modulated frame header is expressed as: x(t ), t,2,..., N The received frame header has not only a phase offset, but also noise n(t ). Thus, it can be expressed as: y(t ) x(t )e j n(t ), t,2,..., N The noise is assumed to be addictive white Gaussian noise (AWGN) with a distribution N (, σ2) The product of y(t ) and the conjugate of x(t ) is expressed as: z(t ) x* (t ) y(t ) x(t ) e j x* (t )n(t ) 2 If a non-biased estimator [8] is applied, the output is expressed as: E z(t ) E[ x(t ) e j x* (t )n(t )] E[ x(t ) e j ] E[ x* (t )n(t )], 2 2 For AWGN, E[n(t )] E z(t ) E[ x(t ) e j ] 2 Thus, the estimated phase is expressed as: est angle( E[ x(t ) e j ]) 2 38

47 Since the system is using DBPSK demodulation. The Phase Offset Detection function block maps the estimated phase to either or π using the mapping shown in Table 3. The MATLAB function script is shown in the Appendix E. Input Phase Range Mapping Output (-π/2, π/2) (π/2, 3π/2) π Table 3 Phase Mapping Table Phase Correction Figure Phase Correction Subsystem The Phase Correction subsystem shifts the input data by the estimated phase offset as shown in Figure

48 DPSK Demodulation The DPSK Demodulation block (see Figure 2.33) demodulates the corrected data with a DPSK demodulator. A Binary Differential Phase Shift Keying (DPSK) demodulation scheme is implemented in the receiver. A Simulink model which compares the input to the output of the demodulation is shown in Figure The parameter settings of the M-DPSK Demodulator is shown in Figure The M-ary number is set to be 2 and the input type is bit. The received waveform in the presence of noise in the Simulink model is shown in Figure 2.35, while the receiver output waveform in the Simulink model is shown in Figure Figure DBPSK Demodulator 4

49 Figure Parameter Setting of M-DPSK Demodulator 4

50 Figure Received Waveform of the DBPSK Demodulator Baseband block Figure Receiver Output Waveform of the DBPSK Demodulator Baseband block Check the values of both waveforms from t =.5 to t = Figure Received Waveform of the DBPSK Demodulator Baseband block with Marked Points 42

51 Figure Receiver Output Waveform of the DBPSK Demodulator Baseband block with Marked Points In Figure 2. 37, the same input waveform (Frame 4) is shown as the blue waveform. The red circles are the actual bipolar data values. In Figure 2.38, the same output waveform (Frame 4) is shown as the blue waveform. The red circles are the demodulated data. Recall the DPSK demodulation scheme in Chapter 2 Section 3, a n Incoming data bits d n Pre-processed bits a dˆk a k dˆk a k a k, k a k dˆk a k The DBPSK decoding for Frame 4 is shown in Table 4. Received data Input data a n Output data d n Reference bit Table 4 DBPSK decoding The result of the output data is correct based on the theorem of the DPSK demodulation. 43

52 Text Message Decoding Figure Text Message Decoding Subsystem The Text Message Decoding subsystem as shown in Figure 2.39 consists of Payload Selector, Descrambler and Message Selector. Payload Selector The single frame structure is shown in Figure 2.4. Based on the frame structure, the first 3 bits of the frame consist of the header. The payload has 87 bits in total. The first 63 bits of the payload are the message bits. The last 24 bits have nothing to do with the message and are just zeros. Header (3 bits) Message (63 bits) Zeros (24 bits) Payload (87 bits) Frame ( bits) Figure 2. 4 Single Frame Structure 44

53 The Payload Selector (see Figure 2.4) selects the payload bits from the 4th bit to the th bit of the frame. It does this by setting the index value from sdrudpsk.barkerlength+ to sdrudpsk.framesize In this Simulink model, the Barker length is 3 and the frame size is. These two values are stored in the initial parameter settings of sdrudpsk.barkerlength and sdrudpsk. FrameSize (see Table 2). sdrudpsk.barkerlength+ = 3 4 sdrudpsk.framesize= The Payload starts at 4th bit and ends at the th bit of the frame. 45

54 Figure 2. 4 Parameter Setting of the Payload Selector block Descrambler The Descrambler block descrambles the input signal. It is the inverse of the Scrambler block. Since a Scrambler block is applied in the transmitter, a descrambler is required to descramble the received signal. The 87 payload bits are descrambled through the descrambler. 46

55 Figure shows the descrambler schematic, the descramble polynomial is expressed as: P( z ) P ( Pz P2 z 2 P3 z 3 P4 z 4 ) Input data P 2 P 3 P2 4 P3 P4 + - Descrambled data Figure Descrambler in the Simulink model of the Receiver Figure 2.43 shows the parameters of the Descrambler which matches the settings of the Scrambler in the transmitter. The Scramble polynomial is [ ] which creates a polynomial: P( z ) ( z z 2 z 4 ) 47

56 Figure Parameter Setting of the Descrambler For example if the input signal is the descrambler operation process is shown in Table 5. The initial contents of the shift register are fixed. When the first bit of the sequence arrives, this bit is differenced mod-2 with the mod-2 sum of the initial value of stages, 2 and 4. This difference becomes the first bit of the output sequence. At the same time, the shift registers are shifted up one bit, the content of shift register 4 goes out, the content of shift register 3 goes to shift register 2, the content of shift register 2 goes to shift register, and the next bit of input sequence is appeared. The same procedure is repeated. 48

57 Time Input Sequence Shift register Shift register 2 Shift register 3 Shift register 4 Output Sequence Table 5 Example of the descrambler Payload Selector The Message Selector (see Figure 2.43) selects message bits which are the first 63 bits of the payload. 49

58 Figure Parameter Setting of the Message Selector block It selects the index value from to sdrudpsk.messagelength. In this Simulink model, the message length is 63. The value is stored in the variable sdrudpsk.messagelength (see Table 2). The Message starts at st bit of the payload and ends at the 63th bit. The selected message bits were extracted and stored in a workspace variable. A test message Hello ### was transmitted through this Simulink model, where ### is a repeating sequence of '', '', '2',..., '9'. Run sdrudpsk_bits2char.m (see Appendix F), all of the stored bits will be converted to characters and displayed at the MATLAB command window. 5

59 The test result is shown in Figure Figure Display the decoded data in MATLAB command window 5

60 Chapter 4: Conclusion This project describes the steps taken in building the receiver portion of a DPSK communication link. Most of the signal processing including modulation was done in software. This project designed and implemented a DPSK communications link using software defined radio. Some background information was needed to complete this project, including knowledge of Software Defined Radio, Universal Software Radio Peripheral, Differential Phase Shift Keying, and Frame Synchronization. Some of the background information is presented in greater detail in another graduate report, and documented in Reference. The receiver presented five subsystem designs which include the USRP Simulink Receiver Implementation subsystem, Matched Filter subsystem, Phase Error correction Subsystem, Timing Recovery subsystem and Data Decoding subsystem. These were implemented in MATLAB Simulink for this project. The USRP Simulink Receiver Implementation subsystem illustrated how to setup the SDRu Receiver block to build a communication link between Simulink which is software and the Universal Software Radio Peripheral (USRP) which is hardware. The Matched Filter subsystem presented downsampling procedure achieved by a Square Root Raised Cosine Filter. The Phase Error correction Subsystem implemented a phase locked loop (PLL) to track the phase shift of the input signal. The Timing Recovery subsystem corrected the timing error in the received signal. The Data Decoding subsystem performed frame synchronization, phase ambiguity correction, phase mapping, DPSK demodulation and the text message decoding. The receiver obtained a signal, processed and decoded the signal into a message. The message Hello ### is just the first of many that can be received due to of the effort completed in this project. 52

61 References [] Design and Implementation of a DPSK Transmitter Using Software Defined Radio, Yan Jin, November 24 [2] [3] Architectures, Systems and Functions (Markus Dillinger, Kambiz Madani, Nancy Alonistioti) Page xxxiii (Wiley & Sons, 23, ISBN ) [4] Quinn Norton. "GNU Radio Opens an Unseen World". Wired.com. Retrieved [5] [6] Michael Rice, "Digital Communications - A Discrete-Time Approach", Prentice Hall, April 28. [7] [8] Hazewinkel, Michiel, ed. (2), "Unbiased estimator", Encyclopedia of Mathematics,Springer, ISBN

62 Appendix A MATLAB Function sdrudpsk Initialization sdrudpsk_init.m function SimParams = sdrudpsk_init % Set simulation parameters load sdrudpsk_sbits_; % length 87 % General simulation parameters SimParams.M = 2; % BPSK SimParams.Upsampling = 6; % Upsampling factor SimParams.Downsampling = 8; % Downsampling factor SimParams.Fs = 2e5; % Sample rate in Hertz SimParams.Ts = /SimParams.Fs; % Sample time in sec SimParams.FrameSize = ; % Number of modulated symbols per frame SimParams.BarkerLength = 3; % Number of Barker code symbols SimParams.DataLength = SimParams.FrameSize SimParams.BarkerLength; % Number of data payload bits per frame SimParams.ScramblerBase = 2; SimParams.ScramblerPolynomial = [ ]; SimParams.ScramblerInitialConditions = [ ]; SimParams.sBit = sbit; % Payload bits SimParams.RxBufferedFrames = ; % Received buffer length (in frames) K = ; A = /sqrt(2); SimParams.PhaseErrorDetectorGain = K*A^2; SimParams.PhaseRecoveryGain = ; % K_ for Phase Error Correction SimParams.TimingErrorDetectorGain = K*A^2; SimParams.TimingRecoveryGain = -; % K_ for Timing Recovery PLL SimParams.RaisedCosineFilterSpan = ; SimParams.RaisedCosineGroupDelay = 5; % Group delay of Raised Cosine SimParams.MessageLength = 63; 54

63 Appendix B MATLAB Function for Delay Computation ComputeDelay.m function delay = ComputeDelay(Ref,Data) % Calculate the cross-correlation of two signals % Find the delay of the Data % % Input: % Ref - Correct frame header % Data - Symbol-spaced data % Output: % Delay - Number of symbol delay %#codegen [r,j]=xcorr(ref,data); % find the cross-correlation r and the lags j [maxv,maxind]=max(abs(r)) ;% find the max value of the r Mlags=j(maxInd);% find the lag j at the max value delay=-mlags;% actually delay caused by the system 55

64 Appendix C MATLAB Function for Data Alignment Aligndata.m function Data = aligndata(delay, RxData) % Extract data from the buffered RxData, using the delay to find the frame % start % % Input: % Delay - Index of frame start % RxData - Buffered symbol-spaced data % Output % Data - Data with the Barker code at frame start %#codegen Data = RxData(Delay+:Delay+length(RxData)/2); end 56

65 Appendix D MATLAB Function for Phase Offset Estimation PhaseOffset.m function Phase = phaseoffset(ref,data) % Calculate Phase offset % Input: % Ref - Modulated Frame Head x(t) % Data - Received Frame % Output: % Phase - Phase offset cause by the system Ref=conj(Ref); % x*(t) Data=Data(:3); % y(t) = x(t)e^(j*phi) + n(t) Note: n(t) is the noise function P=Ref.*Data; % P = x(t)*y(t) = e^(j*phi) + x*(t)n(t) Mean_P=mean(P); % E[e^(j*phi) + x*(t)n(t)] = E[e^(j*phi)] Phase=angle(Mean_P); % phi_est estimated phase offset 57

66 Appendix E MATLAB Function for Phase Mapping Phasedecision.m function Out = phasedecision(in) % Map the estimated phase to one of, pi %#codegen if In<pi/2 && In>-pi/2 Out = ; else Out = pi; end 58

67 Appendix F MATLAB Function for Bits to Char Conversion sdrudpsk_bits2char.m str = 'Hello '; % Cycle through the string and convert characters to integers lens = length(str); % Number of characters in the string % Convert bit stream back to integers frameind = size(received,); for i=:frameind strbit = received(i,:); strbit = reshape(strbit, 7, lens); strbit = strbit'; sintest = bi2de(strbit, 'left-msb'); % Convert integers back to characters sest = (char(sintest))'; disp(sest) end 59