Eliminating speed penalty in ECC protected memories

Transcription

1 Elmnatng speed penalty n ECC protected memores Mchael Ncolads, Therry Bonnot, Nacer-Eddne Zerganoh TIMA Laboratory (CNRS, Grenoble INP, UJ) Abstract Drastc devce shrnkng, power supply reducton, ncreasng complexty and ncreasng operatng speeds that accompanyng technology scalng have reduced the relablty of nowadays ICs. The relablty of embedded memores s affected by partcle strkes (soft errors), very low voltage operatng modes, PVT varablty, EMI and accelerated crcut agng. Error correctng codes (ECC) s an effcent mean for protectng memores aganst falures. A major ssue wth ECC s the speed penalty nduced by the encodng and decodng crcuts. In ths paper we present an effectve approach for elmnatng ths penalty and we demonstrate ts effcency n the case of an advanced reconfgurable ODM modulator.) Keywords-Relablty, technoloy scallng, ECC, performance I. INTRODUCTION (HEADING ) Drastc devce shrnkng, power supply reducton, ncreasng complexty and ncreasng operatng speeds that accompany the technologcal scalng to the nanometrc doman, have reduced the relablty of nowadays ICs. The relablty of embedded memores s affected by partcle strkes (soft errors); very low voltage operatng modes; process, voltage and temperature (PVT) varablty; electromagnetc nterferences (EMI); and accelerated crcut agng nduced by falure mechansms ncludng NBTI, PBTI and HCI. These trends requre new desgn approaches for enhancng SoC relablty [-5] and requre concurrent error detecton and/or correcton for logc (e.g. [6], [7] and Error control codes (ECC for memores). As embedded memores represent the largest and denser parts of modern SoCs, they concentrate the majorty of falures. Thus, they are the frst blocks that desgners have to protect n order to meet ther relablty ECC s a convenent mean for protectng memores aganst falures, as they usually acheve hgh relablty at moderate area and power penaltes. One ssue wth ECC concerns the sgnfcant delays added by the encodng crcutry placed on the wrte sde of the memory and by the decodng and error correcton crcutres placed on ts read sde. These delays may nduce sgnfcant reducton of the clock frequency, whch may be nacceptable n many applcatons. In ths paper we present an effcent approach for treatng ths ssue. It elmnates the speed penalty nduced by ECC at the cost of very low area and power penaltes. We demonstrate the effectveness of the proposed approach n the case of an advanced reconfgurable ODM (orthogonal frequency dvson multplexng) modulator [6-8]. In our /DATE/ 20 EDAA experments we consder sngle error correctng codes (lke Hammng and Hsao), but also multple error correctng codes (lke BCH and Reed-Solomon). Protectng memores aganst sngle errors was suffcent n the past as multple errors were very rare. Thus, codes wth sngle-error correctng capabltes, lke the Hammng and Hsao codes [9] [0] were commonly used n ndustral products [] [2]. However, multple cell upsets (MCUs) produced by neutron strkes are today very common, as a consequence of the drastc devce shrnkng n advanced technologes. The problem can be overcome by usng column nterleavng, whch places further apart bts belongng to the same memory word. However, ths approach has ts lmts as further scalng ncreases the spreadng of MCUs [3] [4] and requres a hgher nterleavng factor. Ths requres placng large numbers of words n the same memory row, resultng n hgh row capactance, low speed, and hgh power dsspaton. urthermore, n recent memores, desgned for varablty robustness, pars of memory cells of the same word must be placed back to back. Also, usng multple error correctng codes s convenent n memores used for temporal storage (e.g. IO buffers) on the emsson/wrte port and recepton/read port of storage/transmsson meda/channels, as these meda/channels are protected by such codes. II. SPEED PENALTY ELIMINATION SCHEME Implementng ECC n memores ntroduces extra delays: - n the path of wrte data due to the crcutry used to compute the check-bts, and, - n the path of read data due to the crcutry used to compute the check-bts and correct the error n read data. It may be sutable n a desgn to remove the extra delay from one or both of these paths. Our scheme can do both for systematc codes (.e. separate nformaton bts and check bts). A. Delay elmnaton n the wrte path gure depcts the block dagram of our soluton for elmnatng extra delay n the path of the wrte data. We llustrate the soluton for the Hammng code but t s smlarly appled to any systematc code. As shown n fgure, the databts and the check-bts are stored n two separate memores (data-memory and code-memory). We can see n ths fgure the block generatng the check-bts from the data-bts to be wrtten n the data-memory, as well as the block generatng the checkbts from the data-bts read from the data-memory. The later check-bts are bt-wse XORed wth the check-bts read from the code-memory by a stage of XOR gates (XOR), whch produces the error syndrome. Ths syndrome ndcates the

2 poston of the erroneous bt n a bnary-code form. A combnatonal block transforms ths form nto a -hot code (- hot block). nally, a second block of XOR gates (XOR2) btwse XORs the -hot form of the syndrome wth the data-bts read from the data-memory and the check-bts read from the code-memory to correct eventual errors affectng these bts. In ths scheme, the data-bts are wrtten n the data-memory as soon as they are ready. Thus, the frequency of the clock sgnal Ck s the same as n the case of a system whch does not mplement ECC. Ths elmnates the speed penalty on the wrte sde. However, an extra delay s added on the nputs of the code-memory by the code generaton block. To manage ths delay, the code-memory uses a clock sgnal Ck+δ, whch has the same frequency as sgnal Ck, but t s delayed wth respect to ths sgnal by a delay δ equal to or larger than the delay of the code generaton block. As a matter of fact, the check-bts are ready when the sgnal Ck+δ enables wrtng these checkbts n the code-memory. Nevertheless, snce the sgnal Ck+δ enables both the wrte and the read operatons n the codememory, then, durng a read operaton, the check-bts wll be read wth a delay δ wth respect to the data-bts read from the data-memory. However, ths delay does not ncrease the delay of the error detecton/correcton process, because the checkbts read from the code-memory are appled drectly to the XOR block, whle the data-bts read from the data-memory traverse the code generaton block, whch has a delay equal to δ (same as the code generaton block used n the wrte sde). The delayed clock sgnal Ck+δ can be generated locally, by addng a delay element on the Ck sgnal of the datamemory. Ths local generaton mnmzes skews between the clock sgnals of the data-memory and the code-memory. Careful mplementaton of the delay element wll consder worst-case delay of the code-generaton block as well as bestcase (mnmum) delay of ths element. Another possblty s to use a sngle clock sgnal for both memores, but use the one edge of ths sgnal (e.g. the rsng edge) as the actve edge for the data-memory, and ts second edge (e.g. the fallng edge) as the actve edge for the code-memory. Ths wll work f the delay of the code generaton block does not exceed the tme nterval that separates theses edges. block s larger than one clock cycle, more ppe-lne stages are added. Ths means that a wrte n the code-memory wll be performed more than one clock cycle after a wrte n the datamemory. Ths large delay s balanced by the delay of the code generaton block placed on the read data, snce, n ths block, a smlar number of ppe-lne stages are added. Long delays n the later block wll be handled by the scheme that removes speed penalty on the read sde, as descrbed next. B. Delay elmnaton n the read path gure 2 depcts the block dagram of a system where the data read from a memory pass through a combnatonal logc block (Logc) and are stored n a stage of flp-flops (). Logc can be empty (.e. the read data enter drectly ). Input Logc g. 2: A system wth an unprotected memory In fgure 2, the memory s not protected by an ECC. If ECC s used, the error detecton and correcton crcutry wll be placed between the memory and the combnatonal block Logc, ncreasng sgnfcantly the sgnal delay and decreasng accordngly the clock frequency. In many applcatons, t may be requred to mantan the clock frequency of the ntal (unprotected) desgn. or dong so, one soluton conssts on addng one or more stages of flp-flops between the memory and. Ths soluton wll allow reachng the desrable clock frequency. However, performance wll stll be mpacted as the data read from the memory wll reach the flp-flop stage one or more clock cycles later than n the unprotected desgn. Ths may not be desrable n many applcatons. Detecton EI hold Control Correcton M U X Logc 2 g. 3: Reducton of the speed penalty on the path of read data g. : Elmnaton of extra delay n the path of wrte data Another mplementaton, useful when the delay for the code generaton s very large, conssts on addng a ppe-lne stage n the code generaton block. Wth ths soluton, the operatons n the code-memory wll be performed one clock cycle later than n the data-memory. Also, f the delay of the code generaton Detectng an error s faster than correctng t. Based on ths observaton, the clock frequency can account only for the delay of the error detecton sgnal. Thus, a second soluton s shown n fgure 3. The data read from the memory are suppled to the system through a MUX. The frst nputs of the MUX come drectly from the memory and the second nputs from the error correcton block. In error-free operaton, the frst nputs of the MUX are suppled to the system. When the error ndcaton sgnal (EI) detects an error, the system s halted for one or more clock cycles to provde extra tme for performng the error correcton. At the end of these cycles, the second nputs of the MUX are suppled to the system. Whle ths

3 soluton reduces the speed penalty, stll the desgner may not acheve ts target speed due to the delay of error detecton. So, we are lookng for a soluton enablng elmnatng clock speed reducton wthout addng extra ppe-lne stages. The detaled mplementaton of the proposed soluton depends on the relatons between the delays of the detecton crcutry and of the correcton crcutry (.e. n how many cycles after read the error detecton sgnal and the corrected data are ready). Thus, several cases are consdered. We start wth the smpler ones to present the basc prncples of the approach n smple way. Then we generalze them for more complex cases. g. 4: Elmnaton of error detecton and correcton delays Case a: The error detecton sgnal and the corrected data are ready one clock cycle after latches the erroneous data. In ths case, the proposed soluton s llustrated n fgure 4, for the desgn of fgure 2. or easer llustraton, the detecton and correcton blocks are shown to be dstnct, but n realty they share the code generaton block. The dea here s to supply, through a MUX, the data to the system as soon as they are read. Thus, we can use a clock perod that does not account for the error detecton and error correcton delays. In ths case, the system wll work properly as long as no errors are present n the data read from the memory. Durng ths tme the MUX supples to the system the data comng drectly from the memory. However, when an error s present n the read-data, t s propagated and contamnates the system flp-flops before the error detecton sgnal ndcates ts occurrence. To handle ths ssue, the actvaton of the error detecton sgnal EI actvates durng the next clock cycle the hold sgnal of all flp-flops except the frst stage of flp-flops (). It also enables the MUX to supply the data comng from the error correcton block. Thus, durng one clock cycle all the flp-flop stages but are hold, mantanng ther prevous state. Durng the same clock cycle, the stage s decontamnated, snce t receves the corrected data. Then, the hold sgnal s deactvated and the system resumes operaton from a correct state. EI EI Control Detecton Correcton Control M U X Detecton Correcton M U X g. 5: Handlng lateral nputs Logc IO- MUX Logc Input 2 hold hold The above mplementaton works when only data orgnated from the erroneous read value enter the ppe-lne stages of the decontamnaton path. If some other nputs enter these stages (as Input sgnaled n fgure 2 by a dashed arrow), then, durng the decontamnaton phase the values appled on these nputs have to be the same as the ones appled durng the error propagaton phase. As a matter of fact, a IO s added on these nputs, to preserve ther values and apply them later on the crcut through a MUX, as shown n fgure 5. As n ths fgure the values comng from Input are propagated durng one clock cycle before actvatng the hold sgnal, then, a sngle stage IO s used (.e. IO- s just a stage of flp-flops). Case b: The error detecton sgnal s ready one clock cycle after the uncorrected data are latched n and the corrected data are ready m clock cycles after ths tme (the correcton block wll comprse m ppe-lne stages to handle ts delay, wth m>). The mplementaton of our soluton s as n case a (fgure 4). However, when an error s detected the control s dfferent than the one correspondng to fgure 4. In fact, n the present case, the hold sgnal s mantaned actve for m- cycles to gve the tme requred for the data to be corrected and stored n m cycles later. Durng the same perod the control sgnal of the MUX s mantaned hgh. Thus, at the end of the m th cycle, when the data are corrected, the nputs of come from the correcton block. Thus, at the m th cycle all stages contan correct data and the hold sgnal s released at the next cycle enablng all ppelne stages to resume operaton. Case c: The error detecton sgnal and the corrected data are ready k cycles after the uncorrected data are latched n (the detecton block and the correcton block wll comprse k ppe-lne stages, wth k>). Note that, for holdng the system, we need to take nto account the delay of the detecton block plus the delay of the nterconnectons dstrbutng the hold sgnal. Thus, the k ppe-lne stages of the detecton block also account for the delay of these nterconnectons. In the present case (c), the erroneous data are propagated through k ppe-lne stages before the system flp-flops are hold. Thus, the decontamnaton process wll take k clock cycles. urthermore, the number of cycles durng whch dfferent stages are hold s varable: The very frst flp-flop stage followng the correcton block s not hold at all; the s that are one stage further are hold for one clock cycle; the s that are two stages further are hold for two clock cycles; ; the s that are k stages further as well as all other s are hold for k clock cycles. In addton, as an extenson of the prncple of fgure 5, f some data not orgnated from the erroneous read values enter the ppe-lne stages of the decontamnaton path (lke Input n fgure 2), then, durng the decontamnaton the values appled on these nputs have to be the same as the ones appled durng the error propagaton. Thus, IOs are added on these nputs to preserve ther values and apply them (through a MUX) durng the decontamnaton phase. The number of the stages of each IO depends on ts poston n the decontamnaton path. or nputs connected to the very frst stage followng the correcton block the IO wll have k stages; for nputs connected at one stage further the IO wll have k- stages; ; for nputs connected k-

4 stages further the IO wll have stage. Also, each IO wll be hold durng the same number of cycles as the flp-flops of the ppelne stage on whch t s connected. Case d: The error detecton sgnal s ready k clock cycles after the uncorrected data are latched n and the corrected data are ready m cycles after ths nstant (the detecton block comprses k ppe-lne stages and the correcton block comprses m ppe-lne stages, wth m>k>). or ths case, the mplementaton of our soluton s as n case c. However, when an error s detected the control s dfferent. In fact, as n the present case the corrected data are ready m-k cycles after the error detecton sgnal actvates the hold sgnal, we have to hold the system flp-flops for m-k cycles (to gve the tme requred for the data to be corrected and stored n ), before startng the decontamnaton phase descrbed n case c. In the above we present the prncples of the proposed approach. However, numerous partcular cases concernng the placement of the IOs, ther depth and the number of cycles certan stages have to be hold are not presented here for space reasons. The complete algorthm was mplemented n an automaton tool whch wll be descrbed n a further communcaton. Ths tool s nteractve, as, n certan cases, t proposes several solutons concernng the placement and depth of IOs and leaves the desgner to make the fnal choce. In some other cases, t requests the desgner some functonal nformaton concernng the way certan paths are used, n order to determne the optmal soluton. The proposed approach allows mplementng ECC n embedded memores wthout affectng the clock frequency of the desgn, nether ntroducng extra ppe-lne stages. The counterpart s to pay some extra clock cycles each tme an error s detected. However, the performance reducton ntroduced by these extra cycles s nsgnfcant. As an llustraton, let as consder a SoC comprsng 50 Mbytes of embedded memores (whch s on the upper lmts of what s today possble wth advanced technologes). Let us also consder that the SER (soft error rate) s 000 IT per Mbt (whch s rather on the hgh sde of SER encountered n current technologes - usually several hundreds IT per Mbt). Then, the total SER wll be 60x8x000 IT = 48x0-3 falures per hour, IT = 0-9 falures per hour) or about falure every 5 days. Ths MTB s totally unacceptable for numerous applcatons ncludng networkng, servers, automotve etc, and mposes usng ECC to protect the embedded memores of the SoC. As ECC mplementaton may nvolve nacceptable performance penalty, the proposed approach can be used to handle ths ssue. Consderng a rather large delay for error correcton (e.g. three clock cycles), the descrbed approach wll nduce loosng three clock cycles every 5 days. or a 200 MHz clock frequency we wll have a performance reducton of 0-8 %, whch s totally nsgnfcant! Note that, as the functon of processors s to execute nstructons, processors realze certan nstructon manpulaton functons such as bubblng, flushng, Thus, n processors, reducton of ECC speed penalty durng read can be done at the functonal level. The smlar technque as the one n fgure 3, wll be typcally mplemented by stallng the ppe-lne. Complete elmnaton of ECC penalty can also be done at the functonal level, but s more complex way. or nstance, after error detecton the ppelne s flushed - the nstructon affected by the ncorrect data and the nstructons fetched after t are dsregarded (smlarly to branch mspredcton recovery). Then, the dscarded nstructons are replayed, wth the frst of them usng data comng from the error correcton crcut. These approaches are lmted to processor only desgns. However, a SoC may comprse hundreds of memores, wth several of the used by non-processor logc. Thus, the desgners need a generc (preferably automated) approach, to mplement fast ECC n any desgn. The approach descrbed above s generc, as t works for any RTL desgn, and s automated. A non-processor desgn s consder n the next secton as case study. III. CASE STUDY AND IMPLEMENTATION The case study conssts n an advanced reconfgurable ODM modulator [6-8], proposed n the context of Software Desgn Rado (SDR). SDR supports several standards wth a unque termnal. ODM modulaton s partcularly mportant for the development of SDR, because of the many standards usng ths knd of modulaton (B3G, 4G, WII, WIMAX, WRAN). The reconfgurable archtecture consdered here s able to compute several modulatons: ODM QAM and OQAM. These modulatons are based on T or IT usng RADIX algorthms, and IOTA flterng for OQAM. IOTA stands for "Isotropc Orthogonal Transform Algorthm pulse shapng flterng". IOTA flterng mproves performance aganst coste nterference, mpulsve nose, and frequency-selectve fadng [6]. Consequently, t does not requre guardng nterval for the same performance. On the other hand, ODM symbols have to be computed twce faster n average. The desgn supports a varable number of sub-carrers from 64 to 892, and s able to compute up to 4 modulatons n parallel. g. 6: Reconfgurable computng matrx Ths desgn s a memory ntensve parallel archtecture and the protecton of memores aganst falures s hghly desrable. It s composed of reconfgurable data path computng matrx, dvded n 2 blocks of complex multplcatons and accumulatons (g. 6). 2 ROMs store T and IOTA coeffcents. 2 RAMs store samples for T and IOTA flterng computatons. The RAM dedcated to T s dvded n two blocks whch are alternately used. Each block s composed of 8 sub-blocks of complex samples. Equvalently,

5 we may consder that each block has 6 nput/outputs. Each of the 6 storages s a reconfgurable memory block, whch confguraton depends on the number of sub-carrers and MIMO. Regardng the computng matrx, the confguraton depends on the algorthm chosen (Radx 2, 4 or 8), the number of MIMO, and IOTA flterng. The Calculus Blocks (CB), whch are not nvolved n computaton, can be deactvated. Regsters can also be deactvated n each of the busy block, dependng of the current calculus mode. The approach for speed penalty elmnaton, presented n the prevous secton, was frst mplemented manually for the RAM blocks storng the T samples (T RAM blocks). As data can be wrtten and read at the same tme n these blocks, separate encodng and decodng crcuts were used On the other had, the control block s common to all memory I/O n order to smplfy the clock control. The read clock has a phase dfference of π wth the clock of the rest of the desgn. Consequently, f we nsert the detecton and correcton blocks n ths desgn we wll dspose less than a half clock cycle for detecton and correcton. Ths tme s nsuffcent and wll requre ether reducng the clock frequency or addng extra ppelne stages. In both cases, we wll have a drastc throughput reducton. Thus, the approach descrbed n the prevous secton s very sutable. Subsequently we used the automaton tool to mplement our approach. The soluton proposed by the tool, based on structural (RTL) nformaton only was more expensve n hardware. However, the tool was able to specfy the paths n whch some functonal nformaton could allow cost reducton, and once we provded ths nformaton, the tool proposed the same soluton as the one found by manual analyss. It s worth notng that the manual analyss took several months of work, whle the response of the tool s vrtually nstantaneous. The most complex task for the manual mplementaton was to analyze the complex archtecture of the reconfgurable ODM modulator and determne the places n the decontamnaton path where IOs and MUXes have to be nserted (postons where data not orgnated from the erroneous read values enter ths path). As we have seen n the prevous secton, the length of the decontamnaton path and the sze of the IOS depend on the delay of error detecton. Thus, the analyss vares from one code to another. The detaled presentaton s lengthy and goes along wth a detaled presentaton of the crcut. Thus, we only present the general prncples that confrm the decsons of the RTL tool by the manual analyss: Outsde the reconfgurable matrx, some sgnals have to be stored for savng the operatng context needed durng decontamnaton. The most mportant are the prevous confguraton of the matrx, and the dentfcaton of the concerned T RAMs (g. 7). Accordng to the g. 6, each Calculus Block n the matrx can be deactvated on demand. or nstance, f the frst stage (CB, 2, 3 and 4) s nvolved n a correcton, the other blocks can be stopped. If the second stage s nvolved (CB 5, 6, 7 and 8), the frst stage s already deactvated, and the thrd stage has to be stopped. By deactvatng CBs handlng data that are not corrupted, ther state s preserved. However, due to ther complexty, the detaled descrpton of CBs s requred for presentng the detals concernng the case when CBs are actvated. The most complex of the processng elements of the desgn has a ppelned archtecture wth feed-back loops. Thus, IOs and MUXes are used to save the context (g. 8). The decsons made by ths analyss confrm the decsons made by the tool. urthermore the mplementaton was extensvely valdated by error njectons on the read data. g. 7: Addtonal IOs and MUXs for savng context outsde the matrx g. 8: Addtonal IOs and MUXs for savng context nsde the matrx IV. RESULTS The crcut together wth the varous ECC mplementatons were synthessed on a 65 nm technology wth Desgn Vson and smulated wth Modelsm. The clock frequency of the orgnal desgn (.e. wthout ntroducng ECC), s 278 MHz. Several sngle-error correctng and multple-error correctng codes were mplemented: extended Hammng (22, 6, ), Hsao (22, 6, ), BCH (3, 6, 3), Reed-Solomon (56, 6, 7), as well as Reed-Solomon (20, 8, 4) usng the approach n [5] to reduce the complexty. In the parentheses, the frst number gves the total number of bts (data plus check bts), the second number gves the data bts and the thrd the number of the correctable errors. The data wdth n the desgn s 6 ts. The 8 data bts n Reed-Solomon (20, 8, 4) mean than the 6 bts are dvded n two parts and each part s checked by a (20, 8, 4) Reed-Solomon code. The crcut operaton under ncorrect data was verfed by error njectons at the read data. Table presents the results for the dfferent mplementatons. Column presents the dfferent codes that were evaluated. Column 2 presents the maxmum operatng frequency obtaned wth the standard mplementaton of these codes, and column 3 the maxmum operatng frequency obtaned wth the proposed mplementaton. Columns 4 and 5

6 present the area and power penaltes nduced by the proposed ECC mplementaton n comparson wth the standard ECC mplementaton. These penaltes are computed on the bass of the area and power of the memores and of the standard mplementaton of the ECC crcutry and not on the bass of the area and power of the whole desgn. These overheads wll be lower f we compute them on the bass of the area and power of the whole desgn, but such a computaton wll not be far as the proposed approach mproves the performance related to the ECC nserton. In all cases, the frequency allowed by the new mplementaton s equal to 278 MHZ, whch s the frequency of the unprotected ODM crcut (no ECC for memores). We observe drastc speed mprovements wth respect to the standard mplementatons of the dfferent codes (40% for Hammng, 42% for HSIAO, and up to 329% for Reed- Solomon (56, 6, 7)), whle the area and power penaltes wth respect to the same mplementatons are very low. As concernng the extra cycles nduced n case of error detecton: or the Hammng and HSIAO codes, the erroneous data contamnate one flp-flop level before error detecton and actvaton of the hold sgnal. Thus, we used one clock cycle for performng decontamnaton. or BCH (3, 6, 3) and RS (20, 8, 4), the erroneous data contamnate two flp-flop levels before the actvaton of the hold sgnal. Thus, we used two clock cycles for performng decontamnaton. nally, for RS (56, 6, 7), the erroneous data contamnate three flp-flop levels before the actvaton of the hold sgnal. Thus, we used three clock cycles for performng decontamnaton. In addton, for ths code, error correcton delay requres nsertng one wat cycle before startng decontamnaton. Ths means that accordng to the code used, at each error detecton, computatons wll take one, two or four extra clock cycles. However, as shown n the prevous secton ths represents nsgnfcant performance penalty, even for complex codes lke BCH or Reed-Solomon. Thus, even such complex codes can be mplemented wthout performance penalty. ODM desgn r standard r New Area New Power New Hammng (22,6) 98 MHz 278MHZ +2,64% +6,0% Hsao (22, 6) 96 MHz 278MHZ +2,69% +3,62 BCH (3, 6, 3) 5 MHz 278MHZ +2,5% +9,04 RS (56, 6, 7) 64,7 MHz 278MHZ +2,24% +8,27 RS (20, 8, 4) 7 MHz 278MHZ +,9% +6,75 Table CONCLUSION In ths artcle we have presented an approach for elmnatng the speed penalty related wth the mplementaton of ECC n embedded memores. The approach s generc (works for any systematc code and for any knd of desgn), t completely elmnates the speed penalty nduced by the ECC crcutry, and s shown by means of a practcal case study (an advanced reconfgurable ODM modulator) to requre very low area and power cost. We show that these results are vald even for complex codes lke BCH or Reed-Solomon, whch could otherwse nduce very hgh speed penalty. REERENCES [] R.C. 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