8-channel FastADC with 14 bit resolution

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1 August 7, channel FastADC with 14 bit resolution J. Andruszkow a, P. Jurkiewicz a, F. Tonisch b Reference Manual Version 1.1 a. Henryk Niewodniczanski Institute of Nuclear Physics, Cracow b. DESY Zeuthen

2 2 8-channel FastADC with 14 bit resolution

3 Table of contents Table of contents i. List of Figures... 4 ii. List of Tables General description Hardware Modes of operation Analog buffer and ADC ADC clock adjustment DSP connection Timing DSP connector VME-Address mapping Status and Control Register Mapping Description of the VME Control and Status registers Description of the ADC Control Registers ADC memory address mapping and data lines channel FastADC with 14 bit resolution 3

4 List of Figures i. List of Figures FIGURE 1. Block diagramm of the ADC... 7 FIGURE 2. Sample mode... 8 FIGURE 3. Normal mode ( continuous sampling)... 8 FIGURE 4. Stop mode... 9 FIGURE 5. Input stage of ADC unit FIGURE 6. Jumper positions FIGURE 7. Sample clock adjustment FIGURE 8. Data transfere on DSP connector in low frequency mode FIGURE 9. Data transfere on DSP connector in high frequency mode channel FastADC with 14 bit resolution

5 List of Tables ii. List of Tables TABLE 1. gain and DC offsets for the basic input ranges TABLE 2. Output data format TABLE 3. Input range selection TABLE 4. Input impedance and coupling mode selection TABLE 5. DSP connector pin assignment TABLE 6. Register Addresses TABLE 7. Memory address mode selection channel FastADC with 14 bit resolution 5

6 General description 1. General description 1.1. Hardware The FastADC is a high speed high resolution analog to digital converter board in VME standard. It can convert and store analog signals from 8 channels with 14-bit resolution at a rate of up to 10MSample/s. The ADC channels are grouped in four blocks sharing a single voltage reference and a single 128k x 32bit SRAM (see blockdiagram in Figure 1 on page 7). Data from the odd input channels are stored in the lower half of the word and data from even channels in the upper half of the word. Tri-state-buffers decouple the individual ADC data lines from the local bus on the board. The local bus is operated at a frequency of 66MHz. The latches are for the synchronization of the ADC data. The analog amplifier adapts the input signal range to the input range of the ADC. The input range can be set individually for each channel by the mean of jumpers. One can select either +/-1V or +/-5V range. Since the ADC chip has a single supply voltage, ground based bipolar input signals require a DC-level-shifting also performed by that input amplifier. The input impedance of each ADC channel can be choosen to be eather 50Ω or 1kΩ. A more detailed description will be given in Section 2. The operation of the ADC is controlled by logic realized within an ALTERA-FPGA. This FPGA contains all necessary registers. A detailed description of all operating modes is given in Section 1.2. External or internal triggering is possible. One can select as well external or internal ADC clock. The clock phase can be adjusted with respect to the analog input signal in steps of 5ns within a range of 100ns. Conversion takes place at the rising edge of the ADC clock signal. The FastADC is a standard VME-Slave module. The status and control registers are accessible in A16D16 mode. The data memory can be accessed either in A24D16, A24D32, A32D16 or A32D32 mode. The board occupies 256Words of the short address space and 2Mbytes of the standard or extended address space. The address mode is selected by means of a jumper (see Figure 6 on page 13). The VME interface logic is realized within a XILINX FPGA. 6 8-channel FastADC with 14 bit resolution

7 General description FIGURE 1. Block diagramm of the ADC Delay Line 20 x 5ns Ext. Trigger ADC Controller VME Controller Ext. Clock ALTERA EPF10K10TQFP144 Local Control Xilinx XCS30XL-PQ208 IN8 Ampl. ADC-Clock ADC 14 bit Ref. Volt. OE-Enable ADC-Latch TriState Latch SRAM 128k x 32 Buffer Local Data Local Address DSP Port Connector VME Connector J1 IN7 Ampl. ADC 14 bit TriState Latch Buffer IN6 Ampl. ADC 14 bit TriState Latch Buffer Ref. Volt. SRAM 128k x 32 IN5 Ampl. ADC 14 bit TriState Latch Buffer IN4 IN3 IN2 IN1 Ampl. Ampl. Ampl. Ampl. ADC 14 bit Ref. Volt. ADC 14 bit ADC 14 bit Ref. Volt. ADC 14 bit TriState Latch TriState Latch TriState Latch TriState Latch SRAM 128k x 32 SRAM 128k x 32 Buffer Buffer Buffer Buffer Power Supply and Filters Digital: +5V +3.3V Analog: +5V +7V -3V VME Connector J2 8-channel FastADC with 14 bit resolution 7

8 General description 1.2. Modes of operation The ADC can operate in three different modes of triggers. The trigger modes are selected via the ADC Control Register ( ADC Control Register: on page 20): Sample Mode: After a trigger a predefined number of samples are taken and stored within the memory. Conversion stops after the predefined number of triggers were received. It generates an interrupt at the end of each sample and one if the number of triggers where reached. New sampling starts at the beginning of the memory. FIGURE 2. Sample mode Start sampling (# of triggers = 3) end sampling Trigger ADC-Clock N Samples N Samples N Samples End of Sample (Interrupt 1) End of Conversion (Interrupt 2) Memory Address 0 N-1 N 2*N-1 2*N 3*N-1 Normal Mode: In this mode the buffer is filled continuously with a preset number of samples. The data are filled in wrap-around mode, e.g. older data are overwritten. Every N samples an interrupt is generated. The ADC is stopped by a software or a hardware reset (system reset). FIGURE 3. Normal mode ( continuous sampling) Trigger ADC-Clock N Samples N Samples N Samples End of Sample (Interrupt 1) End of Conversion (Interrupt 2) Memory Address (T-1)*N T*N-1 T*N (T+1)*N-1 (T+1)*N (T+2)*N-1 T = # of triggers taken so fare 8 8-channel FastADC with 14 bit resolution

9 General description StopAfter Mode: The data aquisition starts immediatly after enabling this mode. The sampling stops a pre-defined number of samples after receiving a trigger. FIGURE 4. Stop mode Trigger ADC-Clock N Samples End of Sample (Interrupt 1) End of Conversion (Interrupt 2) Memory Address data before trigger N data after trigger For all trigger modes a special register returns the address of last written data. Knowing the sample mode and the contents of the of the number of triggers and samples taken one can calculate data buffer size and location. The module generates interrupts after the number of samples are reached or after the conversion has been finished. If the interrupt is enabled a 8-Bit interrupt status/id is put onto the VME bus. The interrupt level is programmable 8-channel FastADC with 14 bit resolution 9

10 Analog buffer and ADC 2. Analog buffer and ADC The analog part for each channel of the ADC board consists of a buffer amplifier and the ADC chip itself. Figure 5 on page 11 shows the schematic diagram of a single analog channel of the ADC board. It consist of the analog-to-digital converter AD9240 from Analog Devices and an AD9631 as buffer amplifier. The ADC has a resolution of 14-bit and the maximum sample rate is 10MSample/s. It operates from a single +5V power supply. The AD9240 has a differential input structure. The input span of the ADC is determined by the reference voltage U ADCref ( V INA V INB ) U ADCref. In the actual design the theoretical value for reference voltage is U ADCref 2.333V determined by and. = R 11 R 12 Proper single ended bipolar operation with DC coupling requires a shifting of the DC level of the input signal at V INA and the V INB input biased to that DC offset. The level shifting circuit is based on the operational amplifier AD9631. This is a wide bandwidth low distortion amplifier for exceptionally fast and accurate pulse response. The voltage at the V INA input of the AD9240 is given by: V INA = U IN gain + U offset The V INB input of the AD9240 is fixed to U ref = 2.5V provided by an external reference voltage source AD780. From the block diagram in Figure 1 on page 7 one can see the always two channels are driven by on reference voltage source AD780. Depending on the jumper settings one can realize different gains and different DC offsets. These values should be choosen in a way that the voltage at V INA fits best into the range from U ref U ADCref = 0.167V to U ref + U ADCref = 4.833V. Table 1 shows the values for the basic options. One can install other combination of jumper settings although it is not recommended because not all combinations of jumper settings make sense. For some of them even the maximum ratings for the input voltage of the AD9240 are exceeded. Input range +/- 1V (a) gain (theoret.) DC Offset (theoret.) a. Input impedance = 50Ω, input left open b. Input impedance = 1kΩ, input left open expected ADC value One can choose the input impedance to be either 50Ω or about 1kΩ. The coupling between the buffer amplifier and the AD9240 can be AC or DC coupled. All jumper settings for the different options are given in Table 3 on page 12 and in Table 4 on page 12. The location of the jumpers are shown in Table 6 on page 13. U min U max V V 1.1V +/- 5V (a) V V 6.5V +/- 1V (b) V V 0.75V +/- 5V (b) V V 5.7V TABLE 1. gain and DC offsets for the basic input ranges 10 8-channel FastADC with 14 bit resolution

11 Analog buffer and ADC FIGURE 5. Input stage of ADC unit C2 2.2PF R6 1.5K JP3 AD9240 JP2 C3 0.5PF R11 10K VREF LEMO IN R2 510 R4 1.1K R7 2.4K R12 7.5K SENSE R1 56 REFCOM JP1 R3 1.1K R8 2.4K U1 JP5 INA VINA R9 604 JP4 AD9631 CK1 10UF + R10 1.1K CK2 100N CML OTR REF_IN INB VINB D[13:0] The digital output of the ADC is represented in straight binary and given by: Data = V INA V INB U ADCref The OTR bit indicates an underflow or overflow condition. V INA V INB (D15) OTR (D14) Digital Output Data (D13..D00) U ADCref = U ADCref 1LSB = = U ADCref < U ADCref TABLE 2. Output data format 8-channel FastADC with 14 bit resolution 11

12 Analog buffer and ADC Channel Input Range Open Closed 1 +/-1V JP3, JP4 JP2 +/-5V JP2 JP3, JP4 2 +/-1V JP8, JP9 JP7 +/-5V JP7 JP8, JP9 3 +/-1V JP13, JP14 JP12 +/-5V JP12 JP13, JP14 4 +/-1V JP18, JP19 JP17 +/-5V JP17 JP18, JP19 5 +/-1V JP23, JP24 JP22 +/-5V JP22 JP23, JP24 6 +/-1V JP28, JP29 JP27 +/-5V JP27 JP28, JP29 7 +/-1V JP33, JP34 JP32 +/-5V JP32 JP33, JP34 8 +/-1V JP38, JP39 JP37 +/-5V JP37 JP38, JP39 TABLE 3. Input range selection Channel Input Impedance Open Closed Coupling Mode Open Closed 1 50Ω JP1 DC (a) 1kΩ JP1 AC (b) JP5 JP5 50Ω JP6 DC JP10 2 1kΩ JP6 AC JP10 50Ω JP11 DC JP15 3 1kΩ JP11 AC JP15 50Ω JP16 DC JP20 4 1kΩ JP16 AC JP20 50Ω JP21 DC JP25 5 1kΩ JP21 AC JP25 50Ω JP26 DC JP30 6 1kΩ JP26 AC JP30 50Ω JP31 DC JP35 7 1kΩ JP31 AC JP35 50Ω JP36 DC JP40 8 1kΩ JP36 AC JP40 TABLE 4. Input impedance and coupling mode selection a. DC-Offsets see Table 1 on page 10 V INA b. DC-Offset = 2.5V V INA 12 8-channel FastADC with 14 bit resolution

13 Analog buffer and ADC FIGURE 6. Jumper positions 8-channel FastADC with 14 bit resolution 13

14 ADC clock adjustment 3. ADC clock adjustment When used with external clock the sample clock to the analog-to-digital converter can be delayed up to 100ns in steps of 5ns with respect to this clock. The required delay is set with the delay register (see Delay Register: on page 21). The delay of the sample clock at the ADC chip with respect to the external clock directly measured at the input connector is: Delay 40ns ; for delay register set to 0 (or if D is set >20) Delay 5ns D + 45ns ; for delay register set to D, where D ranges from 1 to 20. The internal delay of the analog signal from input to the ADC chip is approximately 5ns. FIGURE 7. Sample clock adjustment Sample point Analog Signal ext. Clock ADC_Clk Delay 14 8-channel FastADC with 14 bit resolution

15 DSP connection 4. DSP connection 4.1. Timing For future applications with a DSP a special interface was realized on the board. During the data transfere to the memory the actual sampled data are available at this connector. FIGURE 8. Data transfere on DSP connector in low frequency mode SYSCLK INTERNAL LocalBus Data BusBufEN[3..0] Ch1-2 Ch3-4 Ch5-6 Ch A data transfere is indicated by the signal INTERNAL. The data transfere on this bus differs depending on the sample rate of the ADC. For low sample rates up to 1-2 Msamples/s data from all ADC channels are transfered one by another. The signals BusBufEN can be used by the interface logic to latch data to different input registers. FIGURE 9. Data transfere on DSP connector in high frequency mode SYSCLK INTERNAL LocalBus Data BusBufEN[3..0] Ch Ch For sample rates above 2 MSamples/s there is no time enough to transfere data from all ADC channels to the DSP. Then only two channels selected within the ADC Control Register (see ADC Control Register: on page 20) is transfered DSP connector The connector is a 64 pin CMC connector according to IEEE 1386 for mezzanine boards (AMP reference Nr: ; MOLEX reference Nr: ). On the board containing the interface logic should be used the corresponding CMC connector (AMP reference Nr: ; MOLEX reference Nr: ). Table 5 on page 16 shows the connector pin assignment. 8-channel FastADC with 14 bit resolution 15

16 DSP connection Pin Signal Signal Pin 1 +5V +5V V +5V 4 5 D00 D D02 D D04 D D06 D D08 D D10 D D12 D D14 D GND GND D16 D D18 D D20 D D22 D D24 D D26 D D28 D D30 D GND GND BusBufEN0 BusBufEN BusBufEN2 BusBufEN GND GND INTERNAL reserved reserved reserved reserved reserved V +3.3V V +3.3V GND GND SYSCLK GND V +5V V +5V 64 TABLE 5. DSP connector pin assignment 16 8-channel FastADC with 14 bit resolution

17 VME-Address mapping 5. VME-Address mapping 5.1. Status and Control Register Mapping All status and control registers of the modul are accessed by A16D16 (AM=$29 or AM=$2D) cycles only. The base address for the Status and Control Registers is set by means of jumpers H1 [A15..A8] ( see Figure 6 on page 13). An open jumper means the corresponding address bit must be high and on the other hand a closed jumper means the corresponding address bit must be low during address selection. Address offset Register Descrcription $0 Base Address Register $2 Interrupt Status Register 0 $4 Interrupt Status Register 1 $6 Control and Status Register 0 $8 Control and Status Register 1 $A Read from last memeory location $C Clear Interrupt Request 0 $E Clear Interrupt Request 1 $10 Trigger Register $12 Sample Register $14 ADC Control Register $16 Delay Register $18 Trigger Counter Register $1A Sample Counter Register $1C Clock Divider Register TABLE 6. Register Addresses 8-channel FastADC with 14 bit resolution 17

18 VME-Address mapping 5.2. Description of the VME Control and Status registers Base Address Register: Offset: $0000 Access Mode: A16D16, R/W D15 D08 D07 D05 D04 D00 Write EXT_Base STD_Base x x x x x Read EXT_Base STD_Base The content of this register defines the base address for the memory access. Two modes according to the setting of jumper J41 are possible. Ext_Base represent the address lines A32..A24 and STD_base the address lines A23..A20. Memory access is disabled unless the correct memory base address is set. First write to this register enables the memory access. Interrupt Status Register 0: Offset: $0002 Access Mode: A16D16, R/W D15 D14 D13 D12 D11 D10 D08 D07 D00 Write x x x Read IRqst0 0 0 Auto- Clr Auto- Clr x IRQ Level Interrupt Status/ID x 0 IRQ Level Interrupt Status/ID 0 Interrupt Status Register 1: Offset: $0004 Access Mode: A16D16, R/W D15 D14 D13 D12 D11 D10 D08 D07 D00 Write x x x Read IRqst1 0 0 Auto- Clr Auto- Clr x IRQ Level Interrupt Status/ID x 0 IRQ Level Interrupt Status/ID 1 The ADC can generate interrupts on two events. Each time the sample counter reaches zero IRqst0 is set. If the trigger counter zero and the sample counter reaches zero then IRst1 is set. Compare to the different operation modes. The priority of the issued interrupts is defined by setting the corresponding IRQ level ranging from 7 to 1 (where IRQ level=7 correspond to highest priority). IRQ Level set to zero disables the corresponding interrupt source. The module can be programmed either to act as ROAK (Release on Acknowledge) or as RORA (Release on Register Access) interrupter. If Auto-Clr is set then the pending interrupt request is cleared during the interrupt acknowledge cycle automaticly (ROAK) otherwise it has to be cleared by writing to dedicated addresses (RORA, base address + $C or base address + $E). Clearing interrupt requests this way works independenly of the status of the Auto-Clr bit. The Interrupt Status/ID is the 8-bit vector put on data bus during interrupt acknowledge cycles. To avoid confusion bit D0 for each Status/ID is predefined. If the IRQ levels for both interrups are set to eaqal values indicating same priority the the IRqst0 is acknoledged first channel FastADC with 14 bit resolution

19 VME-Address mapping Control & Status Register 0 (CSR0): Offset: $0006 Access Mode: A16D16, R D15 D08 D07 D00 Read LAST_LOC[15:2] 0 0 Control & Status Register 1 (CSR1): Offset: $0008 Access Mode: A16D16, R/W D15 D08 D07 D06 D05 D04 D03 D00 Write x x CH[2:0] x x x x Read 0 0 CH[2:0] 0 LAST_LOC[18:16] During each conversion cycle (ADC clock cycle) the recent address from the ADC controller is stored in the registers CSR1 and CSR0. After the sampling has been finished these registers contain the last address date have been written to. CH[2:0] defines the ADC channel from which data can be read directly from last memory location (see next). Read last data from memory: Offset: $000A Access Mode: A16D16, R Read D15 D08 D07 D00 last writen ADC-Data from selected channel In conjunction with CSR1 ( CH[2:0]) conversion data can be read directly from the last written memory location. Clear Interrupt Request 0: Offset: $000C Access Mode: A16D16, W Write D15 dummy D00 Clear Interrupt Request 1: Offset: $000E Access Mode: A16D16, W Write D15 D00 dummy Writing to this location clears the coreesponding interrupt request independently wether Auto-Clr is set or not. 8-channel FastADC with 14 bit resolution 19

20 VME-Address mapping 5.3. Description of the ADC Control Registers The next registers control the operation of the ADC. Trigger Register: Offset: $0010 Access Mode: A16D16, R/W D15 D00 Write Read # of triggers to take # of triggers to take Whithin this register the number of trigger to accept ( from 1 to 65535) is set. If the setted number is reached the conversion process is stopped. Sample Register: Offset: $0012 Access Mode: A16D16, R/W D15 D00 Write Read # of samples to take # of samples to take This register defines the number of samples (from 1 to 65535) to take after a trigger has been received. ADC Control Register: Offset: $0014 Access Mode: A16D16, R/W D15 D14 D13 D12 D11 D09 D08 D07 D05 D04 D03 D02 D00 Write Ch3 Ch2 Ch1 Ch0 x x IntTrg IntClk x x x HI/LO DisWr CMD Read Ch3 Ch2 Ch1 Ch0 x x IntTrg IntClk x x x HI/LO DisWr CMD CMD defines the operation executed by the ADC. The following commands are executable : - CMD=0 - Clear; Initializes the ADC. This command can be given at any time. - CMD=1 - Sample; After a trigger S samples ( Sample Register) are stored within the memory. Conversion stops after T triggers ( Trigger Register). Each time the sample counter reaches zero an interrupt (if enabled) is generated. If both, the sample counter and the trigger counter reaches zero a second interrupt (if enabled). The SRAM address counter is cleared and CMD is set back zero. - CMD=2 - Normal; After a trigger S samples are stored within the memory. Conversion stops on hardware reset or if CMD=0 is given. The value within the Trigger Register is ignored but must be greater the zero. Each time the sample counter reaches zero an interrupt (if enabled) is generated. - CMD=4 - StopAfter: This enables the ADC to sample data continuosly ( free - running ). Data taking will be stopped S samples after a trigger was received. The value within the Trigger Register is ignored as well. The SRAM address counter is cleared after end of conversion and CMD is set back to zero. If a trigger was received The value CMD can be used to check the status of the ADC wether it is running or not channel FastADC with 14 bit resolution

21 VME-Address mapping All comands can be given also with DisWr=1. This disables writing to the SRAM and is for hardware debugging purposes only. HI/LO defines the frequency mode of the ADC. If the HI/LO-bit is cleared the ADC is operating in low frequency mode. The ADC can operate in this mode with a sample rate up to 2 MSample/s. For higher sample rate (max. sample rate = 10MSample/s) the HI/LO-bit must be set. For IntClk=0 the external clock signal is used. IntClk set to 1 enables the internal ADC clock. The clock frequency then is set by writing a number between 7 and to the Clock Divider Register. IntTrg cleared selects external trigger source. If IntTrg is set to 1 then internal triggering is enabled. Writing CMD=1 automatically T triggers with S samples are taken. For a single software trigger the number of triggers should be set to one. With CMD=2 the ADC is automatically re-triggered until CMD=0 is given. During a conversion cycle data from all ADC channels are send to the DSP port ( HI/LO=0 ). If the ADC is working in high frequency mode ( HI/LO=1 ) only data from selected channel defind by CH[3:0] are send to this port otherwise ADC data are send one by one to DSP independent from the content of CH[3:0]. Delay Register: Offset: $0016 Access Mode: A16D16, R/W D15 D08 D07 D05 D04 D00 Write x x x x Delay Read Delay The phase of internal ADC clock can be adjusted whith respect to the external clock signal in steps of 5ns. The maximum delay is 100ns. The delay is defined by setting bit0 through bit4 of this register. The setting of the delay effectcs all ADC channels. Trigger Counter: Offset: $0018 Access Mode: A16D16, R Read D15 # of triggers left This register is read only and contains the actuel contents of the trigger counter. D00 Sample Counter: Offset: $001A Access Mode: A16D16, R Read D15 # of samples left This register contains the actuel contents of the sample counter. D00 8-channel FastADC with 14 bit resolution 21

22 VME-Address mapping Clock Divider Register: Offset: $001C Access Mode: A16D16, R/W Read D15 The register is used if the internal ADC-clock is used. The sample rate then is defined to be 66MHz divided by N. One has to care about the maximum sample rate of the ADC which is 10MHz ( N min =7 ). N D channel FastADC with 14 bit resolution

23 VME-Address mapping 5.4. ADC memory address mapping and data lines The data from the memory can be accesse eather via A32 mode (extended, AM=$09 or AM=$0D) or A24 mode (standard, AM=$39 or AM=$3D) depending on the setting of jumper J41 (close to the address jumpers). Double byte (D16) or Quad byte (D32) data transfere access is accepted. Address Mode A24 A32 JP41 closed open TABLE 7. Memory address mode selection The table below shows the mapping of the ADC data. Address D31 D16 D15 D00 ADC-Data $ ADC Channel 2 ADC Channel 1 0 MEM1 512kbyte $7 FFFC $ ADC Channel 4 ADC Channel N= (max) MEM2 512kbyte $F FFFC $ ADC Channel 6 ADC Channel 5 MEM3 512kbyte $17 FFFC $ ADC Channel 8 ADC Channel 7 $1F FFFC MEM4 512kbyte 8-channel FastADC with 14 bit resolution 23

Operating Instructions

6 18 GHz Frequency Synthesizer PFS-618-CD-1 Operating Instructions 1) Frequency Control The Frequency Control Code is constructed of 17 bits (A0 - A16). The following equation and table describe the frequency