IEEE SENSORS JOURNAL, VOL. 9, NO. 2, FEBRUARY

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1 IEEE SENSORS JOURNAL, VOL. 9, NO. 2, FEBRUARY A Snapshot CMOS Image Sensor With Extended Dynamic Range Alexander Belenky, Alexander Fish, Member, IEEE, Arthur Spivak, and Orly Yadid-Pecht, Fellow, IEEE Abstract In this paper, a proof of concept for a snapshot CMOS image sensor with extended dynamic range is presented. A prototype of pixels has been fabricated using the 1-poly 4-metal CMOS 0.35 m process available through MOSIS and was successfully tested. The measurements from the test chip showed that the fabricated imager allows wide dynamic range (WDR) operation in a snapshot readout mode. This DR extension has become possible due to a unique in-pixel architecture allowing automatic adaptation of each pixel in the array to its illumination level. To reduce the pixel power dissipation various low-power design techniques have been utilized in the pixel design. A single pixel occupies 18 18( m) 2 and dissipates 23 nw with 8 bit DR expansion at room light level, and 29 nw at high illumination level, equivalent to clear sky at video rate. The power dissipation of the whole sensor (including the supporting circuitry) is 450 W at video rate. Sensor design is described, design considerations are shown and measurements from the test chip are presented. Index Terms CMOS imagers, high dynamic range, image sensor, integration time, low-power, very large scale integration (VLSI). I. INTRODUCTION F AST development of low-power miniature CMOS image sensors triggers their penetration to various fields of our daily life. CMOS imagers offer significant advantages in terms of low-power, low-voltage, flexibility, cost, and miniaturization. These features make them very suitable for a variety of applications where both low-power and wide intrascene dynamic range (WDR) are the main demands. While power reduction is usually achieved by technology scaling and aggressive supply voltage reduction [1], it however affects the output swing of the sensor and thus decreases its dynamic range (DR) [1] [3]. The narrow DR of image sensors entails saturation of a pixel with high sensitivity, in case of high illumination levels, and part of the information can be lost. DR insufficiency of conventional video cameras is a serious problem in realizing a robust vision system for taking images consisting of wide illumination conditions in the same scene. Different solutions for extending the DR in CMOS image sensors have been presented in recent years [5] [30]. A comprehen- Manuscript received March 02, 2008; revised June 23, 2008; accepted July 16, Current version published January 09, The associate editor coordinating the review of this paper and approving it for publication was Prof. Paul Regtien. The authors are with the VLSI Systems Center, Department of Electrical and Computer Engineering, Beer-Sheva 84105, Israel ( belenky@ee. bgu.ac.il; afish@ee.bgu.ac.il; spivakar@bgu.ac.il; oyp@ee.bgu.ac.il). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /JSEN sive summary of existing solutions and their comparisons have been presented in [4]. In the aforementioned paper, the WDR algorithms have been divided to six general categories, however nowadays we can divide them to eight categories, since additional WDR solutions have been proposed throughout the past nine years. The updated classification of WDR schemes and their brief overview is presented below: (a) Companding sensors, such as logarithmic, compressed response photodetectors [5] [7]. These sensors achieve very high DR and work in continuous, i.e., nonintegrating mode and, therefore, can have a higher time sampling resolution per pixel, if required. A disadvantage of these sensors that the mismatch between the transistors will cause a nonlinear fixed pattern noise (FPN); (b) Multimode sensors, that have a linear and a logarithmic response at dark and bright illumination levels, respectively, i.e., they are able to switch between a linear and a logarithmic mode of operation[8], [9]. Usually, they require extended settling time when switching and require massive signal post-readout processing; (c) Frequency-based sensors, where the sensor output is converted to pulse frequency [10] [12]. In these sensors, the DR extension can exceed five decades, but the pixel structure becomes complex, and the power consumed by each pixel is increased; (d) Sensors, where a capacity well adjustment method is applied. One of the possible implementations of this method is to control the potential depth of the sensing node well [13]. An alternative implementation utilizes an additional fixed capacitance where the overflowing charge is being accumulated [14], [15]. These sensors achieve an increased DR, which is clamped by the photodiode and the overflow capacitances ratio, while keeping the pixel structure very simple; (e) Time to First Spike sensors, where the information is encoded at the time the pixel was detected as saturated [16] [18]. Combination of saturation time information with the reference voltage signal provides good flexibility for this WDR scheme, however, it requires quite complex signal processing at the chip periphery; (f) WDR sensors with global control over the integration time. Multiple exposures method is an example of global control over the integration time, where the whole sensor is let to integrate for different exposure times regardless of the incoming light intensity [19] [23]. The final image can be reconstructed by choosing the closest value to saturation, for each pixel. In [22], the pixel value is constructed by successive comparisons to a monotonic ramp signal after every integration slot. After integration stops, the pixel mantissa and the extension exponent are ready for readout. However, this method requires allocating memory to store an intermediate digitized pixel value. Alternatively, the final image can be reconstructed by combining the pixel values captured at different exposure times and the time the pixel saturated [23] X/$ IEEE

2 104 IEEE SENSORS JOURNAL, VOL. 9, NO. 2, FEBRUARY 2009 Another variation of the multiple exposures algorithm was presented in [24] and [25], where the shorter integration time overlapped the longer one. During the integration, the array was reset to some intermediate well potential. Pixels that did not pass the mid-point barrier continued to integrate without intermediate information loss. The information loss caused by the mid-point reset was compensated by autoscaling the charge accumulated during the shorter exposure time. Consequently, the signal-to-noise ratio (SNR) in low light intensity was improved in comparison to regular multiple exposures algorithm; (g) Sensors with local control, where different areas within the sensor can have different exposure times [26]; and (h) Sensors with autonomous control over the integration time, in which the integration time is adjusted by each pixel [27] [30]. The imager described in this paper is based on this method. This method can be regarded as a multi-reset algorithm and utilizes the conditional reset scheme, which is implemented at the pixel level. The pixel structure remains simple and the final signal processing is very straightforward, i.e., the data is being integrated on the pixel capacitance; followed by readout of the signal and reset levels for subtraction and final A-D conversion. Thus, there is no need to choose between optional signals received from multiple A-D conversions that are unavoidable in the multimode and the multiple exposure sensors. Another advantage of the sensors proposed in [27] [30] is that the threshold value to which the pixel is being compared to is time invariant, thus there is no need to generate highly precise global time varying voltage references. Conventional CMOS imagers operate in a rolling shutter mode [3] which leads to image deformation in times when there is relative motion between the imager and the scene. The imager, operating in the global shutter (snapshot) regime, utilizing a memory element inside each pixel solves this problem and provides capabilities similar to a mechanical shutter. This allows simultaneous integration of the entire pixel array, and then preventing exposure while the image data is read out. Recently, we have proposed a new WDR CMOS image sensor architecture that can deal with all the above mentioned challenges of CMOS image sensors and presented its simulation results [30]. This proposed imager was expected to provide wide DR by applying adaptive exposure time to each pixel, according to the local illumination intensity level. Driven by low-power dissipation requirements, the proposed pixel was designed to operate with dual low-voltage supplies (1.2 and 1.8 V) and utilized an advanced low-power sensor design methodology. This methodology included implementation of a special low-power and area efficient components, such as comparator and multiplexer, as well as various general techniques for power reduction. The goal of this paper is to provide a proof of concept for the previously designed imager. Since the imager employs nonstandard circuits and utilizes complicated pixels, each consisting of 18 transistors, this proof of concept stage is essential for further snapshot WDR sensor development. This paper presents measurements from a test chip and shows that the fabricated imager is fully operational and allows extension of dynamic range, as expected. In addition, design considerations, such as threshold voltage considerations, low-power considerations, and noise analysis are presented. Fig. 1. The photograph of the fabricated chip with highlighted major building blocks. The remainder of this paper is organized as follows. Section II presents a brief description of the sensor and its operation. Design considerations are discussed in Section III. Section IV presents measurements from a fabricated prototype. Conclusion and future research are outlined in Section V. II. SENSOR DESCRIPTION AND OPERATION This section describes the scheme of the proposed pixel and briefly explains general principles of its operation. A more detailed description of the imager operation can be found in our former publication [30]. A photomicrograph of the chip that highlights its major building blocks is shown in Fig. 1. The sensor consists of a pixel array, one row decoder, two column decoders, sample and hold (S/H) circuits, and a digital storage. Two column decoders for the pixel array work in parallel and are used to retrieve the mantissa and exponent values, correspondingly. Fig. 2 shows the implementation scheme of the fabricated snapshot WDR pixel. The pixel operation is based on the multireset algorithm for DR expansion, recently successfully implemented by our group in rolling shutter imager [27]. According to this algorithm, the full integration time for the frame is subdivided into intervals, preferably in a sequence of progressively shorter intervals. At the end of each interval, a nondestructive readout of the pixels is performed, and the readout level of each pixel is compared to a respective threshold. Based on the comparison result, it is determined if the pixel will saturate before the end of the frame. If it is determined that the pixel will saturate, the pixel is reset. Resetting the pixel at an intermediate point during the integration period significantly reduces the probability that the pixel will saturate prior to the final readout. The binary information concerning having the reset applied or not is saved in a digital storage, to enable proper scaling of the value read. The incident light intensity may then

3 BELENKY et al.: A SNAPSHOT CMOS IMAGE SENSOR WITH EXTENDED DYNAMIC RANGE 105 Fig. 2. Scheme of a single WDR snapshot pixel. be calculated at the end of the integration period by multiplying the final readout level by a scaling factor which is based on the length of time since the last reset. This length of time may be determined from knowledge of how many times the given pixel was reset over the entire integration period. Therefore, the light intensity of the pixel is calculated as where relates to the incident light intensity, is the analog or digitized output value that has been read out at the end of the integration period, is a chosen constant ( ), for example 2, that relates to the division of the integration time into progressively shorter intervals and represents how many times the given pixel was reset over the entire integration period. The presented circuit operates as follows: at the beginning of the frame the pixel is reset by applying 0 and 0. This way the internal line Reset is equal to 1 h (1.8 V) independently on the internal line Comp out value, charging the photodiode ( ) and internal line Comp_in ( )to, where ( 1 h ), ( 1 ) and is the threshold voltage of an NMOS. At the same time, the internal line Comp out is precharged to 1 h by negative pulse of 0. The reset phase is stopped by applying 1 and 1 and photodiode starts discharging, according to the energy of (1) incident light. At this stage, the total capacitance connected to the photodiode is given by. At the end of the first interval the output of the photodiode (voltage on ) is compared with an appropriate threshold, associated with the switching threshold voltage of the comparator, implemented by a conventional inverter. This comparison is performed by enabling the inverter operation ( 1 h and 0 ). If, meaning that the pixel will saturate at the end of the integration time, then 1 h (determined by the inverter). At the same time, Cond Reset falls to 0 by applying short negative pulse, causing the and to operate as a standard inverter and enabling operation of the inverter, consisting of, and. As a result, (for 1 h ) the photodiode is reset again. The binary information concerning having the reset applied or not is saved locally in storage capacitor ( ) by 0 at the time when 0 and is transmitted during the next interval to the external digital storage in the upper part of the sensor array, associated with the certain pixel, to enable proper scaling of the value read. The readout of this digital signal is performed through the regular output chain, used for analog signal readout, by allowing 1. If, i.e., meaning that the pixel will not saturate at the end of the integration time, then 0 (determined by the inverter). In this case, the photodiode is not reset ( 0, 0 0 ) and transistor is turned off, separating and. Once the comparison is stopped by returning the inverter to the sleep mode and applying 1 and 1, the photodiode continues discharging, according to the energy of incident light. This time, the total capacitance connected to the photodiode is given only by. At the end of subsequent intervals (when comparisons are performed again), is already disconnected from the, causing the voltage saved on ( ) to be compared to the threshold voltage, produced by the inverter. Thus, no resets are applied until the full integration time is finished. At the end of the full integration time, the capacitor is connected to the capacitor by applying 0 and the final photodiode voltage on the capacitor is determined by the charge transfer between and. This way this final voltage is independent of whether transistor was closed or open during the last interval. Note, in case, when Comp out was equal to 1 h (reset was performed at the last comparison), the capacitor was already connected to the capacitor. The next stage is transfer of the charge accumulated in the photodiode capacitor to a storage capacitor, by applying 1 h. Before this charge transfer, the storage capacitor is reset to by applying 0. Once this charge transfer has been completed, the photodiode is able to begin a new frame exposure, and the charge, newly transferred to the in-pixel memory, is held there until it is read out at its assigned time in a row-by-row readout sequence through the output chain.

4 106 IEEE SENSORS JOURNAL, VOL. 9, NO. 2, FEBRUARY 2009 Fig. 3. Threshold voltage derivations. III. DESIGN CONSIDERATIONS A. Threshold Voltage Considerations The overall idea of the algorithm is to avoid the effect of pixel saturation. As previously mentioned, the algorithm compares the readout level of each pixel to a respective threshold voltage at the end of each interval and takes a decision based on the anticipation if during the whole integration period the pixel will be saturated or not. Therefore, assuming that the pixel value was first compared at, the intrinsic (theoretical) threshold value should be chosen in such a way, so that a straight line (dash-doted line number 1 in Fig. 3) that describes discharging of the pixel during, through (photodiode reset voltage) at and the threshold voltage at the first subintegration period, will not cross the pixel saturation voltage before the whole integration time is due. The equation of this straight line is given by where is a maximum pixel voltage swing equal the difference between and values. To find the value of the intrinsic threshold voltage, the is substituted into the line equation, resulting in the following formula: In real designs, each comparator has its own offset voltage. Therefore, for two different comparators having two different offset voltages the comparison will be performed at different points even if the same threshold voltage was set. Fig. 3 shows an example of two pixels, discharging by the same illumination level and being processed using two comparators having different offset values. The same was applied for both cases. As can be seen, there is an immunity to change in comparator offsets, since in both cases the final results are the same. In the first case (shown by the solid line number 2), the pixel value did not pass the threshold voltage and, therefore, it was not reset at the first comparison. In the second case (2) (3) (shown by the dashes line number 3), the pixel value did pass the threshold voltage and, therefore, it was reset at the first comparison. However, the final results [given by (1)] remain similar for both cases. Note, in the second case, the SNR of the pixel is reduced since the integration time was reduced in this case. A more detailed description on influence of integration time on the sensor SNR can be found in [21] [23]. Although the sensor provides immunity to the comparator offsets, it is very important to choose the threshold that ensures that all pixels in the array will not saturate at the end of the whole integration period. This threshold voltage is given by where is the absolute value of the maximum comparator offset in the array. B. Noise Considerations Noise contribution in the fabricated imager can be classified according to the following noise generation sources: thermal ( reset ) noise induced by reset operation, fixed pattern noise (FPN), caused by process variations and quantum shot noise due to fluctuations in the photo and dark currents. The overall contribution of the reset noise in the imager is given by The noise variance resulted in reset operation contributed by the capacitance is doubled since the readout procedure does not utilize true CDS. Assuming that the sensor operates at room temperature, the calculated noise voltage deviation is 1.46 mv. At the end of integration period,, the final voltage on the capacitance is given by where is the effective integration time, representing the period from the last reset to and is the nominal pixel reset voltage on the sensing node. is defined by the (4) (5) (6)

5 BELENKY et al.: A SNAPSHOT CMOS IMAGE SENSOR WITH EXTENDED DYNAMIC RANGE 107 and reset values ( and ) and the magnitude of each of the three aforementioned pixel capacitances In order to calculate the final output voltage [ from (1)] that represents the incident light intensity fallen on the pixel, two samples are performed at the end of the integration period. During the first sample, the is readout, while during the second one the value is sampled. The readout value of the first sample is given by where is the SF transistor threshold voltage, is the bias current in the SF and is the transconductance parameter of the same transistor. The value of the second sample is given by The FPN noise can be divided into two general components: gain and offset. The gain component is caused by process fluctuation in each parameter of the pixel transfer function (active area, capacitance magnitude ( ). The offset FPN component arises from variations in the pixel dark current, SF input transistor threshold ( ) and strength ( ) and differences in column current source. Most of the offset FPN components can be eliminated by subtraction of these two aforementioned samples; however, the variations in capacitors and dark current values between different pixels are not compensated. Using (7) (9), the deviations in as a function of the mismatch in each pixel parameter are derived. For example, assuming 1% mismatch in the and, the maximal output voltage variation will be around 941. Future FPN reduction methods include digital double sampling (DDS) that will reduce the noise generated in an analog subtraction. Moreover, the pixel design and implementation will be adapted to increasing demands of the future chip performance by means of operation frequency, spatial resolution and power dissipation. Therefore, we will minimize gradients that can occur when biasing large pixel arrays that operate at high switching frequencies, while keeping the switching power minimized. Another noise mechanism that should be addressed is the quantum ( shot ) noise. This process also causes fluctuations in the value. The maximal variance in the readout signal can be described as (7) (8) (9) (10) where is the current that causes the photodiode to discharge completely during the integration time. Using this relation, we can calculate that the deviation caused by this noise process is bounded by 1.15 mv and it is very close to the reset noise component value. Therefore, the reset noise is the dominant component for all illumination levels. C. Low-Power Design Considerations A number of approaches for power reduction in CMOS image sensors were presented in the literature [1], [31]. According to these approaches, the power can be reduced at different design levels technology, device, circuit, logic, architecture, algorithm, and system integration. In the presented WDR imager design, much efforts have been done to reduce power dissipation by utilizing various design techniques at the circuit and logic level. These techniques have allowed reduction of both peak power dissipation (during the snapshot operation) and average power, dissipated by the pixel. The utilized methods can be divided into four main parts. (a) Power reduction by leakage current control in analog and digital circuits differentiation between the active and sleep modes of the certain circuit by insertion of a sleep transistor was applied on the in-pixel circuits like Mux and comparator. This technique relies on the reduction of the leakage current using the stacked scheme by stacking two off transistors, the subthreshold leakage current is reduced significantly compared to a single off device due to simultaneous reductions in gate-source, body bias, an drain-source voltages [32]. However, the insertion of sleep transistors slightly reduces the fill factor and increases the capacitance of the Sleep wire, which is shared by all pixels in the array and is driven by an external digital driver. Since the operation of the pixel is fully parallel, as described in Section II, the influence of the increase in the delay due to the insertion of the sleep transistors is negligible compared to the whole integration time (a few nano seconds compared to 30 milliseconds of the integration time). (b) Low voltage operation reduction of the power supply voltage is a key element in low-power CMOS imagers. However, the design of a low-voltage CMOS sensor involves several well-known challenges. Employing multiple voltage supplies can relax the problem. The idea of multiple grows up from the dual- approach in the digital circuit design, where the gates of the noncritical paths have the reduced supply voltage, while those on the critical paths have. This results in reducing the power without degrading the entire circuit performance. Similarly to the digital circuits, in the designed sensor high (1.8 V) was used in the critical places, significantly influenced by reduction, while low-voltage supply (1.2 V) was applied in others. (c) Applying various low-power digital design styles for power reduction in the digital circuitry in general, the custom design of the particular blocks in digital circuitry using nonstandard design techniques, like pass-transistor-logic (PTL) may significantly improve power dissipation. Custom digital design can be very useful when the in-pixel digital processing approach is used. In the presented WDR imager, a nonstandard low-power Mux, implemented using gate diffusion input (GDI) design technique was used. The GDI method is based on a simple cell that contains four terminals, allowing implementation of various complex functions using only

6 108 IEEE SENSORS JOURNAL, VOL. 9, NO. 2, FEBRUARY 2009 Fig. 4. Setup for picture capture. two transistors [33]. It has been proven that this Mux implementation leads to significant reduction in power dissipation, compared to a standard CMOS implementation. In addition, it employs only two transistors ( and ) to implement the Mux functionality. In the case of the discussed snapshot pixel, a regular state of the Mux circuit is 1 and 1 and if 1, therefore leakage current does not exist most of the time. (d) Optimization of digital and analog sensor output chains a standard three-transistor APS pixel includes only one analog output and two digital control inputs. An advanced sensor usually has more complicated structures. In addition to an increased number of analog outputs and digital control inputs, it can include digital outputs generated by the pixel. The demand for this increased number of pixel inputs and outputs, the desire for acceptable fill factor and the requirement for low-voltage operation result in the necessity to optimize the analog and digital sensor output chains for area efficient low-power low-voltage operation. In this design, the same output chain was employed both for analog and digital signals to reduce the area and power dissipation of the imager. Fig. 5. Optical test setup. Fig. 6. Measured quantum efficiency. IV. EXPERIMENTAL RESULTS A32 32 imager was successfully fabricated using standard mixed-signal TSMC 0.35 process available through MOSIS. Each pixel has a size of and a fill factor of 15%. To verify the proposed concept, the fabricated test chip was tested using dual power supply voltages (1.2 and 1.8 V), as described in Section II. All control signals were generated externally using an field programmable gate array (FPGA) based test board. The output signals were downloaded to the PC, allowing image capture, processing and presentation. The test setup is shown in Fig. 4. The setup allowed imager operation at up to 1000 frames/s and DR extension of up to 8 bits. Fig. 5 depicts an optical setup used for the test chip characterization. This setup is common for most of optical tests and consists of: a) a halogen lamp; b) a motorized filter wheel with a long-pass filters with cutoff wavelengths within the range of the visible light spectrum; c) monochromator; d) integrating sphere; and e) reference diode. The integration sphere is used to obtain Fig. 7. Imager normalized output voltage as a function of incident illuminance without applying the WDR algorithm. a uniform illumination on the chip interface. Light intensity is controlled by the monochromator slit input and is measured by the reference photodiode. The spectral response of the fabricated sensor is depicted in Fig. 6. The maximum quantum efficiency (QE) of 32% is achieved at 600 nm wavelength. Fig. 7 shows measurements of the image sensor normalized output voltage as a function of incident illumination without applying the WDR algorithm. The measurements were performed by acquisition of numerous frames at varying light intensities.

7 BELENKY et al.: A SNAPSHOT CMOS IMAGE SENSOR WITH EXTENDED DYNAMIC RANGE 109 Fig. 8. Imager normalized output voltage as a function of incident illuminance: (a) without applying the WDR algorithm and (b) with 3 bits DR extension. Each point represents an average of 50 frames for a given intensity. The sensor linearity and output swing is defined by the in-pixel source follower amplifier. Under these conditions, the measured DR is 49 db. According to simulation results, presented in [30], the maximum DR without expansion was 57 db. We assume that the main reasons of this discrepancy between the results are switched capacitor noise with sharing between the comparator and photodiode capacitor, kickback comparator noise, and reset path jitter that have not been taken in account in the analysis presented in Section III. Fig. 8 presents comparison of the output voltage as a function of incident illumination measurements performed without applying the algorithm (similar to Fig. 8 and with 3 bits DR expansion (equivalent to 18 db extension). It can be seen that the pixel performs reset operation each time the photodiode voltage reaches the comparator threshold according to the incident light intensity. In this design, the comparator threshold ensures that the pixel will not saturate at the end of the integration time (see threshold voltage consideration in Section III). To do so, the output voltage in Fig. 8 does not reach its maximum possible value (630 mv) and is reset at 480 mv, reducing pixel SNR [22], [23]. Fig. 9, shows the scene observed by the proposed imager at different illumination conditions. The scene observed at room light illumination conditions is presented in (a). The same scene observed with a laser light on the object is shown in (b). In this test, the imager operated without WDR expansion. As can easily be seen, some of the pixels were saturated because of the strong light conditions. The scene observed at the same illumination conditions (with a strong light on the object) is seen in (c). However, in this case, 1-bit WDR expansion was applied. It can be clearly seen that, as expected, the part of the pixels saturated in (b), did not saturate in this case. Fig. 9(d) demonstrates the imager performance under the same illumination with 2 bits extension. Note, both Fig. 9(c) and (d) aim to prove the functionality of the imager, showing only the output of the imager. Therefore, the images give an impression of noise presence. In order to present the actual pixel values [see (1)], the value of each pixel has to be calculated according to (1) and should then be com- Fig. 9. (a) Scene observed at room light illumination conditions. (b) Scene observed at room light conditions with a laser light on the object without WDR expansion. (c) Scene observed at room light conditions with a laser light on the object with 1-bit WDR expansion. (d) Scene observed at room light conditions with a laser light on the object with 2-bit WDR expansion. TABLE I POWER DISSIPATION OF A SINGLE PIXEL FOR DIFFERENT ILLUMINATION LEVELS pressed to suit an 8-bit monitor resolution. There are many ways to present WDR imagers on 8-bit monitors [34], [35], however, this issue is out of scope for this paper. Table I presents power dissipation of a single sensor for different illumination levels at video rate ( ). To perform these measurements, the power supply of the pixel array was separated from all support circuitry, the power of the

8 110 IEEE SENSORS JOURNAL, VOL. 9, NO. 2, FEBRUARY 2009 TABLE II IMAGE SENSOR PERFORMANCE FIGURES OF MERIT proposed pixel is operated by dual low voltage supplies (1.2 and 1.8 V) and utilizes an advanced low-power sensor design methodology. The measurements from the test chip have shown that the fabricated imager allows DR expansion of up to 97 db. REFERENCES whole array was measured and divided by The power was measured in three cases: (a) no DR expansion algorithm was applied; (b) expansion of 4 bit (equivalent to ); and (c) expansion of 8 bit (equivalent to ). As can be seen, the pixel has very low-power dissipation of 23 nw for 8 bit expansion at room light and 29 nw at high illumination level equivalent to clear sky. The power dissipation of the whole sensor (including the supporting circuitry) was 450. Since the proposed imager was implemented in 0.35 CMOS technology, a relatively large pixel size and a low fill factor have been achieved. The imager implementation in more advanced technologies can decrease the pixel size or/and increase the fill factor. Scaling to 0.18 and larger technologies is straightforward and can be easily calculated using a scaling factor. However, the scaling to more advanced processes (below 0.18 ) is not straightforward since it may require techniques for more aggressive power reduction due to increased leakages. In addition, the reduced supply voltage in these technologies may also result in the need to change the inpixel circuitry, while remaining with the same algorithm. It is also very important to mention, that although a proof of concept for the small pixel array was presented, the array can be easily enlarged to any size since the pixels operation is fully parallel and the requirements for readout operation are relaxed. The only restriction on the array scaling to higher pixel counts is the peak power dissipation during the parallel operation of all pixels in the array. However, this issue can be resolved on the layout level by designing critical wires wide enough. It is obvious, that the size of the memory, decoders and S/H circuits will be scaled accordantly with the pixel array scaling. Table II presents the chip attributes. V. CONCLUSION We have presented a low-power global shutter CMOS image sensor with ultra-wdr. A prototype of pixels has been fabricated using the 1-poly 4-metal CMOS standard 0.35 process available through MOSIS and was successfully tested. The proposed imager performs snapshot image acquisition and offers a customized, linear, large increase in the dynamic range by implementing smart, low-power circuits for in-pixel autoexposure. Driven by low-power dissipation requirements, the [1] K. Cho, A. I. Krymski, and E. R. Fossum, A 1.5-V 550 W autonomous CMOS active pixel image sensor, IEEE Trans. on Electron Devices, Special Issue on Image Sensors, vol. 50, pp , Jan [2] E. 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Süsstrunk, High dynamic range image rendering with a retinex-based adaptive filter, IEEE Trans. Image Process., vol. 15, no. 9, pp , Sep [35] M. D. Fairchild and G. M. Johnson, icam framework for image appearance, image differences, and quality, J. Electronic Imaging, vol. 13, no. 1, pp , Jan Alexander Belenky received the B.Sc. degree in physics and the M.Sc. degree in electrooptics engineering from Ben Gurion University, Beer Sheva, Israel, in 1995 and 2003, respectively. He is now working towards the Ph.D. degree at Ben Gurion University. From 1998, he has been working at the VLSI Systems Center, where he is responsible for the VLSI Laboratory. His current interests are smart CMOS image sensors, image processing, and imaging systems. Alexander Fish (S 04 M 06) received the B.Sc. degree in electrical engineering from the Technion, Israel Institute of Technology, Haifa, Israel, in 1999, and the M.Sc. degree in 2002 and the Ph.D. degree (summa cum laude) in 2006, respectively, from Ben Gurion University, Israel. He was a Postdoctoral Fellow in the ATIPS Laboratory at the University of Calgary (Canada) from 2006 to Currently, he is a faculty member in the Electrical and Computer Engineering Department at the Ben-Gurion University. He has also published two book chapters. He has authored over 50 scientific papers and patent applications. His research interests include low-power CMOS image sensors, analog and digital on-chip image processing, algorithms for dynamic range expansion and low-power design techniques for digital and analog circuits. Dr. Fish was honored with the Electrical Engineering Dean Award at Technion in 1997 and with the Technion President s Award for Excellence in study in 1998, respectively. He was a coauthor of two papers that won the Best Paper Finalist awards at the ICECS04 and ISCAS05 conferences. He was also awarded the Young Innovator Award for Outstanding Achievements in the field of Information Theories and Applications by ITHEA in In 2006, he was honored with the Engineering Faculty Dean Teaching Excellence recognition at Ben- Gurion University. He has served as a referee in the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I, the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II, Sensors and Actuators Journal, the IEEE SENSORS JOURNAL, SPIE Optical Engineering Journal, as well as ISCAS, ICECS, and IEEE Sensors Conferences. He was also a co-organizer of special sessions on smart CMOS Image Sensors at the IEEE Sensors Conference 2007 and on low-power Smart Image Sensors and Beyond at the IEEE ISCAS Arthur Spivak received the B.Sc. degree in electrical engineering from Technion, Israel Institute of Technology, Haifa, Israel, in He is currently working towards the M.Sc. degree in electronics. In 2006, he joined the VLSI Systems Center, where he has been engaged in the research, development, and design of the analog and digital circuits integrated in CMOS imagers. Orly Yadid-Pecht (S 90 M 95 SM 01 F 07) received the B.Sc. degree in electrical engineering, and the M.Sc. and D.Sc. degrees from Technion, Israel Institute of Technology, Haifa, Israel, in 1984, 1995, and 1990, respectively. She was a National Research Council (USA) Research Fellow from 1995 to 1997 in the areas of advanced image sensors at the Jet Propulsion Laboratory (JPL), California Institute of Technology (Caltech). In 1997, she joined the Ben-Gurion University, Israel, as a member in the Electrical and Electro-Optical Engineering Departments. There she founded the VLSI Systems Center, specializing in CMOS image sensors. Since 2003, she has also been with the ATIPS Laboratory at the University of Calgary, Canada, promoting the area of Integrated sensors. Her main subjects of interest are integrated CMOS sensors, smart sensors, image processing, neural nets, and microsystem implementations. She has published over 100 papers and patents and has led over a dozen research projects supported by government and industry. Her work has over 200 external citations. In addition, she has coauthored and coedited the first book on CMOS Image Sensors: CMOS Imaging: From Photo-Transduction to Image Processing, (2004). Dr. Yadid-Pecht was an Associate Editor for the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS and the Deputy Editor-in-Chief for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART I. She is currently an Associate Editor for the IEEE TBioCAS, a member of the IEEE Sensors Council, and a member of several other technical and steering committees. She was an IEEE Distinguished Lecturer of the Circuits and Systems Society in She was also the General Chair of the IEEE International Conference on Electronic Circuits and Systems (ICECS).