Awinner-take-all (WTA) circuit, which identifies the

Transcription

1 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 52, NO. 3, MARCH High-Speed and High-Precision Current Winner-Take-All Circuit Alexander Fish, Student Member, IEEE, Vadim Milrud, and Orly Yadid-Pecht, Senior Member, IEEE Abstract A CMOS high-performance current-mode winnertake-all circuit is presented. The circuit employs a novel technique for inhibitory and excitatory feedbacks based on input currents average computation, achieving both high speed and high precision. The circuit is designed for operation with a wide range of input current values, allowing its integration with circuits operating both in subthreshold and in strong inversion regions. Two circuits, each for a different range of input currents, have been implemented in a standard m CMOS process available through MOSIS and are operated via a 3.3-V supply. Their operation is discussed, simulation results are reported and preliminary measurements from a test chip are presented. Index Terms Analog circuits, analog integrated circuits, CMOS analog integrated circuits, neural networks, winner take all (WTA). I. INTRODUCTION Awinner-take-all (WTA) circuit, which identifies the highest signal intensity among multiple inputs, is one of the most important building blocks in neural networks, fuzzy systems and nonlinear filters. Many WTA circuit implementations have been proposed in the literature [1] [19]. The MOS implementation of the WTA function was first introduced by Lazzaro et al. [1]. This very compact circuit optimizes power consumption and silicon area usage. It is asynchronous, processes all input currents in parallel and provides output voltages in real time. The first true current-mode (CM) WTA circuit, producing an output current that is proportional to the value of the winning current, was introduced by Andreou et al. [2] and Boahen et al. [3]. In 1993, the use of positive feedback to improve the performance of a CM WTA system was reported by Pouliquen et al. [4]. Several modifications to Lazzaro s design have been suggested in the past [5] [7]. The circuit has been modified by Starzyk and Fang [5] by improving precision and speed performance. In 1995, DeWeerth and Morris [6] have added distributed hysteresis using a resistive network. Distributed hysteresis allows the winning input to shift between adjacent locations maintaining its winning status, without having to reset the network. Additional modifications that endow the Lazzaro s WTA with hysteretic and lateral inhibition and excitation properties have been proposed by Indiveri [7]. Voltage-mode WTA works based on Lazzaro s circuit were Manuscript received March 9, 2004; revised July 13, This paper was recommended by Associate Editor A. G. Andreou. A. Fish and V. Milrud are with the VLSI Systems Center, Beer-Sheva 84105, Israel ( afish@ee.bgu.ac.il; milrud@ee.bgu.ac.il). O. Yadid-Pecht is with VLSI Systems Center, Beer-Sheva 84105, Israel, and also with the Department of Electrical and Computer Engineering, University of Calgary, AB T2N1N4, Canada ( oyp@ee.bgu.ac.il). Digital Object Identifier /TCSII presented [8], [9]. In 1995, this circuit was modified with feedback and inhibition by Wilson and DeWeerth [8] and later, in 1999, by Kalim and Wilson [9]. The performances of all WTA circuits can be measured in terms of speed, accuracy and power consumption. For example, some of them were designed to achieve high speed and high accuracy in high-speed, high-precision applications [10], [11], while [12], [13] were designed for pulse-coded neural networks. The fact that the WTA operation is fully parallel and can be distributed makes these circuits very useful in visual attention and tracking systems, where the localization of the most salient regions in an image and selection of salient targets in the field of view (FOV) are very important tasks. In these systems WTA networks are able to select and lock onto the input with the strongest amplitude, and to track it as it shifts from one pixel to its neighbor [20] [29]. Although WTA circuits are very useful in many applications and are very popular, they suffer from matching problems, especially in systems with a large number of inputs. A complete analysis of device mismatch limitations in large WTA circuits was first presented by Kumar et al. in 1993 [30], [31] and was a subject of further research in the later works [10], [32]. A floatinggate calibration technique to improve the performance/matching of a WTA circuit was presented by Miwa et al. [33] in This paper presents a novel high-speed and high-precision CM WTA circuit. The circuit employs inhibitory and local excitatory feedbacks based on input currents average computation, enhancing precision and speed performance of the circuit. Local excitatory feedback provides a hysteretic mechanism that prevents the selection of other potential winners unless they are stronger than the selected one by a set hysteretic current. The proposed circuit can be useful for integration with circuits operating in the strong inversion region and supplying input currents of 3 50 A, as well as for subthreshold applications with inputs of 0 50 na. Not as the previously presented WTA circuits, the proposed circuit achieves a very high speed [32 ns for high currents of 3 50 A (measured) and 34 ns for subthreshold currents (simulated)] in case when a very small difference between two input currents is applied (30 na for high currents and 1.8 na for subthreshold applications). These circuit performances are the direct result from very strong feedbacks applied in the circuit, causing however, higher power dissipation (87.5 W for high-input currents and 22.5 W for subthreshold currents), compared to existing low-performance WTA circuits, operating in subthreshold and optimizing power consumption [1], [5], [7]. The power consumption of the proposed circuit can be significantly reduced by decreasing the feedbacks values, while degrading the circuit performance /$ IEEE

2 132 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 52, NO. 3, MARCH 2005 Fig. 1. Cells 1 and k (out of n) of the proposed WTA circuit. Section II presents the proposed circuit architecture and describes its operation. The performance of the implemented circuits including simulation results, preliminary measurements from a test chip, as well a comparison to the existing WTA circuits are shown in Section III. Section IV concludes the paper. II. CIRCUIT DESCRIPTION Fig. 1 shows cells and (out of the interacting cells) of the WTA circuit. Cell receives a unidirectional input current, and produces an output voltage. This output has a high digital value if the input current is identified as winner and low, otherwise. The WTA circuit operates as follows: the drains of transistors of all cells of the array are connected to the drains of transistors by a single common wire with voltage. The circuit starts competition by applying 1 for a short period of time. This way the excitatory feedback and inhibitory feedback are cancelled. Assuming that all cells in the array are identical and 1 is applied, the current, through, is equal to the average of all input currents of the array, neglecting small deviations in the referenced input currents. is copied to by the pmos current mirror ( and ) and is compared with the input current copied by the nmos current mirror ( and ). If then, assuming the same drivability factor of and transistors. An increase in input current relative to causes a decrease in due to the Early effect. This way, during the reset phase, input currents of all cells are compared to the average of all input currents of the array, producing a unique output for every cell. The cell having the highest input current value produces the smallest voltage. With the completion of the reset phase, i.e. 0, the excitatory feedback and the inhibitory feedback are produced. The node inputs to the gate of pmos transistor; thus, the cell with smaller (highest input current) produces higher current through and. This current is copied by the nmos current mirror ( and ), creating the excitatory feedback. On the other hand, is copied by the nmos current mirror ( and ), resulting in inhibitory feedback. The is added to the flowing through and is added to the average of all input current by connection transistor to COM node, increasing the value. This way, every cell produces a new voltage value, according to the comparison between current and a new value of current, that is now given by where is the average of all input currents of the array and N is the number of array cells. For the cell, having the highest input current, the difference between and growths, decreasing value. For example, for the same dimensions of and transistors, the value of is equal to. The difference between the input current of the cell and without feedback (during reset phase) can be calculated as (1) (2)

3 FISH et al.: HIGH-SPEED AND HIGH-PRECISION CURRENT WTA CIRCUIT 133 After feedback is applied, the difference is given by (3) because, (3) can be rewritten as (4) Thus, the difference between and is given by Fig. 2. Transient response of WTA circuit. where is the average of excitatory feedback currents of all cells. It can be easily seen, that if cell has the highest input and thus the maximum, then, causing to decrease. A decrease in causes to increase and so on. At the same time, cells, having small inputs have, causing their to be increased. This computation phase is finished when only one cell is identified as a winner, producing 1 at the inverter output. All other cells are identified as losers with 0. As was mentioned above, excitatory feedback provides a hysteretic mechanism that prevents the selection of other potential winners unless they are stronger than the selected one by a set hysteretic current. The value of this hysteretic current can be calculated in the following way: the excitatory and inhibitory feedbacks of the all looser cells are approximately equal to zero. Thus, assuming cell is a winner, the hysteretic current value can be expressed as Note, that in some applications (operating in strong inversion) this hysteresis can be useful, allowing circuit operation without need to reset, while in others, where small currents are input to the circuit, a reset of the circuit is required each time before the competition start. III. PERFORMANCE, SIMULATION AND PRELIMINARY MEASUREMENTS FROM TEST CHIP Two circuits, each designed for a different range of input currents, having eight cells were designed and fabricated in the m, n-well, 4-metal, CMOS technology process supported by MOSIS. To verify the above analysis, the performance of both WTA circuits has been simulated with the SPECTRES Cadence simulator using TSMC m CMOS process parameters. The preliminary measurements from a test chip were performed for the high-input currents. The supply voltage is 3.3 V. (5) (6) TABLE I SIMULATION RESULTS OF FABRICATED CIRCUITS A. Simulation Results Fig. 2 shows an example of the transient responses of voltages for two cells. For this simulation A and A, while have different values, smaller than. Because is greater than, cell is supposed to be the winner and cell 2 the loser. Two phases can be clearly identified in Fig. 2: the reset phase, where excitatory and inhibitory feedbacks are cancelled, and a computation phase, where the winner is found. It can be seen that and are constant during the reset phase. After the feedbacks are applied, rapidly falls, causing cell to be a winner. Note, that the presented voltages are the cell outputs before the inverter, thus the circuit real response time is faster than indicated in Fig. 2. Table I summarizes the main characteristics of the circuit, as were carried out by simulations. Note that mismatch problems between different devices are not taken in account in these simulation results, but can be clearly identified by measurements of a test chip, as shown in the next subsection. Monte Carlo simulations and analysis of the proposed circuit operation with a large number of inputs are subjects for further research. B. Preliminary Measurements From a Test Chip To determine the properties of the fabricated WTA circuit, a specific test board has been designed. This board is designed to provide all control signals for the circuit as well high-precision currents in very wide range. At this stage the board set-up is not finished yet, therefore only preliminary measurements for high input currents results are provided. Generally, there is a good

4 134 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 52, NO. 3, MARCH 2005 TABLE II MAIN CHARACTERISTICS OF FABRICATED CIRCUITS WITH COMPARISON TO EXISTING WTA IMPLEMENTATIONS agreement between the measurement process and the simulation process. Two main sets of measurements where applied on the test chip to determine its properties: 1) typical delay measurements during these measurements the difference between the two highest closest input currents was about 10% (the same conditions as presented in simulation, shown in Fig. 2), and 2) precision measurements and delay measurements in case when the difference between two highest closest input currents is equal to the value of measured precision. Note, that this is the worst case for delay measurements. In order to check the influence of the device mismatch on the circuit performance, the two most far inputs were tested ( and ), while had different values, smaller than and. Following the test chip measurements, the measured mismatch is equivalent to the difference of 10 na in input currents. Table II summarizes the main characteristics of the fabricated circuit, comparing the proposed circuit with existing WTA circuits [5], [18], [32]. IV. CONCLUSION We have presented a high-speed and high-precision CM WTA circuit, described its operation and compared it to the WTA circuits previously published in the literature. A prototype chip with two WTA circuits, each for a different range of input currents, have been implemented in a standard m CMOS process available through MOSIS. The circuit employs inhibitory and local excitatory feedbacks based on input currents average computation. The simulation results and preliminary measurements from a test chip show that the proposed circuit achieves very high speed and high precision and is suitable for a wide range of input currents. Subthreshold matching issues (including Monte Carlo simulations), circuit operation with a large number of inputs are subjects for further research. ACKNOWLEDGMENT The authors wish to thank A. Slepoy for his help with the simulations and layout for this work. REFERENCES [1] J. Lazzaro, S. Ryckebusch, M. A. Mahowald, and C. A. Mead, Winner-Take-All Networks of O(n) Complexity, D. S. Touretzky, Ed. San Mateo, CA: Morgan Kaufmann, 1989, vol. 1, pp [2] A. G. Andreou, K. A. Boahen, A. Pavasovic, P. O. Pouliquen, R. E. Jenkins, and K. Strohbehn, Current-mode subthreshold MOS circuits for analog VLSI neural systems, IEEE Trans. Neural Netw., vol. 2, no. 2, pp , Mar [3] K. A. Boahen, A. G. Andreou, P. O. Pouliquen, and R. E. Jenkins, Current-mode based analog circuits for synthetic neural systems, U.S. Patent , Apr. 27, [4] P. O. Pouliquen, A. G. Andreou, K. Strohbehn, and R. E. Jenkins, An associative memory integrated system for character recognition, in Proc. 36th Midwest Symp. Circuits Systems, Detroit, MI, Aug. 1993, pp [5] J. A. Startzyk and X. Fang, CMOS current-mode winner-take-all circuit with both excitatory and inhibitory feedback, Electron. Lett., vol. 29, no. 10, pp , [6] S. P. DeWeerth and T. G. Morris, CMOS current-mode winner-take-all circuit with distributed hysteresis, Electron. Lett., vol. 31, no. 13, pp , [7] G. Indiveri, A current-mode hysteretic winner-take-all network, with excitatory and inhibitory coupling, Analog Integr. Circuits Signal Process., vol. 28, pp , 2001.

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