The ALICE Upgrade. W. Riegler, ECFA HL-LHC Experiment Workshop, Oct. 3rd, 2016

Transcription

1 The ALICE Upgrade W. Riegler, ECFA HL-LHC Experiment Workshop, Oct. 3rd, 2016

2 ALICE Upgrade Strategy Goal: o High precision measurements of rare probes at low p T, which cannot be selected with a trigger. Target a recorded Pb-Pb luminosity 10 nb -1 8 x events to gain a factor 100 in statistics over the Run1+Run2 programme and o Significant improvement of vertexing and tracking capabilities Detector: o Read out all Pb-Pb interactions at a maximum rate of 50kHz (i.e. L = 6x10 27 cm -1 s -1 ) upon a minimum bias trigger o Perform online data reduction based on reconstruction of clusters and tracks o Improve vertexing and tracking at low p T New Inner Tracking System (ITS) 2

3 L3 Magnet, 0.5T Solenoid ALICE Upgrade Forward Muon Spectrometer, 0.7T Dipole Inner Tracking System (ITS) Time Projection Chamber (TPC) Transition Radiation Detector (TRD) Time Of Flight detector (TOF) Photon Spectrometer (PHOS), EMCAL High Momentum Particle Identification Detector (HMPID) Alice Cosmic Ray Detector (ACORDE) Muon Forward Tracker (MFT) Muon Chambers (MCH) Muon Trigger/Identifier (MTR/MID) Fast Interaction Trigger (FIT) Zero Degree Calorimeter (ZDC) 3

4 The ALICE Upgrade, 5 TDRs Silicon Inner Tracking System (ITS) upgrade Time Projection Chamber (TPC) readout chamber upgrade Muon Forward Tracker (MFT) Upgraded readout for all detectors to cope with the higher rate (SAMPA, CRU) Upgraded Central Trigger Processor Upgraded Fast Interaction Trigger (FIT) based on Quartz+MCP & Scintillator Radiation requirements New Upgraded Online-Offline (O2) system to handle the continuous readout at 50kHz PbPb collisions and reconstruction

5 Inner Tracking System (ITS) Upgrade 5

6 7 Layers of Monolithic Active Pixel Layers Inner Barrel 3 Layers <0.3%X 0 /layer 50um silicon thickness Aluminum Flex 1.7x MeV neq/cm 2 2.7MRad Outer Barrel 4 Layers <1% X 0 /layer 100um Silicon thickness Copper Flex MeV neq/cm 2 100kRad 6

7 ALPIDE Technology and Pixel Layout CMOS Pixel Sensor using TowerJazz 0.18mm CMOS Imaging Process ALICE ITS Upgrade NWELL DIODE NMOS TRANSISTOR PMOS TRANSISTOR SUB PIX_IN SUB IRESET VRESET AVDD PWELL PWELL NWELL DEEP PWELL h e e h h e e Epitaxial Layer P- h Substrate P++ N A ~ N A ~ N A ~ pwell deep pwell A) deep pwell PIX_IN VRESET_D Spacing Diameter deep pwell p substrate nwell deep pwell p + n + p + p + p + p + n + pwell nwell nwell Collection diode Spacing Diameter Spacing B) C) p + p -- p + n + p -- p + p -- epitaxial layer Diode Reset VRESET_D D0 epitaxial layer p substrate Collection Diode SUB High-resistivity (> 1kW cm) p-type epitaxial layer (25mm) on p-type substrate Small n-well diode (2 mm diameter), ~100 times smaller than pixel => low capacitance (~ff) Reverse bias voltage (-6V < V BB < 0V) to substrate (contact from the top) to increase depletion zone around NWELL collection diode Deep PWELL shields NWELL of PMOS transistors (full CMOS circuitry within active area) 7

8 15mm ALPIDE Technology and Pixel Layout 30mm May-2014 palpide-1 - Full-scale prototype: 1024 x sectors with pixels variants - pixel pitch: 28mm x 28mm - 1 register/pixel, no final interface May-2015 Oct-2015 palpide-2 palpide-3-4 sectors with pixels variants - Optimization of circuits blocks - Optimization of circuits blocks allowing integration into ITS modules - NO high-speed output link (1.2 Gbit/sec replaced by a 40Mb/s) - 8 sectors with pixel variants, 3 registers / pixel - All final features, including 1.2 Gbit/s HSO Aug ALPIDE Chip Final Version Main changes wrt palpide-3 Full matrix with same pixel type CLK gating, time skew of global signals Improved protection against SEUs Improvement of PLL HSO 8

9 512 rows zero suppression zero suppression zero suppression zero suppression ALPIDE Final Version 1024 pixel columns AMP COMP THR Architecture continuous or external trigger In-pixel amplification Amplification Discrimination 3-hit storage registers (MEB) Bias, Data Buffering, Interface In-matrix sparsification Key Features High speed serial data output (HSO) OB: 400 Mbit/s Dimensions: 30mm x 15mm IB: 600 Mbit/s or 1.2 Gbit/s Pixel pitch: 29mm x 27mm Ultra-low power (entire chip): < 40mW/cm 2 Global shutter: triggered acquisition (200 khz) or continuous (integration time <10ms) 9

10 More details and test results from the final ALIPIDE chip ALICE ITS, Luciano Musa, Tuesday October 4 th, 17:40 10

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12 Muon Forward Tracker 12

13 Muon Forward Tracker 5+5 forward tracker discs using the ALIPE chip. LHCC in depth review - 19/09/

14 MFT Layout 920 silicon pixel sensors (0.4 m 2 ) in 280 ladders of 2 to 5 sensors each. 1 Introduction Disk#4 Disk#3 Disk#2 Disk#1 10 half-disks 2 detection planes each Disk#0 Radiation doses < 400 krad < 6x MeV n eq /cm 2 10-fold security factor -3.6 < h < z = cm LHCC in depth review - 19/09/2016 z = cm : Layout of the active area of the MFT detector, showing the positioning of the 5% of the ITS surface Twice the ITS inner barrel 14 IP region

15 Fast Interaction Trigger 2 Quartz Cherenkov Detectors with MCPs for MIP resolution <50ps. 1 Fast Scintillator detector for MIP resolution <300ps. LHCC in depth review - 19/09/

16 Time Projection Chamber Upgrade 16

17 Preproduction of GEM foils is ongoing TPC Upgrade

18 Prototype evaluation ongoing, EDRs done, PRR towards end Start of production beg

19 TPC Readout Electronics, SAMPA System overview (1) Continuous sampling of each TPC channel at 5 MHz and - Front-end 3276 ASIC: Front SAMPA End Cards (FEC) on det ect or shipping of data to O2 - Readout: GBT Readout and versatile ASIC: SAMPA link computing facility Front-End Cards (FEC), 550k channels 360 Common Readout Units (CRU) Readout syst em: GBT and versat ile link - Signal processing 360 Common and data Readout reduction Unit s (CRU) off-det ect or Online processing & calibrat ion - calibration and pattern recognition Online processing and calibration on O 2 farm Space charge dist ort ion correct ion Tracking and dat a reduct ion H Appelshäuser ALICE TPC Upgrade LHCC week Sept. 19,

20 SAMPA Chip Common Readout Chip for TPC and Muon Chambers 20

21 SAMPA Chip PASA: Low Noise Shaping Amplifier ADC: 5-10MHz, 10bit low power SAR ADC DSP: Digital Signal Processing i.e. signal shaping, zero suppression Memory, Serial link: High Speed links to Data Acquisition 21

22 SAMPA Chip MPW2 (full functionality) and several test blocks are under evaluation. E.g. noise performance of Shaper Test Block is according to specs. ADC sampled test pulses are read out through the e-links on the full chip. Final chip submission (MPW3) with fixes (if necessary) to be submitted beginning of 2017.

23 Continuous Readout of ALICE Detector Time Frames/Heart Beat Frames HB header Payload (if no hits empty) HB trailer HB header Deleted HBF (no or partial data) HB trailer FLP.. First Level Processor EPN.. Event Processing Node STF.. Sub Time Frame TF.. Time Frame HB.. Heart Beat Trigger HBF.. Heart Beat Frame HB0 HB1 HB2 HB3 HB4 HB5 HB6 HB7 HB8 HB9.. HB255HB0 HB1 HB2 HB3 HB4 HB5 HB6 HB7 HB8 HB9.. HB255 FLPn FLP2 FLP1 FLP0 EPN EPN 23

24 Common Readout Unit (PCI40) Common Readout Unit (common with LHCb) 24

25 ALICE O 2 Requirements 1. LHC min bias Pb-Pb at 50 khz ~100 x more data than during Run 1 2. Physics topics addressed by ALICE upgrade Rare processes Very small signal over background ratio Needs large statistics of reconstructed events Triggering techniques very inefficient if not impossible khz > TPC inherent rate (drift time ~100 µs) Support for continuous read-out (TPC) Detector read-out triggered or continuous New computing system Read-out the data of all interactions Compress these data intelligently by online reconstruction One common online-offline computing system: O 2 Paradigm shift compared to approach for Run 1 and 2 LHCC Review Sep 2016 Pierre Vande Vyvre Unmodified raw data of all interactions shipped from detector to online farm in triggerless continuous mode HI run 3.4 TByte/s Baseline correction and zero suppression Data volume reduction by zero cluster finder. No event discarded. Average compression factor 6.6 Data volume reduction by online tracking. Only reconstructed 90 data GByte/s to data storage. Average compression factor 5.5 Data Storage: 1 year of compressed data Bandwidth: Write 170 GB/s Read 270 GB/s Capacity: 60 PB 20 GByte/s 500 GByte/s 90 GByte/s Tier 0, Tiers 1 and Analysis Facilities Asynchronous (few hours) event reconstruction with final calibration 25

26 O2 Facility Container at experiment site procurement Following the standard CERN procedure Market Survey (MS): questionnaire received from 18 firms out of which 8 were qualified Invitation to Tender (IT) : Supply, Installation and Commissioning of Container Data Centres (CDC) Technical specifications prepared with LHCb and the Neutrino Platform (NP) who have similar needs for the same period. Number of racks units Total Power Footprint Delivery (U) (MVA) (m 2 ) ALICE x 24 Q Q3 19 LHCb x 16 Q3 18 Q1 21 NP x 9 Q1 17 Schedule 09-Sep: Publication of the IT. Publication time: 5 weeks 14-Oct: papers have to be ready for the Finance Committee 14-Dec: CERN Finance Committee LHCC Review Sep 2016 Pierre Vande Vyvre 26

27 O2 Facility Common Data Center in Prevessin An alternative to the CR0 at P2 has been proposed by CERN New common data center in Prevessin regrouping some IT services and possibly the HLT farms of ALICE and LHCb More detailed proposal expected at CERN by mid-october LHCC Review Sep 2016 Pierre Vande Vyvre 27

28 LS2 schedule Dec-Feb (10 weeks) Open Experiment + TPC/ITS/beampipe deinstallation Mar-Dec (40 weeks) TPC upgrade Sep-Dec (15 weeks) Recommissioning Dec-Aug (37 weeks) Reinstall TPC/ITS/MFT/FIT/beampi pe + close Experiment One shift/day Long days foreseen for transport tasks 24h/24 for few specific tasks (e.g. TPC RO tests) LHCC in depth review 28

29 Conclusions ALICE is preparing a major upgrade for LS2. Final prototypes of the subsystems are under test, in view of start of production early