AMIS CMOS Image Sensor IC Preliminary Data Sheet

Transcription

1 1.0 Introduction The AMIS CMOS image sensor has a resolution of 750 x 400 pixels. The AMIS is a high performance CMOS imager optimized for applications requiring a high operating temperature range and high dynamic range as often required in automotive, machine vision, security and surveillance. The high speed on chip ADC permits readout of up to 60 full frames per second. The sensor features the high dynamic LinLog technology permitting a linear or programmable linear logarithmic response for acquisition of high contrast images without image lag or smear. The global shutter technology enables acquisition of fast moving scenes without motion artifacts, unlike in most other CMOS sensors with rolling shutter, all pixels are integrating light at the same moment. Table 1 gives the key features of the AMIS CMOS image sensor IC. Figure 1 shows the spectral response curve of the sensor. Figure 2 shows the orientation of the sensor on a printed circuit board (PCB). 2.0 Key Features Table 1: General Properties of the AMIS Feature Property Pixel number 750 x 400 Pixel size 10.6µm x 10.6µm Active optical area 7.95mm x 4.30mm Recommended-mount lens format 2/3 Full well capacity (saturation) electrons Shutter mode Global shutter Shutter efficiency > 99.5% Min. region of interest (ROI) 1 row x 16 columns Fill factor 35% (diode area only) Quantum sensitivity 7.5µV/electron (calculated) l Sensitivity unity gain Noise free in pixel gain (skimming) x3 small signal gain Programmable on chip gain x1 - x8 in 8 steps I 30C 3.6V 2fA Response Linear and LinLogTM Dynamic range 60dB linear; 120dB with LinLogTM Output swing 10 bit digital Peak quantum efficiency 25% (including fill factor) Spectral range nm peak 550nm Number of outputs 1 Pixel rate 20MHz Maximum frame rate at full frame 60fps Voltage supply 3.3V and 4.2V Power 20MHz 300mW Temperature range ºC 3.0 Ordering Information Marketing Name Ordering Code Tray Ordering Code Wafer Package/extra info. Temperature Range AMIS70700AAA 0C XTD LCC 52 19x19 V -40 C 105 C AMIS70700ABA 0C XDW Bumped + probed -40 C 105 C AMIS70700ADA 0C XDW Unbumped + probed -40 C 105 C 1

2 Figure 1: Spectral Response Curve of the AMIS CMOS Image Sensor Figure 2: Orientation of the AMIS CMOS Image Sensor on the PCB 2

3 4.0 Timing Diagrams To synchronize the data during read out of the frame FVAL (FRAME VALID) signals the read out of a frame and LVAL (LINE VALID) signals the read out of a line. The pixel clock PCLK is continuous. The data change with the rising edge of the pixel clock PCLK and valid data can be grabbed at the falling edge of PCLK. Figure 3 shows the delay between the pixel clock PCLK and the DATA[9:0]. The handshake signal FVAL and LVAL have the same delay to the pixel clock PCLK as the data DATA[9:0]. The read out of a frame starts with the rising edge of the frame valid signal FVAL. After 74 cycles of the pixel clock PCLK the first line starts with rising edge of the line valid signal LVAL. The line pause between two lines is 61 cycles of the pixel clock PCLK. The frame stops with falling edge of FVAL and LVAL which occur at the same time. The number of lines and the number of pixels in a line could be determined by choosing a region of interest (ROI) for the read out of the sensor. Table 2 summarizes the frame rate of the sensor in different applications and resolutions (ROI). Figure 3: Time Delay Between PCLK (blue) and DATA (light blue) Table 2: Frame Rate at Different Regions of Interest (ROI) ROI Width (x-pixels) ROI Height (y-pixels) Total Pixels (megapixels) Max. frame rate (fps) (triggered,10 ms integration) Max. frame rate (fps) (non-triggered, interleaved integration) ,

4 4.1 Free Running Mode The pre-installed free running mode allows images to be acquired without external control signals. The sensor will be read out after the set integration time; then the sensor will be reset. Following this, integration starts again and the readout of the image information begins afresh. The data are output on the rising edge of the pixel clock. The signals FVAL (FRAME VALID) and LVAL (LINE VALID) mask valid image information. The signal SHUTTER in the timing diagram indicates the active integration phase of the sensor. For CameraLink interface implementations the handshake signal DVAL (DATA VALID) must be set to always high, as shown in Figure 4. Figure 4: Timing Diagram Free Running Mode 4.2 Triggered Mode The trigger mode image acquisition begins with the rising edge of an external trigger pulse. The image will be read out after the preset exposure time. After readout, the sensor returns to the reset state and the camera waits for a new trigger pulse. The data are output on the rising edge of the pixel clock. The signals FVAL (FRAME VALID) and LVAL (LINE VALID) mask valid image information. The signal SHUTTER in the timing diagram indicates the active integration phase of the sensor. For CameraLink interface implementations the handshake signal DVAL (DATA VALID) must be set to always high, as shown in Figure 5. 4

5 Figure 5: Timing Diagram Triggered Mode 5.0 Variation of the Sensor Characteristics The AMIS enables the user the possibility to adapt the characteristics of the sensor to the requirements of the application. Figure 6: Response of the Various Camera Modes 5

6 Figure 7: Response of the Various Camera Modes For normal applications that do not require high contrast, the sensor can be operated in linear mode. For applications having short exposure times and low illumination intensity, it is advisable to activate skim mode, in which a non-linear amplification, similar to a gamma correction, is implemented in the pixel so that small signals are amplified significantly more than large signals. In situations involving high intra-scene contrast, compression of the upper gray level region can be achieved with the LinLogTM technology (see Figure 6 and Figure 7). At low intensities, each pixel shows a linear response. At high intensities, the response changes to logarithmic compression. The transition region between linear and logarithmic response can be smoothly adjusted and is strictly monotonic and continuously differentiable. Two examples in the following sections should illustrate the LinLog feature with measurements. 5.1 Example LinLog Mode An example for the simple LinLog response curve (no variation of LinLog value during the integration time) is shown in Figure 8. The integration time was tint = 10 ms. The decimal value in the legend corresponds to the LinLog settings. With the LinLog setting 0 3 the sensor shows a linear response curve. With the settings one enter the logarithmic compression mode not shown in Figure 8. 6

7 Figure 8: Response Curve of the AMIS in Different LinLog Modes 5.2 Example LinLog2 Mode An example for an extended LinLog response curve (variation of LinLog value during the integration time) is given in Figure 9. The integration time was tint = 10ms and the step of the LinLog voltage from the programmed LinLog voltage to 0V occurs at 99% of the integration time. The decimal value in the legend corresponds to the LinLog settings LINLOGV1. The response curves for the different settings of the LinLog voltage show the programmable threshold between linear and logarithmic response. It can be observed that the slope in the logarithmically compressed part of the response is increased compared to the simple LinLog response curve. Figure 9: Response Curve of the AMIS in Different LinLog2 Modes 7

8 6.0 Variation of the Amplification The CMOS sensor can be operated in skim mode, corresponding to a non-linear amplification. In this mode low intensities are amplified more strongly than high intensities (small signal amplification). The resulting response is similar to a gamma correction. The small signal amplification can reach a gain of 3. Figure 10 shows an example of the sensor response curve for different skim voltage. The integration time was tint = 10ms. The decimal value in the legend corresponds to the skim settings. Note: Skim settings 0 2 produce no usable response functions. Figure 10: Response Curve of the AMIS in Skim Mode Beside the nonlinear amplification of the signal in the pixel with the skimming option of the sensor one can use the on chip gain. The gain of the programmable gain amplifier (PGA) is between gain 1 and gain 8 with a resolution of 8 steps. Table 3 summarizes the settings of the PGA. Figure 11 gives an example of the sensor response curve using different gain settings. The integration time was tint = 1ms. The decimal value in the legend corresponds to the gain settings. Table 3: Gain Steps of the PGA PGA code Gain

9 Figure 11: Response Curve of the AMIS for Different Gain Settings 7.0 Change of Parameters and of Resolution The AMIS can operate in different modes, according to the corresponding configuration registers. The serial interface is based on a UART (universal asynchronous receiver transmitter) block plus a shadow register bank. The UART will work at 2baud rates (default baud rate: 9.6kbaud; alternate baud rate: 115.2kbaud). The chip supports the three-wire interface with TX, RX and GND. Handshake is done via software. Table 4 gives an overview about the parameters that can be changed by software. Table 4: Functionality of the AMIS Communication Interface Access Function Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Write Only Write Only Exposure time and trigger delay for shutter All LinLog parameters for LinLog2 mode Programmable gain amplifier x1 x8 Small signal gain with skimming ROI, in x-direction in steps modulo 8, minimum 1 line and 16 pixel Sub sampling Frame request Soft reset 9

10 The user can define a ROI within the sensor to be transmitted to the frame grabber. The smallest ROI for the camera consists of one line of 16 pixels. The ROI is defined via sensor registers. The coordinates of the active area of the chip are (4,4) and (753,407) as shown in Figure 12. Figure 12: Location of the Active Area in the Pixel Matrix The register map of the device is depicted in the following Table 5. Each register is 10 bit wide. Bits marked as RESERVED are not addressable and must not be modified by the customer. 10

11 Table 5: Register Map of the AMIS Address Name Bit map Default Value 00H ITIME Integration time (affected by prescaler, see note 1 and 2) 3E8H 01H LNLGT1 LinLog timing register 1 (affected by prescaler, see note 1 and 2) 384H 02H LNLGT2 LinLog timing register 2 (affected by prescaler, see note 1 and 2) 3DEH 03H PRESCLR Prescaler (see note 2) 014H 04H DLYLSB LSB of delay register (see note 3) 000H 05H DLYMSB MSB of delay register (see note 3) 000H 06H LNLGV2/1 9:8 RESERVED 7:4 LNLGV2 LinLog setting from instant by LNLGT1 to LNLGT2 07AH 3:0 LNLGV1 LinLog setting from start of integration time to LNLGT1 07H SKIM 9:4 RESERVED 3:0 SKIM voltage for pixel gain threshold control 006H 08H AMPLFCTL 9:7 RESERVED 6:4 GAIN 00DH 3:0 OFFSET 09H ROIULFTX ROI upper left corner X coordinate on the monitor 004H 0AH ROIULFTY ROI upper left corner Y coordinate on the monitor 004H 0BH ROILRGHX ROI lower right corner X coordinate on the monitor 2F1H 0CH ROILRGHTY ROI lower right corner Y coordinate on the monitor 193H ODH RESERVED RESERVED 0A9H 0EH BPTHRHLD Threshold for bad and hot pixel function 080H 0FH CONFIG 9:8 General purpose outputs Bit 9 corresponds to GPOUT[1] Bit 8 corresponds to GPOUT[0] 7 Bad/hot pixels (1 function on, 0 off) 6 Transmitter (1 function on, 0 off) 5 Baud rate (1 high speed, 0 low speed) 4 1:2 Y axis Subsampling (1 subsampling active) 040H 3 Skim control (1 skim active) 2 LINLOG control (1 LinLog active) 1 Trigger mode (1 trigger mode, 0 free running) 0 PGA_EN (0 PGA active, 1 PGA off) 10H RESERVED RESERVED 000H 11H RESERVED RESERVED 003H 12H- 1EH RESERVED RESERVED - 1FH SERIFCOMM 9:2 RESERVED 1:0 Additional commands received through the serial interface 00H Null 01H Device reset 02H Frame trigger 000H Notes: 1. Base timing for ITIME, LNLGT1 and LNLGT2 is 1 clock cycle (50 ns) 2. PRESCLR register is used to set number of clock cycles of the LSB of registers in Note 1. In this way, integration time can vary (50ns* PRESCLR*ITIME) from 50ns up to 52ms. The same applies to LNLGT1 and LNLGT2. 3. The delay register (DLYLSB/DLYMSB) is a 20 bit, the same as PRESCLR/ ITIME combined, so they can be used consistently to compensate for changing integration times, in the case that period from trigger to readout needs to be constant. 11

12 8.0 Power Supply and Voltage Reference Decoupling Figure 13 shows the recommended power supply and reference voltage decoupling of the AMIS CMOS image sensor. The analog power supply AVDD and the digital power supply VDD should be well separated, because injection of ripple over AVD into the image sensor decrease the image quality. A good decoupling between AVDD and VDD could be reached with a ferrit bead. The best way to decouple both voltages and to increase the power supply rejection is to use for each voltage a separate linear regulator. Special care is necessary for the decoupling and buffering of HVDD, because during reset of the sensor high currents flow into the sensor. Each pin should be decoupled with a high capacity for buffering and a 100nF ceramic capacity. Figure 13: Power Supply and Voltage Reference Decoupling 12

13 Table 6: External Decoupling Capacitors Capacitor Function Typical Value C1 Power supply decoupling 100µF C3 C6 Power supply decoupling 100nF C2 Power supply decoupling 100µF C7 C10 Power supply decoupling 100nF C16, C17 Power supply decoupling 4.7µF C11, C12 Power supply decoupling 100nF C18 ADC reference voltage decoupling 4.7µF C13 ADC reference voltage decoupling 100nF C19 ADC reference voltage decoupling 4.7µF C14 ADC reference voltage decoupling 100nF C20 ADC reference voltage decoupling 4.7µF C15 ADC reference voltage decoupling 100nF C21 ADC reference voltage decoupling 4.7µF 8.1 Sensor Pin Description Table 7 summaries the pinning of the AMIS CMOS image sensor. Table 7: Pin Description of the AMIS CMOS Image Sensor Name I/O PW Number Pull-up/down of Pins (On chip) Description PCLK Input 1-20MHz pixel clock RESET Input 1 Pull-up Device reset (1) EXSYNC Input 1 Pull-down external frame trigger LFTRGHTN Input 1 Pull-down Left/right indication (2) 0 = Right side 1 = Left side Rx Input 1 - Serial interface receiver TOCTL Input 1 Pull-down Timeout control VRAP Power 1 - ADC reference decoupling VRAN Power 1 - ADC reference decoupling VREF Power 1 - ADC reference decoupling DOUT Output 10 - Data output LVAL Output 1 - Line valid FVAL Output 1 - Frame valid Tx Output 1 - Serial interface transmitter GPOUT Output 2 - General purpose outputs VDD Power 3 - Digital power supply GND Power 3 - Digital ground AVDD Power 5 - Analog power supply HVDD Power 2 - High voltage analog power supply AGND Power 7 - Analog ground Notes: 1. An internal RC filter for noise suppression leads to a worst case delay of 1.1µs. 2. This selection influences the serial communication protocol. 13

14 9.0 Absolute Maximum Ratings Stresses above those listed in Table 8 may cause immediate and permanent device failure. It is not implied that more than one of these conditions can be applied simultaneously. Operation outside the operating ranges for extended periods may affect device reliability. Total cumulative dwell time above the maximum operating rating for power supply or temperature must be less than 100 hours. Table 8: Absolute Maximum Ratings Symbol Description Min. Max. Unit VDD Digital power supply voltage V AVDD Analog power supply voltage V HVDD Control Power supply voltage VIO Voltage on any I/O VDD+0.3 V IIO DC forward BIAS current, input or output -24 (source) + 24 (sink) ma Tj Junction temperature C 10.0 Recommended Operating Conditions Operating ranges define the limits for functional operation and parametric characteristics of the device. The recommended operating conditions are summarized in Table 9. Table 9: Recommended Operating Conditions Symbol Description Min. Typ. Max. Unit VDD Power supply voltage (digital) V AVDD Power supply voltage (analog) V HVDD Control power supply voltage (see note 1) V Tamb Ambient temperature under bias C Tj Junction temperature (see note 4) C Cla Load capacitance on sensor outputs pf VIO Voltage on any I/O VDD/AVDD VDD/AVDD V Pwrc Power consumption mw Notes: 1. HVDD will, in any case, be at least AVDD+ (typical) 0.9 V 2. All pins labeled as the same GND will present 50µV of difference between any pair of them. 3. All pins labeled as the same VDD will present 100µV of difference between any pair of them C is the maximum recommended temperature for parameters of the image sensor. For the rest of the parameters, it is C. The power consumption of the AMIS sensor is listed in Table 10. The power consumption depends on the operation mode of the sensor. During integration time (exposure of the pixels) the power consumption is reduced. The digital outputs of the chip are designed to drive capacitive loads up to CL = 50pF. Under this conditions may have a higher power consumption due to higher output currents. 14

15 Table 10: Power Consumption Max. Power Supply Max. Current Typ. Current / Power Power 48mA during Read Out 160mW AVDD 38mA / 126mW 42mA during Integration and Idle 140mW HVDD 3mA 13.5mW 0.2mA / 0.9mW 29mA@50pF output load 96mW 18mA / 50pF VDD 23mA@20pF output load 76mW 12mA / 20pF 15mA during integration and idle 50mW 11.0 Electrical Characteristics Table 11: Electrical Characteristics of I/Os Symbol Description Min. Max. Unit Vil Low level input voltage 20 %VDD Vih High level input voltage 80 %VDD Vol Low level output voltage (See note 1) 0.4 V Voh High level output voltage (See note 1) 85 %VDD Iil Low level input current (See note 2) +-10 µa Iih High level input current (See note 3) +-10 µa Pullres Pull-up/down resistor (see note 4) KΩ Notes: 1. Values for Iol/Ioh=4mA. 2. Vi=GND 3. Vi=VDD 4. Typical value 50kΩ. 15

16 12.0 Packaging Figure 14 shows the drawing of the CLCC52 packaging of the AMIS CMOS image sensor. Table 12 gives the pinning of the sensor. Figure 15 shows the recommended land pattern for the CLCC52 packaging. Figure 16 shows the cross section of the CLCC52 packaging. Figure 14: Schematic Drawing of the CLCC52 Packaging of the Sensor 16

17 12.1 Pin Description of the AMIS in CLCC52 Package Table 12: Pin Description of the AMIS in CLCC52 Package Pin No. Pin name I/O Type Internal Pull UP/Down 1 DATA<4> Digital Out 2 DATA<5> Digital Out 3 AVDD Analog Power 4 AGND Analog Ground 5 DATA<6> Digital Out 6 DATA<7> Digital Out 7 VDD Digital Power 8 GND Digital Ground 9 DATA<8> Digital Out 10 DATA<9> Digital Out 11 LVAL Digital Out 12 FVAL Digital Out 13 HVDD High Power 14 AGND Analog Ground 15 AVDD Analog Power 16 AGND Analog Ground 17 RX Digital In (pull-up) pull-up 50KΩ 18 TX Digital Out 19 VDD Digital Power 20 GND Digital Ground 21 VDD Digital Power 22 GND Digital Ground 23 GPOUT<0> Digital Out 24 GPOUT<1> Digital Out 25 AVDD Analog Power 26 AGND Analog Ground 27 EXSYNC Digital In (pull-down) Pull-down 50KΩ 28 TOCTL Digital In (pull-down) Pull-down 50KΩ 29 HVDD High Power 30 AGND Analog Ground 31 LEFTRGHTN Digital In (pull-down) Pull-down 50KΩ. 32 RESET Digital In (pull-up) Pull-up 50KΩ 33 AVDD Analog Power 34 AGND Analog Ground 35 NC Do not connect 36 AGND Analog Ground 37 VRAN Analog In 38 VRAP Analog In 39 VREF Analog In 40 AVDD Analog Power 41 AGND Analog Ground 42 GND Digital Ground 43 GND Digital Ground 44 PCLK Digital In 45 VDD Digital Power 46 GND Digital Ground 47 DATA<0> Digital Out 48 DATA<1> Digital Out 49 DATA<2> Digital Out 50 VDD Digital Power (out buffer) 51 GND Digital Ground (out buffer) 52 DATA<3> Digital Out 17

18 Figure 15: Recommended Land Pattern for the CLCC52 Packaging Figure 16: CLCC52 Cross Section 18

19 13.0 Company or Product Inquiries For more information about AMI Semiconductor, our technology and our product, visit our Web site at: North America Tel: Fax: Europe Tel: +32 (0) Fax: +32 (0) Production Technical Data - The information contained in this document applies to a product in production. AMI Semiconductor and its subsidiaries ( AMIS ) have made every effort to ensure that the information is accurate and reliable. However, the characteristics and specifications of the product are subject to change without notice and the information is provided AS IS without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify that data being relied on is the most current and complete. AMIS reserves the right to discontinue production and change specifications and prices at any time and without notice. Products sold by AMIS are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMIS makes no other warranty, express or implied, and disclaims the warranties of noninfringement, merchantability, or fitness for a particular purpose. AMI Semiconductor's products are intended for use in ordinary commercial applications. These products are not designed, authorized, or warranted to be suitable for use in life-support systems or other critical applications where malfunction may cause personal injury. Inclusion of AMIS products in such applications is understood to be fully at the customer s risk. Applications requiring extended temperature range, operation in unusual environmental conditions, or high reliability, such as military or medical life-support, are specifically not recommended without additional processing by AMIS for such applications. Copyright 2005 AMI Semiconductor, Inc. 19