Review of Wafer Dicing Techniques for Via-Middle Process 3DI/TSV Ultrathin Silicon Device Wafers

Transcription

1 Review of Wafer Dicing Techniques for Via-Middle Process 3DI/TSV Ultrathin Silicon Device Wafers Andy Hooper, Jeff Ehorn, Mike Brand, and Cassie Bassett Micron Technology, Inc S. Federal Way, Boise, ID Abstract Dicing of ultrathin (e.g. <75um thick) via-middle 3DI/TSV semiconductor wafers proves to be challenging because the process flow requires the dicing step to occur after wafer thinning and back side processing. This eliminates the possibility of using any type of dice-before-grind techniques. In addition, the presence of back side alignment marks, TSVs, or other features in the dicing street can add challenges for the dicing process. In this presentation, we will review different dicing processes used for 3DI/TSV viamiddle products. Examples showing the optimization process for a 3DI/TSV memory device wafer product are provided. Introduction The dicing of ultrathin semiconductor device wafers with thicknesses <75um can be challenging [1], but this is not due to the wafer thickness alone. The structure of metal and dielectric features in the street can have a large effect on the success or failure of a dicing process. In addition, the use of mechanically fragile low-k and ultra low-k dielectrics in the device structure can present additional issues such as: 1) delamination in the device layers, 2) excessive front side and/or back side chipping, 3) excessive die edge sidewall cracking or chipping, 4) long-term reliability issues related to crack propagation, and 5) weak die that break during die pick. An application requiring ultrathin die are threedimensional integrated circuits (3DI) using vertical connections by through-silicon-vias (TSVs). In this case, ultrathin wafers are required to maintain a reasonable TSV aspect ratio. An example of 3DI technology is Micron's Hybrid Memory Cube (HMC) as shown in Fig. 1. The HMC design employs DRAM stacked atop high-performance logic through TSV connections. Potential benefits of this design include higher processor-to-memory bandwidth and reduced power consumption Figure 1. Image of a Micron's Hybrid Memory Cube 3DI die stack (nine-die stack) with and without the lid. Additional issues arise for dicing 3DI wafer that use the via-middle process. For this case, the wafers must be diced after the wafer thinning and backside processing has been completed. Back side features include alignment marks and flip chip bumps utilizing an under-bump metallization (UBM) pad. The presence of these features can place additional restrictions on the size and degree of back side chipping compared to ultrathin wafers with silicon back sides. All of these factors combine to make ultrathin wafer dicing unpredictable from product to product. Some products may dice easily using a simple through-cut saw process, while other products require more advanced techniques such as laser-based dicing. In the worst cases when no ideal dicing process can be found, it may become necessary to either 1) modify the wafer design to resolve the issue, or 2) to accept a larger-than-normal yield loss due to damage at the dicing step. The goal of this manuscript is to compare and contrast the current commercially available dicing techniques for dicing ultrathin silicon wafers for 3DI/TSV via-middle applications. Because dicing processes are highly dependent on the product and process, the review section will be a broad overview. The processes compared are: 1) wafer saw 2) laser full cut dicing, 3) laser scribe/groove + saw hybrid dicing, 4) Stealth dicing, and 5) plasma dicing. In the 2nd part of the paper a detailed case study showing how to optimize blade and laser-based dicing on a 3DI/TSV product wafer is provided. Materials and Methods Several definitions, abbreviations, and assumptions are used in this manuscript: The front side of a 3DI/TSV wafer is defined as the side with circuitry or "device layers". The back side of the wafer is primarily silicon, but for 3DI/TSV wafers there will also be features such as UBM pads and alignment marks. Front side chipping (FSC) must be contained within the dicing street to not damage to the circuitry. For saws, the blade enters from the front side. Back side chipping (BSC) - as the saw blade exits the back side, the pressure from the advancing blade results in significantly larger BSC compared to FSC. However, the lack of circuitry on the back side can allow typical BSC limits to be larger than FSC. Chipping depth or edge chipping As shown in Fig. 2, both FSC and BSC have a length, width, and depth. If the chipping depth is excessive the die strength can be reduced. Die break strength (DBS) a mechanical test used to measure the force required to break a statistically /15/$ IEEE Electronic Components & Technology Conference

2 significant population of die. Different DBS test methods exist such as 3-point bending [2], 4-point bending, and ball-and-ring. It's common to compare DBS for both the "device side in tension" and the "back side in tension." Percent yield (% yield) There are 2 different types: o "Dicing % yield" is the % of die on a wafer with acceptable chipping. If a single chip on any die exceeds the pre-defined limits for FSC, BSC, or edge chipping then the die is scrapped. o "Die pick % yield" is percentage of die that picked from a wafer without breaking. Throughput - number of wafers processed per hour (WPH). Cost of Ownership (COO) an estimation of direct and indirect costs of a process. It is used to calculate cost per wafer. extensive experience with this technique. It s important to note that the wafer thickness alone isn't necessarily the primary challenge for finding a viable saw process. The dimensions and structure of the features in the dicing street can play a significant role in the final process. For example, devices using low-k dielectrics may have excessive FSC due to the lower mechanical strength of these materials [3]. The features in front side scribe streets also can increase BSC due to blade vibrations caused by entering and exiting metal as opposed to dielectric materials (aka "railroad tracking"). For some products, cracks from the dicing saw can propagate under the crack stop [4]. Two common methods of saw dicing are 1) a one-blade "through-cut" as shown in Fig. 3, and 2) a two-blade "stepcut" as shown in Fig. 4. A through-cut is simply dicing a wafer using a single blade to cut completely through the wafer with each pass. For step-cut, two passes are made to cut through the wafer using two different blade thicknesses as shown in Fig. 4. The first blade cuts through the device layers and into the bulk silicon. The second blade is slightly narrower than the first, and cuts through the remaining silicon on the second pass. Figure 2. Chipping measurement diagram. The following equipment was used to carry out the experiments: Through cut and step cut wafer saw was performed on DISCO DFD600 series Dicing Saws Laser scribing/grooving was performed using a DISCO DFL7000 Laser Saw Die break strength (DBS) was tested on a 3pt bend fixture using a Texture Technologies mechanical tester and load cell at a test speed of 0.5 mm/s Front side chipping (FSC) was measured for every die using a wafer automated inspection tool Back side chipping (BSC) was performed by manual inspection using an Olympus semiconductor inspection microscope. Figure 3. Through cut dicing process All techniques were compared using the same live product type which was a 3DI/TSV semiconductor memory product device. The product was specifically selected because it had a complex design of metal features in the dicing street and presented a real challenge demonstrating dicing process optimization. Review of Dicing Techniques for 3DI/TSV Wafers Several dicing techniques exist for dicing ultrathin wafers using the 3DI/TSV via-middle process: Saw Blade Dicing Saw blade dicing has an advantage because semiconductor manufacturers have an installed base of dicing saw tools and Figure 4. Step cut dicing process 1437

3 A tilted SEM image of typical saw-diced die is shown in Fig. 5. For ultrathin wafers, chipping is minimized by optimizing the blade type, blade RPM, and saw feed rate for different products. In addition, chipping can be affected by other factors. The brand/model of dicing tape used can cause chipping variations. The degree and size of chipping can also vary by the cut axis, for example, the short side of a rectangular die may have more chipping than the long. Finally, chipping can be location-specific. It is possible to see cracking at a particular problematic feature in the dicing street that repeats in the same location across a wafer. Figure 6. SEM images of ZH05-SD2000 series blade: tilt shot showing sidewall of blade (left) and zoom of tip (right) Figure 7. SEM images of ZH05-SD3500 series blade: tilt shot showing sidewall of blade (left) and zoom of tip (right) Figure 5. Tilted SEM image of a saw diced ultrathin die Next, we will discuss the common properties of dicing saw blades. Dicing saw blades can be customized based on a variety of parameters. For example, DISCO ZH05 series Nibonded hub blades are commonly used to cut silicon and III-V semiconductor wafers [5]. First, selecting the blade width depends on the street width of the device and desired kerf width. The blade exposure defines the amount of blade material available to cut. Higher exposures can yield longer blade lifetimes though shorter exposures will be more stable at a higher RPM. Blade mesh indicates the relative size of the diamonds used to construct the blade, with smaller mesh indicating smaller diamond size. Larger diamonds have more cutting power though can exacerbate chipping, while smaller diamonds can provide a cleaner cut. However, if the mesh selected is too fine, the blade may not have sufficient cutting power to dice the wafer [6]. Blade concentration refers to the relative amount of diamonds in the abrasive portion of the blade. For DISCO s ZH05 blades, a concentration of 100 indicates 25% diamond grit by volume [5]. Fig. 6 reveals a SEM image of a ZH05- SD2000 series blade which has a lower quantity of relatively larger diamonds. Contrast that with Fig. 7 showing a SEM image of a ZH05-SD3500 series blade which has a higher quantity of relatively smaller diamonds. Stealth Dicing Stealth dicing is a laser-based dicing technique that uses a high powered laser to disrupt the crystalline lattice of the silicon substrate which is then singulated by expanding (stretching) the dicing tape [7]. The laser wavelength selected is normally transparent to silicon except at the high-intensity focal point. Because laser-silicon interactions only occur at the focal point, the position where the crystalline lattice is disrupted (called the Stealth Dicing Layer or SD-Layer) can be carefully controlled by laser beam positioning. For ultrathin wafers, one pass of the laser down the dicing streets is required. Thicker wafers may require multiple passes at different depths for singulation. The key benefits of this technique are that it has zero kerf width, produces no debris, and ideally has no front and back side chipping. The lack of chipping can also result in higher DBS. For ultrathin via-middle 3DI/TSV wafers, the wafer must be stealth diced after the thinning and back side processing has been performed. This potentially creates a problem because any features in the back side street can block or interfere with the laser energy transmission. Ways to address this problem include: Exclusion Zone Method: If the dicing street is not free of metal then a metal-free exclusion zone can be designed into the device as shown in Fig. 8. Wafer Flipping Method: The wafer can be processed from the back side where there are typically no metal features in the dicing streets. This can be achieved by flipping the wafer over and remounting on a dicing tape frame. Images of a Memory Device A wafer processed using the wafer flipping process is shown in Fig. 9 showing the morphology of the SD-layer and effectively zero front and back side chipping. 1438

4 Through-Tape Process: Hamamatsu Photonics website reports that back side Stealth dicing through from the dicing tape is possible with a special transparent tape. After the laser portion of the Stealth Dicing has been completed tape expansion is required to singulate the die. This step must also cleave apart the front side metal and dielectric layers and singulate any Die Attach Film (DAF) present (if used). Tape expansion also provides separation distance between die to facilitate die pick Laser Full Cut Wafer Dicing Laser full cut wafer dicing involves cutting through the wafer using only a high power laser via a process called "ablation" [8]. An example is shown in Fig. 10. Usually, the dicing recipe employs a two-step process. For the first pass, the laser parameters are optimized for scribing through the device layers and slightly into the underlying silicon wafer [9]. This first step is usually necessary to reduce chipping & delamination, or to maximize front side in tension DBS. Next, the laser parameters can be changed to a "silicon cutting" recipe to dice the rest of the way through the wafer. This can require numerous passes of the laser depending on the wafer thickness or recipe parameters. In situations when the wafer is mounted on DAF, a third set of laser parameters may be required to cut through the DAF after the silicon has been cut through. Figure 8. Stealth dicing process Figure 10. Full cut laser dicing Figure 9. Microscope and tilt-sem image of a die processed by Stealth dicing process: a. back side of die, b. front side of die, and c. SEM image along die sidewall. The primary benefit of this technique is that the laser is able to "saw" through any typical semiconductor material such as metals, dielectrics, and DAF without applying mechanical stress to the wafer. And, the FSC and BSC ideally should be insignificant compared to saw dicing. Unfortunately, full cut laser dicing comes with some major drawbacks. First, a significant amount of debris is generated from the process and a spin-on protective coating must be applied to the wafer before dicing. This requirement adds an additional process step and cost to the process. Second, the laser creates an undesirable heat affected zone (HAZ) along the sides and edges of the die. The HAZ is composed of a layer of melted, reflowed, and recystallized silicon [10]. For processes that use high power + low feed rates, a thick HAZ is accompanied by a ridge of material forming along the top edge of the kerf. A FIB/SEM cross section of this effect is shown in Fig

5 Figure 12. SEM images of the edge of a full cut laser diced die a. before and b. after XeF 2 etch. Figure 11. FIB/SEM image of the HAZ edge of a wafer diced using the full cut laser dicing process The HAZ generate by full cut laser dicing is problematic, and some interesting strategies have been published in an effort to address this specific issue: Post Dicing Plasma Etch. In 2007, Samsung published a paper that explored using RF plasma with CF 4 and O 2 etching gasses to remove the heat affected zone post laser full cut dicing [11]. While they did observe removal of the HAZ and an increase in DBS, the circuitry side of the die was visibly damaged by the ion bombardment because a mask layer was not used. Post Dicing Wet Chemical Etch by KOH. The same group at Samsung [11] also explored wet etching laser full cut dies in a 20 wt% / 80 C KOH solution for times up to 40 minutes. As etch time increase the observed the die sidewalls becoming smoother and a significant increase in DBS. They did not comment if there was any observable damage to the circuitry. Post Dicing XeF 2 non-plasma post Etch XeF 2 gas has been used to isotropically react with and remove the HAZ from the sidewalls of full cut laser diced wafers [12]. Because the XeF 2 preferentially etches silicon over metal/dielectrics, no mask is required. Fig. 12 shows sidewall images of a product die before and after XeF 2 exposure. For this case, the die circuitry/device layers were undamaged by the XeF 2 exposure, and the die sidewalls changed from a melted surface into a reticulated surface. Laser Scribing (Grooving) Laser scribing + saw hybrid processing (also called laser grooving) is a compromise between saw dicing and full cut laser dicing. For this process, the laser is used to scribe only through the device layers on the front side of the wafer. Then, the saw is used to cut through the silicon substrate. This combination allows FSC to be minimize (especially for devices with low-k dielectrics) while greatly reducing the HAZ produced by full cut laser dicing. One strategy is shown in Fig. 13. For this method, the device layers in the street are cut through using 2 grooves on both sides of the dicing street followed by saw blade dicing. For this strategy, the grooves serve to mechanically isolate or "disconnect" the street from the rest of the device, and ideally prevent crack propagation. A second strategy is shown in Fig. 14. First, two grooves are cut to define the edges of the kerf. Next, the laser is used to completely ablate of all features in the middle of the dicing street in the region where the saw will pass. Since metal/dielectric features in the dicing street can cause blade agitation, removing them can reduce BSC. A SEM image of a die cut using Broad Scribing is shown in Fig. 15. One drawback of this technique is that this process still requires that a protective coating be applied to the wafer before dicing to capture debris generated from the laser scribing. This adds an additional process step and costs to the process. Figure 13. Hybrid laser grooving + saw process 1440

6 Figure 16. Example of plasma diced wafer complements of Panasonic Factory Solutions Co. Ltd. Figure 14. Hybrid "broad scribing" + saw process Figure 17. Example of plasma dicing process Figure 15. Tilted SEM image of a die processed using the laser + saw dicing process shown in Fig. 14 Plasma Dicing Plasma dicing involves dry etching the wafer using deep reactive ion etch (DRIE). This technique ideally generates no mechanical stress to the wafer during dicing, generates no debris, yields zero FSC & BSC, and creates stress-free die sidewalls yielding a potentially higher DBS [13]. An image of a plasma dice wafer is shown in Fig. 16. A diagram of plasma dicing is shown in Fig. 17. There are two primary considerations for plasma dicing. First, a mask layer is required to protect the active circuitry from damage by the plasma and/or ion bombardment. For the case of via-middle wafers, because plasma dice before grind is not viable, a custom-build mask application module would be required that could handle ultrathin wafers on dicing tape frames. Second, the standard DRIE process that is employed to etch silicon is ineffective for etching metals. Hence, a nonmetal exclusion zone must be included in the dicing street to facilitate plasma dicing. Alternatively, for a case without a dicing street exclusion zone, the wafer could conceivably be flipped and plasma diced from the back side but a method to singulate the metal device layers would still be required. Finally, since plasma dicing requires exposure to vacuum, the dicing tape cannot contain air bubbles or be susceptible to damage from vacuum exposure. 1441

7 Table 1. Dicing Methods (Benefits and Drawbacks). Dicing Method Benefits Drawbacks Saw Dicing Tooling is relatively low cost. Mechanical stresses are applied to wafer. Leverages installed tool base. Die can fly off of tape during dicing. Well known process. Debris (saw sludge) is Low tool footprint. generated that must be Tool is much less washed off, FSC and BSC complex compared to is significantly larger laser-based dicing compared to laser/plasma leading to shorter dicing techniques. training times for tool operators. Blade costs can be expensive. Dicing kerf width is limited by street width. Stealth Dicing Full Cut Laser Dicing Laser Scribing + Saw Dicing Plasma dicing Zero kerf width which can in turn lead to a reduction in street width and increase in DPW. No FSC or BSC. Significantly higher DBS. No debris generated & no post-dicing cleaning required WPH increases as product wafers become thinner. Smaller kerf width compared to saw, no significant FSC or BSC. Ablation process has no material limitations. It can reduce or eliminate FSC compared to saw. Increased DBS due to reduced FSC compared to saw. Removing metal features in dicing street may allow saw higher feed rates resulting in higher throughput for laser + saw compared to saw only. Eliminates FSC and BSC. No mechanical stresses applied to wafer. DBS may be increased by plasma etch "stress removal". It can use endpoint detection. It can increase die per wafer from reducing street width. It does not cut metal or dielectrics and device layers are cleaved using tape expansion. Tooling is expensive and requires tape expansion tool or module. Less effective for device wafers where street is not aligned with crystalline axis. Tooling is expensive. Laser maintenance is expensive. DBS is low due to HAZ It is not viable for thicker wafers. HAZ etch/removal process adds additional process steps and cost. It is dependent on layout and structure of features in the dicing street. Process requires protective coating and post laser cleaning to remove debris which can be expensive. Wafers are fragile being transported after laser scribing to the dicing saw and can be damaged. It requires a silicon exclusion zone in the dicing street or processing from back side of wafer. Tool is relatively expensive requiring high throughput to meet COO. System has a large footprint, requires exhaust abatement, and requires etch gasses that typically are not found on an assembly and packaging floor. Exposed circuitry layers require mask to protect from damage [11]. Throughput for thicker wafers is slower compared to thin wafers. Discussion of Dicing Optimization Process When new semiconductor products arrive at the wafer dicing step, process optimization is often necessary. This process begins by using practice wafers that are mechanically identical to live wafers, but lack electronic functionality. Initially, the wafers are diced by trying a recipe from a similar product type. Fig. 18 shows an example of a failed first attempt on a practice product wafer. Excessive and sporadic BSC with edge chipping that initiated near the front side of the die was observed as shown in Fig. 18a. In addition, front side cross sections of the die in proximity to these large back side chips revealed catastrophic hairline cracks that propagated into the device layers as shown in Fig. 18b. We will now discuss the process employed to optimize the dicing process for this device for both saw and laser + saw dicing methods. Figure 18. Cross section of a semiconductor die that was diced using an unoptimized step-cut process. a. excessive BSC with edge chipping initiating near the front side of the wafer, and b. hairline crack propagation into device layers Mechanical Dicing Optimization As discussed previously the three major defect types pertaining to mechanical dicing are FSC, edge chipping, and BSC. The issue facing the product TSV wafers was a qualification failure linked to back side chipping so large they were breaking through to the circuitry side as shown in Fig. 18. Fig. 19 shows this chipping from the perspective looking along the die sidewall for product by the microscope inspection method shown in Fig. 20. Figure 19. Sidewall view of product die with back side chipping at 10x magnification circuitry is on the top side. 1442

8 Results from the DOE showed that for the response of back side chipping the most significant factor by far was the Z1 mesh using an alpha value of Other factors that were borderline significant just above the selected value of alpha included the Z2 Spindle RPM and Z2 mesh. See sidewall image of best initial result below in Fig. 21. Figure 20. Microscope inspection of die for sidewall cracking and back side chipping The originally developed dicing process was a step cut. The Z1 blade was a DISCO ZH05-SD3500 series blade, and the Z2 was a DISCO ZH05-SD4000 series blade. Z1/Z2 RPMs were set at 45,000/25,000 and the wafer feed speed was 15mm/sec. Dicing was performed on DISCO 6300 series dicing saws. This process had worked successfully on non- TSV products previously but was shown to have poor results when applied to the Memory Device A practice wafers. A screening DOE was initiated to study the primary factors that may influence cut quality. These included the synthetic diamond size (mesh), relative diamond quantity (concentration), and Z2 blade speed. Factors held constant in DOE #1 were the wafer type, wafer thickness, dicing tape, Z1/Z2 blade width and exposure, specific dicing saw, and Z1 blade speed. It was postulated that because the defect mode was back side chipping that changes in the Z2 finishing blade speed would have a more significant impact than Z1. A DOE was generated which tested high/low conditions for the aforementioned factors. For the blade mesh, for example, DISCO ZH05 blades area available ranging from 1500 to 5000, with 1500 being the most coarse/largest diamond size and 5000 being the smallest. In this initial study for Z1 mesh the low end was set to be 1700 and the high end at 3000 based on blades available at the time of the experiment. Z2 mesh ranged from Z1 concentration from , Z2 concentration from 50-90, and Z2 Blade RPM from 20,000-45,000. Sixteen wafers that were available for experimentation were diced using eight treatment combinations with two replicates per condition. Twelve die per wafer from the four were picked and inspected on an Olympus microscope at 20x magnification (see Fig. 20). The die were checked for any sidewall cracks as well as back side chipping along the entire length of both one short and one long axis of each die. If the dimensions of a single crack on the die exceeded a pre-defined limit, it was considered a reject. These die counts were totaled for both short/long axes and averaged to form an overall % failure number for each treatment combination. The data was put back into JMP and a model fit to determine the significance of each factor. The baseline DC/BB step cut process showed an average failure rate for back side chipping of around 40-50% of die inspected. Figure 21. Sidewall view of product die on best optimized dicing condition at 20x magnification circuitry is on the top side. Based on the initial result it was desired to then extend the range of the factors further to test Z1 mesh, Z2 mesh, and Z2 Spindle RPM both at higher levels. Additional blades were procured to test Z1 mesh at 3000/3500/4000, Z2 mesh at 4000/4500/5000, and Z2 spindle RPM at 45k/50k/55k/60k. Step-wise experiments were run testing each factor individually and then inspecting 12 die per wafer using the same method described earlier. The first test involved using three different combinations of Z1/Z2 mesh as follows: 3000/4000, 3500/4500, and 4000/5000. Two baseline wafers diced showed 52% failure rates for back side chipping. Four wafers were diced per experimental condition and the results averaged. These three conditions produced failure rates of 26%, 6%, and 11% respectively. Although qualitatively the edge of the wafer on the back side appeared to be rougher with successively higher mesh, none of the chipping recorded was outside of internal specs. Thus it was concluded that the 3500/4500 mesh combination was the most optimized. See sidewall examples below in Fig. 22, 23, and 24. Lastly it was desired to further explore higher Z2 blade RPM set points above 45,000 for any potential gain. As previously noted the 45,000 Z2 RPM set point appeared to be best and as a result 50k/55k/60k were explored. The maximum safe limit of the blade used was 60,000 RPMs. Two wafers per experimental condition were diced and compared to baseline conditions. BSC was inspected addition to measuring the average and maximum back side chip width. See Fig. 2 above for measurement diagram. Results showed that the three conditions explored were not significantly different for BSC depth or BSC width measurements compared to the 45,000 set point. Figure 22. Back side of product die diced using Z1/Z2 3000/4000 mesh combination blades. 1443

9 Figure 23. Back side of product die diced using Z1/Z2 3500/4500 mesh combination blades. Figure 24. Back side of product die diced using Z1/Z2 4000/5000 mesh combination blades. Hybrid Laser Scribe/Groove + Saw Dicing Optimization For laser scribing of semiconductor device layers, there are 3 unique regimes that should be explored to find an optimized process [10]. For this manuscript we will define these regimes by the laser "bite size" and "laser spot overlap" as shown in Fig. 25. The three are summarized as follows: 1) the "zero overlap" regime where the bite size is larger than the spot size, 2) the "partially overlap" region that includes the region from ~30% to ~70% overlap, and 3) the highly overlapping region. An optimized process may be found in any of these regions depending on the layout and structure of features in the dicing street. Creating recipes for these 3 regimes is achieved by calculating the required laser rep rate & feed rate to achieve the needed bite size and spot-overlap combinations for each regime. Next, wafer scribing is performed for each regime with a series of different laser powers. These "power runs" are then inspected by microscope or SEM to determine the minimum power required to cut through the device layers into the silicon substrate. Once the minimum power is determined, the dicing engineer can select a higher power to provide an acceptable process window for the normal process variations that occur from wafer to wafer. For the case of the initial product, a small bite-size and highly overlapping laser process was initially selected with an 80% spot overlap and 2 um bite size using the process shown in Fig. 14. Although this process achieved good FSC and BSC results, 30% of die broke during die pick. Subsequent DBS measurements revealed that the mean device side in tension DBS (i.e., the side under tension during die pick) had decreased by ~60% compared to the optimized saw process. For the next step, a 50% overlap process was investigated. In order to reach the 50% overlap using a reasonable laser rep rate, the feed rates required were over 200 mm/s. At these velocities, street feature-related chipping and delamination was observed as shown in Fig. 26 on the product. It is possible that a process could have been found by dropping the power and doing multiple passes, but a multi-pass process was deemed too slow to meet throughput requirements. Hence, the 50% overlap process was deemed not viable for the product. Figure 25. Defining Bite Size and %Overlap. Figure 26. Laser Grooves compare at different feed rates with the power normalized to 50 J/cm 2. Gross chipping at critical features was observed to increase with feed rate. Next, a zero-overlap scribing process was investigated. Fig. 27 shows a microscope image of the dicing street after the zero-overlap process but before saw. The scalloped shape from the single pulses is clearly visible along the kerf edges. Unfortunately, the single pulses were ineffective at removing the larger metal features in the dicing street. Using higher laser power to remove the metal was successful, however, the laser pulses drilled deeply into areas without metal features creating via-like structures in those areas. Although the zero-overlap process was not effective for metal feature removal, the DBS results for this process was approximately two times stronger than the highly-overlapping first attempt process. This led to two conclusions: 1) the smaller HAZ provided by the zero overlap increased the DBS, and 2) the 50% overlap process revealed that higher feed rates can cause street feature-specific chipping and delamination for this product. This suggested that the ideal process would be found at 1) lower powers and 2) lower feed rates. After performing some comparison experiments at different laser 1444

10 powers and feed rates (at fixed rep rate) a 90% overlap process with a ~1um bite size was qualified. This was achieved by dropping both the laser power and the feed rate by 80%. A tilted SEM image of the final, optimized process is shown in Fig. 28. The DBS results are shown in Fig. 28 and they are comparable to the saw process. Figure 29. DBS results for the laser and saw processes. Figure 27. Microscope image of dicing street using zerooverlap dicing process after laser processing but before saw. Incomplete removal of street metal features was observed. Figure 28. Tilt SEM image of a die diced using the optimized Hybrid Laser Groove + Saw Dicing process Discussion The summary of front side in tension DBS data is shown in Fig. 29 (the back side in tension DBS results were high for all processes and are not presented). For the initial first attempt laser grooving process using a known good recipe for a similar product, it was observed that 30% of the die broke during pick. The resulting device side in tension DBS had reduced by 60% compared to the saw step cut process. After performing recipe optimization, the die pick yield increased to >99% and the device side in tension DBS was increased by ~2x. An optimized process for the product was also developed for Stealth dicing for comparison. This was performed by using the wafer flipping and backside process. The DBS results are included in Fig. 29. The stealth diced die had an insignificant amount of chipping as shown in Fig. 9, and this is reflected in the DBS. The Stealth process had the highest front side in tension DBS compared to both the saw or laser + saw processes. Weibull analysis was performed on the data sets for the optimized saw process compared to both the unoptimized and optimized laser + saw process as shown in Fig. 30 and Table 2. Details about how to perform and interpret Weibull analysis for DBS can be found here [14]. Weibull analysis is useful for small data sets and provides a graphical method to compare results. The horizontal scale is a measure of life or aging parameter. The vertical scale is the cumulative percentage failed. If the points show a linear fit as observed in Fig. 30, it indicates that the Weibull distribution model is a good choice from a statistical point of view. The slope, β, indicates which class of failures is present (aka the bathtub curve ): β < 1.0 indicates infant mortality followed by a failure rate that decreases with time. β = 1.0 means random failure rate is independent of time β > 1.0 indicates wear out failures, or the rate of failures increases with time. The parameter represents the characteristic life which is defined as the point where 63.2% cumulative failures have occurred. Figure 30. Weibull analysis of saw and laser + saw dicing processes. The color bands indicate 95% confidence. 1445

11 Table 2. Weibull analysis of selected DBS data. Alpha parameters were normalized to the saw step cut. By comparing the graphs in Fig. 30 and the and β parameters for the three processes in Table 2, we can gain insights about these processes. Because the optimized laser and optimized step cut fit lines intersect it reveals that the DBS for these two processes are not significantly different. Next, the parameters indicate that the optimized laser scribe process has the longest characteristic life, followed by the saw process. Next, the difference in the slopes between the three plots indicates that each process has different flaw populations. Specifically, the optimized laser scribe process results in a larger flaw population than the step cut process. Conclusion This report summarizes a wide range of dicing techniques that are suitable for 3DI/TSV wafers using via-middle process. Step-by-step procedures were provided for how the saw and laser + saw processes are optimized for these types of wafers. The final optimized processes had significantly reduced FSC and BSC and significantly higher DBS compared to baseline processes. Acknowledgement We would like to thank Panasonic Factory Solutions Co. Ltd. for supplying a plasma dicing Fig. 16. References 1. W-S. Lei, A. Kumar, and R. Yalamanchili, Die singulation technologies for advanced packaging: A critical review, J. Vac. Sci. Technol. B, vol. 30, no. 4, pp , Jul/Aug SEMI Standard G , 2003, Test Method for Measurement of Chip (Die) Strength by Mean of 3-Point Bending, Z.J. Wang, S. Wang, J.H. Wang, S. Lee, Y. S.Ying, R. Han, and Y.Q. Su, 300mm Low K Wafer Dicing Saw Study, in Proc. IEEE th International Conference on Electronic Packaging Technology (ICEPT), Shenzhen, China, Aug. 32 Sep 2, 2005, pp D. C. Edelstein, Integration/Reliability Issues for Cu/lowk BEOL Interconnects, in Proc. International Interconnect Technology Conference (IEEE), Burlingame, CA, Jun. 4-6, DISCO Corporation, Electroformed Bond Hub Blades ZH05 Series, "Advanced Hub blade for Improved process stability and consistency, 6. UKAM Industrial Superhard Tools, "Selecting the Right Diamond Dicing Blade for your Application," 7. M. Kumagai, N. Uchiyama, E. Ohmura, R. Sugiura, K. Atsumi, and K. Fukumitsu, Advanced dicing technology for semiconductor wafer Stealth dicing, in Proc. IEEE International Symposium on Semiconductor Manufacturing (ISSM),Tokyo, Japan, Sept , 2006, pp D-H. Kim, Y-J. Kim, K-S. Seong, J-K. Song, B-C Kim, C- H. Hwang, and C-H. Lee, Evaluation for UV Laser Dicing Process and its Reliability for Various Designs of Stack Chip Scale Package, in Proc. Electronic Components and Technology Conference (ECTC), San Diego, CA, May 26-29, 2009, pp A. Hooper, D. Barsic, H. Zhang, and J. O Brien, Laser scribing of copper/low-k dielectric semiconductor materials by nanosecond and ultrafast pulsewidth lasers, in Proc. 42nd International Symposium on Microelectronics ( IMAPS), San Jose, CA, Nov. 1-5, A. Hooper and D. Finn, Analysis of Silicon Micromachining by UV Lasers, and Implications for Full Cut Laser Dicing of Ultra-Thin Semiconductor Device Wafers, in Proc. 6th International Conference and Exhibition on Device Packaging (IMAPS), Scottsdale, AZ, Mar. 9-11, J. Li, H. Hwang, E-C. Ahn, Q. Chen, P. Kim, T. Lee, M. Chung, T. Chung, Laser Dicing and Subsequent Die Strength Enhancement Technologies for Ultra-thin Wafer, in Proc. IEEE Electronic Components and Technology Conference (ECTC), Reno, NV, May 29 June 1, 2007, pp A. Hooper, D. Finn, S. Noel, G. Anderson, J. O Brien, and C-C. Lin, Laser technology for TSV and microvia drilling in silicon for 3D packaging applications, in Proc. 7th International Conference and Exhibition on Device Packaging (IMAPS), Scottsdale, AZ, Mar , N. Matsubara, R. Windemuth, H. Mitsuru, and H. Atsushi, Plasma dicing technology, in Proc. Electronic System- Integration Technology Conference (ESTC), Sept , 2012, pp S. Schoenfelder, M. Ebert, C. Landesberger, K. Bock, and J. Bagdahn, Investigations of the influence of dicing techniques on the strength properties of thin silicon, Microelectronics Reliability, vol.47, no. 2 3, pp , Feb. Mar