SAMPLE REPACKAGING FOR BACKSIDE ANALYSIS

Transcription

1 SAMPLE REPACKAGING FOR BACKSIDE ANALYSIS CHAUDAT Willy, CNES /UPS CHAZAL Vanessa, Thales-CNES LAUVERJAT Dorine, Hirex Engineering FORGERIT Bertrand, Hirex Engineering 1

2 OUTLINE Context Process description Process control Conclusion & perspectives 2

3 CONTEXT One key for the success of Backside defect localization is the quality of the sample preparation. The sample to sample reproducibility requires a minimum optionality of the preparation process. The key parameters to be under control are : - Backside flatness - Warp control - Low stress, low damage - Perfect polished surface - Electrical integrity - Perfect polished surface of the initial ball and wedges to be re-bonded The CNES DCT/AQ/LE lab initiates a project for die repackaging using a new concept based on a universal PCB package adapted to their electrical bench interface. Hirex Engineering technology analysis laboratory historically provides many services around FA, DPA, CA and std/custom sample preparation for radiation test. Repackaging activity for backside analysis is now a new item in our business portfolio and roadmap. 3

4 PROCESS DESCRIPTION 1-Die extraction Ceramic package Side brazed package Dice in cavity Plastic package Molded dice New package (3D,TVS,SoC ) Die extraction to be adpated 4

5 1-Die extraction Die in cavity PROCESS DESCRIPTION a- Open the package b- Fill the cavity with epoxy resin c- Cut the Die/Resin/Package cube d- Front side & backside polishing e- Extract chemically the die 5

6 1-Die extraction Molded Die PROCESS DESCRIPTION a- Front side polishing b- Backside polishing c- Cut the package cube 6

7 PROCESS DESCRIPTION 2- Tool kit Metal bloc substrate Repackaging PCB Conductive Silicon Metal screen plate - Cavity for molding Plate Ni Au shorts all pins during - Good thermal diffusion the porcess for the bonding process - Compatible with the wire bonder table 7

8 PROCESS DESCRIPTION 3-Bonding diagram scrambling Pin options : I/O : Connected to tester VCC : Power supply 1 GND : Ground VDD : Power supply 2 NC : Not connected to tester Jumper identification : 8

9 PROCESS DESCRIPTION 4-Die repackaging Molded die a-bond the chip/plastic on the substrate b-position the PCB c-position the conductive silicone plate d-position the screen e-perform the wire bonding operation f-fill the cavity with epoxy resin/low stress plastic g-extract the mounted sample for final polishing PCB Die 9

10 PROCESS CONTROL 5-Key parameters Die extraction Die surface protection Flatness control during process Top/bottom surface referential monitoring Repackaging and rebonding Top/bottom surface referential monitoring Good Mechanical stability Good Thermal transfer Good ultrasonic transfer Residual bonding cleanness ESD protection Stay in the Bonder tool capabilities Die to PCB level step Wire length / loop limitation Bonding termination option choice BBS/BBOS/BSOB for multichip project. 10

11 Conclusion CONCLUSION & PERSPECTIVES Today, we are able to perform repackaging/rebonding operation with good results and stable process. What s next? Design a specific holder for our polishing tool. Integrate SMD parts on the Repackage PCB. Molding resin improvement for large and thin dice. Development of die extraction process on new assembly. Development of assembly process with Copper material. Upgrade the wire bonder tool in order to fit with aggressive pitch trend (<50µm ball bond diameter). 11

12 THANK YOU 12