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1 Is Now Part of To learn more about ON Semiconductor, please visit our website at ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor s product/patent coverage may be accessed at ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. Typical parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

2 Application Note AN4009 (ML AN33) ML484 Combo Controller Applications eneral Description This Application Note shows the step-by-step process to design a high performance supply. The equations shown in this document can also be used for different output voltages and total power. The complete power supply circuit shown in Figure 6 demonstrates the ML484 s ability to manage high output power while easily complying with international requirements regarding AC line quality. The PFC section provides 380V DC to a dual transistor current-mode forward converter. The output of the converter delivers V at up to 6 amps. The circuit operates from 80 to 64V AC with both power sections switching at 00kHz. The PFC Stage Powering the ML484 The ML484 is initialized once C 30 is charged to 3V through R 7 and R 30. PFC switching action now boosts the voltage on C 5 to 380V via T s primary inductance. T then supplies a well regulated 3V for the ML484 from its secondary winding and full wave rectifier consisting of D 3, D 4, C 0 and C. T s primary to secondary turns ratio (N PRI / N SEC ) is 5.5:. For proper circuit operation, high frequency bypassing with low ESR ceramic or film capacitors on V CC and V REF is provided. Orderly PFC operation upon start-up is guaranteed when D quick charges the boost capacitor to the peak AC line voltage before the boost switch AC INPUT 80 TO 64V D C R7 D Z3 Z T R7 Z4 Z R R D4 D3 C R30 R Q C4 C5 R8 C0 C R9 R3 R5 R4 C C3 R ML484 VEAO 6 VFB 5 REF4 VCC 3 VO VO ND 0 ILIM 9 IEAO IAC ISENSE VRMS SS VDC RAMP RAMP D9 R0 C3 C4 C5 C30 C9 CT D8 D0 R C9 Figure. The PFC Stage REV..0.3 /5/0

3 AN4009 APPLICATION NOTE Q is turned on. This ensures the boost inductor current is zero before PFC action begins. The value of the regulated voltage on C 5 must always be greater than the peak value of the maximum line voltage delivered to the supply. VC5 > VRMS( MAX) VC5 > (. 44 )( 64) VC5 > 373 V use 380 V Because the ML484 uses transconductance amplifiers the loop compensation networks are returned to ground (see the ML484 data sheet for the error amplifier characteristics/ advantages). This eliminates the interaction of the resistive divider network with the loop compensation capacitors permitting a wide choice of divider values chosen only to minimize amplifier offset voltages due to input bias currents. For reliable operation R 7 must have a voltage rating of at least 400 volts. Calculate the resistor divider ratio R 7 /R 8. R7 R8 R7 R8 R7 R8 V C Selecting the Power Components The ML484 PFC section operates with continuous inductor current to minimize peak currents and maximize the available power. The inductance value required for continuous current operation in the typical application is found in equation VRMS( MAX) T ( PRI) ( FC)( POUT) T ( PRI) (. )( ) ( 05)( 00) T ( PRI) 55. mh use 5. mh The boost diode D and switch Q are chosen with a reverse voltage rating of 500V to safely withstand the 380V boost potential. The average and peak currents respectively through these components are: () () (3) The boost capacitor value is chosen to permit a given output voltage hold-up time in the event the line voltage is suddenly removed. t HLD hold-up time (sec) V C5(MIN) IAV IAV πp OUT VRMS( MIN) IAV ( )( 00 ) ( )(. 44 )( 80) IPEAK 78. A πiav IPEAK ( )(. 78) IPEAK 437. A ( P t C OUT)( HLD) 5 VC 5( NOM ) VC 5( MIN) minimum voltage on C 5 at which the PWM stage can still deliver full output power A key advantage of using leading/trailing edge modulation is that a large portion of the inductor current is dumped directly into the load (PWM stage transformer) and not the boost capacitor. This relaxes the ESR requirement of the boost capacitor. For reference, equation 7 should be used as a starting point when choosing C 5 s maximum ripple current rating (at 0Hz). Selecting the Power Setting Components The maximum average power delivered by the PFC stage is easily set using the following procedure:. Find the resistive divider ratio that results in the voltage at the V RMS pin being equal to.0v at the lowest line voltage. The voltage at this pin must be well filtered and yet able to respond well to transient line voltage changes. (4) (5) (6) IOUT ( C5) IRMS( C5) (7) ( IPEAK IRMS( C5) ) (7a) R4 0. π OT VRMS( MIN) (8) REV..0.3 /5/0

4 APPLICATION NOTE AN4009 The resistor and capacitor values in the typical example were found empirically to offer the lowest ripple voltage and still respond well to line voltage changes. Should a ratio be required which is greatly different from that found in equation 8, adjust the filter capacitor values according to equations 9 and 0. f 5Hz, f 3Hz R TOT R R 3 R 4 R C TOT 3 π fr ( R3 R4) R4OT R( R3 R4) C π fr 4. Find the constant of proportionality k m of the multiplier gain k in equation a. To obtain brown-out action below the lowest input voltage the maximum gain of the multiplier must be used when finding k M. The maximum gain (0.38) occurs when the V RMS input of the multiplier is.0v. Equation (ref) is the general expression for the multiplier gain versus the line voltage. k k M ( ref) () VRMS km k VRMS( MIN) (9) (0) R V k R MULO ( EAO 5. ) M 5 ( R)( POUT ) R5 ( 3500)( )( 099 ) ( 06)( 00) R Ω use 0. 5Ω R MULO multiplier output termination resistance (3.5k) (3) Voltage Loop Compensation Maximum transient response of the PFC section, without instability, is obtained when the open loop crossover frequency is one-half the line frequency. For this application the compensation components (pole/zero pair) are chosen so that the closed loop response decreases at 0dB/decade, crossing unity gain at 30Hz, then immediately decreasing at 40dB/ decade. The error amplifier pole is placed at 30Hz and an effective zero at one-tenth this frequency or 3Hz. First find the crossover frequency ( PS ) of the power stage. For reference, equation 5 finds the power stage pole, equation 6 the power stage DC gain. VBOOST R7 R8 5 FB.5 VEAO 6 R C9 km ( )( 80) km Now select the value of R which permits the greatest multiplier output current without saturating the output. The maximum output current of the multiplier is 00µA. k VRMS( MIN VEAO 5 R )(. ) R ( ) ( 80)( ) R 983kΩ use M Ω 4. Selecting the value of the current sense resistor completes the calculations for the power setting components. (a) () Figure. Voltage Amp Compensation PIN( AV) fc π VC5VEAO( MAX) C5 fc 00 ( )( )( 380)( 5. 3)( ) fc 58. 5Hz πrlc5 ( )( 7)( ) 63. Hz (4) (5) REV..0.3 /5/0 3

5 AN4009 APPLICATION NOTE V RL C5 POUT PS( DC) fc (. )(.) PS( DC) (. 63) PS ( DC) 50. (34.dB) Now the gain of the power stage at 30Hz is calculated. PS( 30Hz) f C 30. PS( 30Hz) PS( 30Hz).95 (5.8dB) The power stage gain will be attenuated by the resistive divider R 7 /R 8 according to equation 8. RDIV R 8 R7 R8 RDIV ( 37. ) ( ) RDIV ( 43.6dB) (6) (7) (8) The amount of error amplifier gain required to bring the open loop gain to unity at 30Hz is the negative of the sum of the power stage plus divider stage gain (attenuation): EA ( PS( 30) RDIV) π RfZ ( )( )(90K)( 3) 58nF ( use 56nF) () Since the pole frequency is ten times the zero frequency the pole capacitor C 9 will be one-tenth the value of C 8. C C C C9 5.6nF Current Loop Compensation The current loop is compensated exactly like the voltage loop with the exception of the choice of the open loop crossover frequency. To prevent interaction with the voltage loop, the current loop bandwidth should be greater than ten times the voltage loop crossover frequency but no more than onesixth the switching frequency or 6.7kHz. The power stage crossover frequency is found in equation 3, the pole frequency in 4 and for reference the power stage DC gain is found in equation K 0 ND IAC VEAO 3.5K 4 V REF IEAO R () EA (. 5 8 ( 43.)) 6 EA 37.8dB (77.6V / V) (9) 3 R5 I SENSE The value of R, which sets the high frequency gain of the error amplifier, can now be determined. R EA gm Figure 3. Current Amp Compensation R (0) R 95K use 90K Calculate C 8 which together with R sets the zero frequency at 3Hz. 4 REV..0.3 /5/0

6 APPLICATION NOTE AN4009 fc R5 VC5 T PRI VRAMP π ( ) ( P P) fc ( 0. 5)( 380 ) ( )( )( )(. 5) fc 4. khz (3) π R fz ( )( )( 36 03)( ) 6. nf( use 7. nf) The pole capacitor C 7 is one-tenth the value of C 6. (9) π RL C5 ( )( 7)( ) 63. H z same as equation 5 (4) The PWM Stage C pf (30) PS( DC) fc (. )(. ) PS( DC) (. 63) PS( DC) 099 ( 66.4dB) Find the gain of the power stage at 6.7kHz. f C PS( 6. 7kHz ) PS( 6. 7kHz ) PS( 6. 7kHz ) ( 6.8dB) The current loop contains no attenuating resistors so proceed to find the error amplifier gain in equation 7. EA ( PS( 6. 7kHz) ) EA ( 6. 8) EA 6.8dB (6.9V / V) Now determine the value of the current error amplifier setting resistor R. R EA gm R R 35. 4k use 36k (5) (6) (7) (8) Soft-Starting the PWM Stage The ML484 features a dedicated soft-start pin for controlling the rate of rise of the output voltage and preventing overshoot during power on. The controller will not initiate soft-start action until the PFC voltage reaches its nominal value thereby preventing stalling of the output voltage due to excessive PFC currents. Furthermore, PWM action will be terminated in the event that the ML484 loses power or if the PFC boost voltage should fall below 8V DC. The soft-start capacitor value (C 9 ) for 5ms of delay is found in equation 3. 6 C9 t 50 0 ( SS) 5. 6 C (. ) 5. C9 µ F Setting the Oscillator Frequency There are two versions of the ML484. The ML484- where the PFC and PWM run at the same frequency and ML484- where the PWM stage is X PFC frequency. (3) ML484- In general it is best to choose a small valued capacitor C to maximize the oscillator duty cycle (minimize the C discharge time). Too small a value capacitor can increase the oscillator s sensitivity to phase modulation caused by stray field voltage induction into this node. For the practical example a 470pF capacitor was first chosen for C. Equation 3 is accurate with values of R greater than 0k. 05. f C SW T Calculate the value of C 6 to form the zero at.6khz. 0. 5( 05)( ) (3) 4.k REV..0.3 /5/0 5

7 AN4009 APPLICATION NOTE Q D5 T L VOUT V, 6A D C4 C R4 R9 Q3 R0 D6 R3 U C R R6 C9 CT R ML IEAO IAC ISENSE VRMS SS VDC RAMP VEAO 6 VFB 5 REF4 VCC 3 VO VO ND 0 8 RAMP ILIM 9 D8 D9 D0 R0 R4 C3 C4 C5 C30 R C0 R5 T3 C5 R6 D7 R7 R8 SR C3 R5 C9 Figure 4. The PWM Stage ML484- The ML484- allows the user to operate the PWM stage at twice the PFC frequency, thereby reducing the physical size of the PWM stage magnetics and filter components. The PFC frequency is the same as the external oscillator frequency. The PWM frequency is formed by comparing the oscillator ramp voltage to internal voltage references which ideally make the duty cycle of the waveforms generated during each oscillator cycle identical. The PWM section duty cycle must be balanced to minimize phase jitter. This is accomplished by making the oscillator dead-time (C discharge time) equal to.5% of the total period. First choose the C value from equation 33. CT fsw Now R is found from equation (34) which is identical to equation fsw CT (33) (34) As a final test, an in-circuit check of adjacent PWM cycles should be examined for duty cycle balance. For more detail involving duty cycle balancing please refer to Application Note 34. Current Limit The PWM power stage operates in current mode using R 0 to generate the voltage ramp for duty cycle control. The ML484 limits the maximum primary current via an internal V comparator which when exceeded terminates the drive to the external power MOSFETs. Maximum primary current is: IPRI ( MAX) IPRI ( MAX) IPRI ( MAX) R0 05. Amps (35) Voltage Mode (Feed-Forward) Should voltage mode control be used it is necessary to know C 5 s peak voltage in order to choose the correct ramp generating components. Equation 36 finds the worse case peak to peak ripple voltage across C 5. To find the peak voltage divide the ripple voltage by two and add it to the regulated boost voltage. Remember that since the ML484 employs leading/ trailing modulation the actual peak to peak ripple voltage will generally be much less than the calculated value. V I R( C5) OUT ( C5) ESR( C5) 4 fc π L 5 (36) 6 REV..0.3 /5/0

8 APPLICATION NOTE AN4009 f L line frequency Solve equation 37 for the ramp resistor value. The ramp capacitor value should be in the range of 470pF 0000pF. Choose a resistor with an adequate voltage rating to withstand the boost voltage. RRAMP σ MAX ( ) V CRAMP fsw n REF VC5 0.5VR (37) σ (MAX) maximum PWM duty cycle (0.45 for the ML484-) V R peak to peak boost capacitor ripple voltage (equation 36) The Power Transformer Turns Ratio The minimum output voltage at the secondary of T is found in equation 38. VSEC( MIN) VSEC( MIN) VSEC( MIN) V OUT VF σ( MAX) Volts (38) The secondary voltage was chosen to be 30 volts to increase the output voltage hold up time. The transformer turns ratio is easily found from equation 39. NPRI V C5 NSEC VSEC( MIN) NPRI NSEC NPRI 38 : 3 NSEC (39) The maximum secondary current with the output shorted is limited by equation 40. ISEC( MAX) ISEC( MAX) IPRI( MAX) NPRI N SEC ()( 38) 3 (40) The output inductor and rectifier were chosen with maximum current ratings larger than the maximum secondary current. Output Filter Component Filter Selection L s value was chosen to efficiently minimize output ripple current thereby easing the ESR requirement of the filter capacitor. C s ESR value is the dominant contributor to the output ripple. The maximum ESR value required is found in equation 4. ESR( C) VRL f SW VSECσ ( MAX) V R peak to peak output ripple voltage (4) Output Voltage Compensation A LM43 shunt regulator SR and opto-isolator U perform output voltage setting and regulation. The opto crosses the primary to secondary safety boundary varying the voltage on the VDC pin to keep the output voltage constant against line and load changes. Using current mode control simplifies loop compensation leaving only a single pole and zero in the output stage. The pole is created from the output capacitor and equivalent load resistance. The zero is formed from the filter capacitor and its ESR. In this example, the action of the zero occurs well after the closed loop response has crossed unity, so it was not compensated with a pole. The output pole is canceled increasing the overall bandwidth by the addition of R 6 and C 3 which form a zero with LM43. For more information on using the LM43, including gain/phase versus frequency characteristics, please refer to the Texas Instruments Linear Data Handbook. 3.3V Output Design Changes The latest microprocessors and support circuitry require a 3.3V supply for proper operation. The ML484 is ideal for these applications including the energy efficient, ecologically friendly reen PC s. If the total output power required varies greatly from 00 watts it will be necessary to re-select certain components beginning with the PFC stage. T s turn ratio must be adjusted according to equation 39 and another low current secondary winding added using the same turns ratio as originally found for the volts. This second winding is necessary to power the LM43/opto circuit as the 3.3V output is not adequate to fully bias the feedback circuitry. C may be increased to reduce the output ripple voltage. The figure below displays a 3.3V output stage capable of supplying 6 amps. ISEC( MAX) 5. 3Amps REV..0.3 /5/0 7

9 AN4009 APPLICATION NOTE T µf400 L VOUT 3.3V, 6A D C4 C R3 U R6 C R 0.K C3 SR LM43 R5 3.6K Figure V Output Stage Note: For more information see Application Note REV..0.3 /5/0

10 REV..0.3 /5/0 9 Figure 6. Complete 00W Circuit AC INPUT 80 TO 64V Z3 Z4 C R5 Z Z R R R3 R4 C R7 T D4 C D3 C0 C3 C9 CT D C R R30 ML484 VEAO 6 VFB 5 REF4 VCC 3 VO VO ND 0 ILIM 9 IEAO IAC ISENSE VRMS SS VDC RAMP RAMP R R9 Q D C4 C5 D9 D8 D0 R7 R8 R0 C3 C4 C5 C30 R R4 C9 Q Q3 C0 R0 D5 R5 T D6 T3 D C5 R6 D7 L C4 R7 R8 C R3 U SR R4 R6 VOUT V, 6A C R C3 R5 APPLICATION NOTE AN4009

11 AN4009 APPLICATION NOTE DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIHT TO MAKE CHANES WITHOUT FUHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISIN OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIHTS, NOR THE RIHTS OF OTHERS. LIFE SUPPO POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPO DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. /5/0 0.0m 00 Stock#AN Fairchild Semiconductor Corporation

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